BR112017023286A2 - An integrated circuit die and method of manufacture - Google Patents
An integrated circuit die and method of manufactureInfo
- Publication number
- BR112017023286A2 BR112017023286A2 BR112017023286-3A BR112017023286A BR112017023286A2 BR 112017023286 A2 BR112017023286 A2 BR 112017023286A2 BR 112017023286 A BR112017023286 A BR 112017023286A BR 112017023286 A2 BR112017023286 A2 BR 112017023286A2
- Authority
- BR
- Brazil
- Prior art keywords
- layer
- heat radiation
- metal
- active device
- interconnection layer
- Prior art date
Links
Classifications
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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CN201510221081.2A CN104851860B (zh) | 2015-04-30 | 2015-04-30 | 一种集成电路管芯及制造方法 |
CN201510221081.2 | 2015-04-30 | ||
PCT/CN2016/080514 WO2016173507A1 (zh) | 2015-04-30 | 2016-04-28 | 一种集成电路管芯及制造方法 |
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BR112017023286-3A BR112017023286A2 (zh) | 2015-04-30 | 2016-04-28 | An integrated circuit die and method of manufacture |
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US (1) | US10607913B2 (zh) |
EP (1) | EP3282478A4 (zh) |
CN (2) | CN108281404A (zh) |
BR (1) | BR112017023286A2 (zh) |
WO (1) | WO2016173507A1 (zh) |
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CN108281404A (zh) * | 2015-04-30 | 2018-07-13 | 华为技术有限公司 | 一种集成电路管芯及制造方法 |
CN107579050B (zh) * | 2016-07-05 | 2019-11-15 | 慧隆科技股份有限公司 | 晶片封装体的制造方法 |
CN112652573A (zh) * | 2020-12-07 | 2021-04-13 | 海光信息技术股份有限公司 | 一种封装方法及芯片 |
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JPS62194652A (ja) * | 1986-02-21 | 1987-08-27 | Hitachi Ltd | 半導体装置 |
US6756670B1 (en) * | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
US5939739A (en) * | 1996-05-31 | 1999-08-17 | The Whitaker Corporation | Separation of thermal and electrical paths in flip chip ballasted power heterojunction bipolar transistors |
US20010018800A1 (en) * | 1999-09-17 | 2001-09-06 | George Tzanavaras | Method for forming interconnects |
US6970362B1 (en) * | 2000-07-31 | 2005-11-29 | Intel Corporation | Electronic assemblies and systems comprising interposer with embedded capacitors |
US6541303B2 (en) * | 2001-06-20 | 2003-04-01 | Micron Technology, Inc. | Method for conducting heat in a flip-chip assembly |
US7126218B1 (en) * | 2001-08-07 | 2006-10-24 | Amkor Technology, Inc. | Embedded heat spreader ball grid array |
US7095121B2 (en) * | 2002-05-17 | 2006-08-22 | Texas Instrument Incorporated | Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices |
US20050012225A1 (en) * | 2002-11-15 | 2005-01-20 | Choi Seung-Yong | Wafer-level chip scale package and method for fabricating and using the same |
US7169691B2 (en) * | 2004-01-29 | 2007-01-30 | Micron Technology, Inc. | Method of fabricating wafer-level packaging with sidewall passivation and related apparatus |
US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
CN1941346A (zh) * | 2005-09-29 | 2007-04-04 | 中国砂轮企业股份有限公司 | 高导热效率电路板 |
US9299634B2 (en) | 2006-05-16 | 2016-03-29 | Broadcom Corporation | Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages |
US9013035B2 (en) * | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
CN101026148A (zh) * | 2007-03-27 | 2007-08-29 | 日月光半导体制造股份有限公司 | 光电芯片的多芯片增层封装构造及其制造方法 |
JP5420274B2 (ja) * | 2009-03-02 | 2014-02-19 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US8492911B2 (en) * | 2010-07-20 | 2013-07-23 | Lsi Corporation | Stacked interconnect heat sink |
CN101980360B (zh) * | 2010-09-15 | 2012-08-29 | 日月光半导体制造股份有限公司 | 半导体结构及其制作方法 |
US9117786B2 (en) | 2012-12-04 | 2015-08-25 | Infineon Technologies Ag | Chip module, an insulation material and a method for fabricating a chip module |
CN203312281U (zh) * | 2013-06-21 | 2013-11-27 | 江阴长电先进封装有限公司 | 一种具有石墨烯层的芯片封装结构 |
US9472533B2 (en) * | 2013-11-20 | 2016-10-18 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming wire bondable fan-out EWLB package |
JP6235353B2 (ja) * | 2014-01-22 | 2017-11-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN203733779U (zh) * | 2014-01-23 | 2014-07-23 | 南通富士通微电子股份有限公司 | 半导体器件 |
US10381326B2 (en) * | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9496198B2 (en) * | 2014-09-28 | 2016-11-15 | Texas Instruments Incorporated | Integration of backside heat spreader for thermal management |
CN104465556B (zh) * | 2014-12-16 | 2017-09-29 | 通富微电子股份有限公司 | 晶圆封装结构 |
CN108281404A (zh) * | 2015-04-30 | 2018-07-13 | 华为技术有限公司 | 一种集成电路管芯及制造方法 |
US10217691B2 (en) * | 2015-08-17 | 2019-02-26 | Nlight, Inc. | Heat spreader with optimized coefficient of thermal expansion and/or heat transfer |
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CN104851860A (zh) | 2015-08-19 |
EP3282478A1 (en) | 2018-02-14 |
EP3282478A4 (en) | 2018-05-02 |
WO2016173507A1 (zh) | 2016-11-03 |
US10607913B2 (en) | 2020-03-31 |
US20180068922A1 (en) | 2018-03-08 |
CN104851860B (zh) | 2018-03-13 |
CN108281404A (zh) | 2018-07-13 |
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