BR112017023286A2 - An integrated circuit die and method of manufacture - Google Patents

An integrated circuit die and method of manufacture

Info

Publication number
BR112017023286A2
BR112017023286A2 BR112017023286-3A BR112017023286A BR112017023286A2 BR 112017023286 A2 BR112017023286 A2 BR 112017023286A2 BR 112017023286 A BR112017023286 A BR 112017023286A BR 112017023286 A2 BR112017023286 A2 BR 112017023286A2
Authority
BR
Brazil
Prior art keywords
layer
heat radiation
metal
active device
interconnection layer
Prior art date
Application number
BR112017023286-3A
Other languages
English (en)
Portuguese (pt)
Inventor
Fu Huili
Cai Shujie
Luo Feiyu
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of BR112017023286A2 publication Critical patent/BR112017023286A2/zh

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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
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    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/161Cap
    • H01L2924/1615Shape
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    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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CN112652573A (zh) * 2020-12-07 2021-04-13 海光信息技术股份有限公司 一种封装方法及芯片

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US10607913B2 (en) 2020-03-31
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