JPS62194652A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS62194652A
JPS62194652A JP61035105A JP3510586A JPS62194652A JP S62194652 A JPS62194652 A JP S62194652A JP 61035105 A JP61035105 A JP 61035105A JP 3510586 A JP3510586 A JP 3510586A JP S62194652 A JPS62194652 A JP S62194652A
Authority
JP
Japan
Prior art keywords
chip
bumps
mother chip
insulating film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61035105A
Other languages
English (en)
Inventor
Kunizo Sawara
佐原　邦造
Kanji Otsuka
寛治 大塚
Takashi Ishida
尚 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61035105A priority Critical patent/JPS62194652A/ja
Priority to US07/015,019 priority patent/US4764804A/en
Publication of JPS62194652A publication Critical patent/JPS62194652A/ja
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に当該装置における放
熱特性を改良する技術に関する。
〔従来の技術〕
半導体装置における熱設計の問題は重要であり、特に、
半導体素子（チップ）の沙数個を搭載するような消費電
力の大なるマルチチップモジュールにあってはその問題
は重要である。
当該マルチチップモジエールの構造例の一つとして本出
願人の提案になる次のようなものがある。
基板の下面にマザーチップを固鬼’Ｌ、該マザ・−チッ
プの下面に、いわゆるＣＣＢ（コンドロールド・コラッ
プス・リフロー・ポンディンり接続により、子チップを
多数固着し、前記基板とキャップとの間にリードフレー
ムを介装し、前記マザーチップと該リードフレームとを
コネクタワイヤにより電気的に結合し、前記基板の上面
に放熱フィンを取付けて成る主要構造を有するマルチチ
ップモジエールである。
このＣＣＢ接続には一般に、半田バンプ電極が使用され
る。なお、バンブ電極は、導電性のバンプで、マザーチ
ップと子チップとの間に信号をやりとりするものと、単
に子チップからの熱をマザーチップ、次いで、放熱フィ
ンを経由して放熱させるための放熱用バンプ（ダミーバ
ンプ）とがある。
従来、この放熱バンプ電極直下の絶縁膜は、一般にＳｉ
ｎ、　、　５ｉａＮ＋などより成る膜により構成されて
おり、熱伝導率が悪く、バンプの熱抵抗が大きく、特に
、上記のごｉきマルチチップモジュール就中パワーの大
きなマルチチップモジエールにおいてその放熱特性上問
題となっていた。
〔発明が解決しようとする問題点〕
本発明は、上記のごときマルチチップモジュールにおけ
る、半田ダミーバンプと連った絶縁膜ノ改良技術を提供
することを目的とし、放熱性の良好なマルチチップモジ
エールを提供することを目的とする。
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
〔問題点を解決するための手段〕
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
すなわち、半田ダミーバンプ電極直下のチップ側絶縁膜
を電子線気相法（ＣＶＤ）によって形成されるようなダ
イヤモンド絶縁薄膜により構成するようにしたものであ
る。
〔作用〕
上記した手段によれば、ダイヤモンド薄膜の絶縁性が高
くかつ、熱伝導率が大であることに応じテハワーの大な
る上記のごときマルチチップモジュールにあっても、放
熱特性を高めることができ、かつ、子チップとマザーチ
ップとの絶縁性をも確保できる。
〔実施例〕
次に、本発明を、図面に示す実施例に基づいて説明する
。
第１図は本発明による半導体装置（ＳｉｏｎＳｉ方式に
よるマルチチップモジュール）の断面図、第２図は同装
置の要部断面図である。
マザーチップ１の一方の面を、基板２にシリコンゴム系
接着剤などにより固着し、子チップ３の一方の面を当該
マザーチップ１の他方の面に半田バンプ４により固着す
る。
第２図は当該マザーチップ１と子チップ３との半田バン
プ４による接続部を拡大断面により示したもので、マザ
ーチップｌの半導体活性領域５の表面には例えばＳｉ３
Ｎ４　　よりなり絶縁膜６が被覆され、さらに、その表
面にＡ８電極配線７が敷設されている。半田バンプ４は
、図示左側の導電性バンプ８と放熱用バンプ（ダミーバ
ンプ）９とを有して成り、当該導電性バンプ８は、バリ
ヤー金属１０を介して、前記Ａ！電極配線７と接続し、
同様に構成された子チップ３との間で導通がとられる。
マザーチップ１０表面には、ダイヤモンド薄膜１１が形
成され、放熱用バンプ９は、接着用金属１２を介して、
当該ダイヤモンド薄膜１１に固着され、さらに同様に構
成された子チップ３と接続している。第１図に図示のよ
うに、マザーチップ１の端部とリードフレーム１２の端
部とをコネクタワイヤ１３により、ワイヤボンディング
する。
当該リードフレーム１２は、基板２とキャップ１４との
間に介装されている。なお、第１図にて、１５は封止材
を示す。
第１図に示すように、基板２のマザーチップ１を固着し
ている面の反対面に放熱フィン１６を取付けする。本発
明におけるダイヤモンド薄膜１１は、絶縁性能の面やそ
の形成スピードなどを考慮すると、公知の電子線ＣＶＤ
法（気相法）により形成することが好ましい。気相法の
他として、メタンと水素の混合ガスを適宜の圧力、加熱
温度下で反応させ、薄い膜状のダイヤモンドを作る方法
や、メタンガスに代えてアルコールなどの炭素。
水素、酸素を含む有機化合物を用い、これを液化させ、
水素とともに適宜温度下で反応させ、ダイヤモンド薄膜
を形成する方法などであっても差支えない。
本発明に用いられる子チップ３は、例えばシリコン単結
晶基板から成り、周知の技術によって当該チップ内には
多数の回路素子が形成され、１つの回路機能が与えられ
ている。回路素子の具体例は、例えばＭＯＳトランジス
タから成り、これらの回路素子によって例えばメモリや
論理回路の回路機能が形成されている。第１図にて、１
７は子チップ３０半導体活性領域を示す。
マザーチップ１も子チップ３と同様に、例えばシリコン
単結晶基板から成り、回路機能が構成されている。
半田バンブ４は、周知のフリップチップの接続端子とし
て用いられているようなものが適用され、例えばコンド
ロールドコラップスリフローチップの５ｎ−Ｐｂを用い
て半球状のバンブ（突起電極）を形成してなるものによ
り構成される。
バリヤー金属１０は、例えばＣｒ　／　Ｃｕ　／　Ａ　
ｕにより構成されている。
基板２は、例えばＳｉＣにより構成されている。
リードフレーム１２は、例えばＦｅ及びＣｕ系合金によ
り構成されている。
コネクタワイヤ１３は、例えばＡＡ細線により構成され
ている。
放熱フィン１６は、例えばＡｌにより構成されている。
本発明の上記実施例によれば、子チップ３０半導体活性
領域１７からの熱はダイヤモンド絶縁薄膜１１．放熱バ
ンブ９．マザーチップ１．基板２゜放熱フィン１５を経
由して、放熱され、その際、当該電子線ＣＶＤ法による
ダイヤモンド薄膜１１は熱伝導が良好であるので、放熱
特性の良いマザーチップモジュールを得ることができた
。
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。
例えば、上記実施例ではダイヤモンド薄膜」１をｓｉ、
Ｎ、　　なる絶縁膜６の上に被膜する例を示したが、こ
のように、絶縁膜の一部を当該ダイヤモンド薄膜により
置き換えるのではなく、絶縁膜全体を当該ダイヤモンド
薄膜により形成してもよい。
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である５ｉｏｎｓｉ方式に
よるマルチチップモジエールについて適用した場合につ
いて説明したが、それに限定されるものではなく、他の
半導体装置に広く適用することができる。
〔発明の効果〕
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。
すなわち、本発明によれば、放熱バンブによる半導体活
性領域からの放熱において、ダイヤモンドよりなる絶縁
膜を介して行うようにしたので、放熱特性が格段に向上
することができた。
【図面の簡単な説明】
図面は本発明の実施例を示し、第１図は本発明による半
導体装置の断面図、第２図は同要部断面図である。 ｌ・・・マザーチップ、２・・・基板、３・・・子チッ
プ、４・・・半田バンプ、訃・・半導体活性領域、６・
・・絶縁膜、７・・・Ａｐ電極配線、８・・・導電性バ
ンブ、９・・・放熱用バンブ、１０・・・バリヤー金属
、１１・・・ダイヤモンド薄膜、１２・・・リードフレ
ーム、１３・・・コネクタワイヤ、１４・・・キャップ
、１５・・・封止材、１６・・・放熱フィン、１７・・
・半導体活性領域。 代理人　弁理士　　小　川　勝　男 第　　１　　図 第　　２　　図

Claims (1)

  1. 【特許請求の範囲】 １、ダイヤモンドより成る絶縁膜を介して、半導体活性
    領域からの熱を、放熱用突起電極より放熱する構造を有
    して成ることを特徴とする半導体装置。 ２、ダイヤモンドより成る絶縁膜が、電子線気相法によ
    り形成されて成る、特許請求の範囲第１項記載の半導体
    装置。
JP61035105A 1986-02-21 1986-02-21 半導体装置 Pending JPS62194652A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61035105A JPS62194652A (ja) 1986-02-21 1986-02-21 半導体装置
US07/015,019 US4764804A (en) 1986-02-21 1987-02-17 Semiconductor device and process for producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61035105A JPS62194652A (ja) 1986-02-21 1986-02-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS62194652A true JPS62194652A (ja) 1987-08-27

Family

ID=12432650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61035105A Pending JPS62194652A (ja) 1986-02-21 1986-02-21 半導体装置

Country Status (2)

Country Link
US (1) US4764804A (ja)
JP (1) JPS62194652A (ja)

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