TWI248667B - Semiconductor package having heat pipes - Google Patents

Semiconductor package having heat pipes Download PDF

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TWI248667B
TWI248667B TW093136291A TW93136291A TWI248667B TW I248667 B TWI248667 B TW I248667B TW 093136291 A TW093136291 A TW 093136291A TW 93136291 A TW93136291 A TW 93136291A TW I248667 B TWI248667 B TW I248667B
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Taiwan
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semiconductor package
package structure
heat sink
wafer
heat
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TW093136291A
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Chinese (zh)
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TW200618221A (en
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Chang-Chi Lee
Tong Hong Wang
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Advanced Semiconductor Eng
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Publication of TW200618221A publication Critical patent/TW200618221A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor package includes a substrate, a chip, a thermally conductive adhesive, a heat spreader and at least one heat pipe. The chip is disposed on the substrate and has an active surface and a back surface opposite to the active surface, wherein the active surface is electrically connected to the substrate. The thermally conductive adhesive is used for mounting the back surface of the chip to the substrate. The heat spreader is mounted on the substrate. The heat pipe is mounted on the substrate and has an evaporator end and a condenser end, wherein the evaporator end is thermally coupled to the back surface of the chip and the condenser end is connected to the heat spreader.

Description

1248667 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體封裝構造，更特別有關於一 種半導體封裝構造，其晶片背面所產生的熱量可藉由至少 7熱官快速傳導至一散熱片逸散。 【先前技術】 隨著半導體封裝構造之主動及被動元件越密，其内部所 產生的熱S也越多。雖然該元件之表面本身就有散熱作 用’但就功率較高的元件而言，仍需要安置散熱片，以避 免工作溫度過高時，該半導體封裝構造的接合部份可能會 被損壞’以及該晶片可能會失效。 散熱塊球袼陣列（Heat Slug Ball Grid Array，HSBGA) 封裝構造係為一種塑膠球格陣列（plastic BaU Grid Array， PBGA)封叙構造之改良形式。其特徵係為將一片銅製散熱 塊内埋於該塑膠封裝構造之封膠體内。該散熱塊（Heat si%) 係企圖降低該塑膠球格陣列封裝構造（PBGA)之熱阻抗 (Thermal Resistance)，卻不改變其材料。一般而言，該散 熱塊球格陣列封裝構造（HSBGA)之熱阻抗約小於該塑膠1 格陣列封裝構造（PBGA)之熱阻抗20%，且在自然對流下， 該散熱塊球袼陣列封裝構造（HSBGA)可達到約5至的 熱散失（Thermal Dissipation)。該散熱塊球格陣列封裝構迕 (HSBGA)係可運用於晶片配置於基板上之任何形式的封裝 構造。對於高功率之封裝構造及高速度之晶片，諸如繪圖 晶片、通訊晶片及網路晶片而言，該散熱塊球袼陣列封裝 1248667 構造（HSBGA)係為-極佳之解決方法，用以散發該封裝構 造内部之晶片戶斤產生的熱量。1248667 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure in which heat generated on the back side of a wafer can be quickly conducted to at least one heat officer. The heat sink is dissipated. [Prior Art] As the active and passive components of the semiconductor package structure are denser, the amount of heat S generated therein is also increased. Although the surface of the component itself has a heat dissipation effect, but in the case of a higher power component, it is still necessary to dispose the heat sink to prevent the joint portion of the semiconductor package structure from being damaged when the operating temperature is too high. The wafer may fail. The Heat Slug Ball Grid Array (HSBGA) package structure is an improved form of a plastic BaB Grid Array (PBGA) seal structure. The utility model is characterized in that a piece of copper heat dissipating block is buried in the sealing body of the plastic packaging structure. The heat sink (Heat si%) attempts to reduce the thermal resistance of the plastic ball grid array package (PBGA) without changing its material. In general, the heat sink block array package structure (HSBGA) has a thermal impedance of less than about 20% of the thermal resistance of the plastic 1 array package structure (PBGA), and under natural convection, the heat sink ball array package structure (HSBGA) can achieve about 5 to the thermal dissipation (Thermal Dissipation). The heat slug ball grid array package (HSBGA) can be used in any form of package configuration in which the wafer is disposed on a substrate. For high power package construction and high speed wafers, such as graphics chips, communication chips and network chips, the thermal block ball grid array package 1248667 construction (HSBGA) is an excellent solution for distributing this The heat generated by the chip inside the package structure.

舉例而言，美國專利第6,400,014號，標題為“具有一 散熱片之半導體封裝構造（Semi_d⑽。r 佩AFor example, U.S. Patent No. 6,400,014, entitled "Semiconductor Package Construction with a Heat Sink (Semi_d(10).r Pei A

HeatSink)”，揭示—種半導體封裝構造2，如第丄圖所示， 其包含-基板H)、至少-晶片2G、—散熱片Μ及複數個 =電元件（Conductive Member)36或錫球。該晶片2〇係黏 著於該基板1G上，並電性連接於該基板1()。該散熱片 具有-平板部40及一支撐部32。該支撐部32係用以支撐 呑亥平板部4 0在一特定高唐，a令乂六上如丁 亏疋同戾以疋位该平板部40在該晶片 20之上方。該平板部4G具有—上表面仏及―下表面料。 5亥上表面4 2裸露於一封膠體3 5¾冰，n T胗體38外，且該封膠體38係用以 封裝該晶片20及該散熱片3G。該下表面44係相對於該上 表面42’並具有一增厚部分46形成於相對於晶片2〇處， 且該增厚部分46之一端表面具有複數個流道（Fl〇w Channe—’其中-間隙34係形成於該增厚料牝之該 端表面與該晶片20之間。該導電元件 Member)36係連接該基板1〇,用以將該晶片電性連接於一 外部元件。再舉例而言’美國專利第6,433,42〇號，標題為 “具有透氣孔之散熱片的半導體封I構造（ — “π Package With A Heat Sink Having Air Vent)”，揭示一種半 導體封裝構造50,如第2圖所示，其包含—基板6〇、至少 一晶片7〇、一散熱片80、複數個導電元件（Conducive Members及一封膠體88。該晶片7〇係黏著於該基板6〇 上，並電性連接於該基板60。該散熱片8〇具有一平板部 1248667 及複數個支撐部82,其中該平板部 錐形之透氣孔92,該透氣孔 成：至〉、- 7〇及一宕M rW ou 見開口面向該晶片 乍開口相對於該寬開口，且該支撐 撺該平板部9〇,並定位該平板部9〇在該晶片7。之上方 :=::(C〇nductive 一)86係固定於該基板6。用 7。：連接於一外部元件。該封膠體吻以封 片 '及該散熱片80,其中部份之該散熱片8〇及該 乳孔92之该窄開口係裸露於該封膠體88外。 然而’由於該晶片所產生的熱量僅能藉由裸露於該封膠 外之該散熱片逸散’且該封膠體通常具有較低之熱傳係 數亦即不易散熱，因此將無法滿足具有高散熱需求、高 功率或高速度之半導體晶片’諸如繪圖晶片、通訊晶片及 網路晶片。 先萷技術已發展將熱管（heat pipe)應用於半導體封裝構 ^其中鑪熱管係為一種藉由毛細作用（capillary action)將 液體回流至蒸發器之蒸發器/冷凝器裝置。該熱管係為一中 空管，其管壁上具有多層濾網。當該熱管之一端被加熱（亦 即，吸熱端）且另一端被冷卻（亦即，冷卻端）時，則熱管之 工作流體（working fluid)係於吸熱端被蒸發且係於冷卻端 被冷凝。該熱管之工作流體於吸熱端接收熱量，藉由蒸發 作用產生工作流體之相改變（phase change)而形成氣相的 工作流體，因此該氣相的工作流體將熱量傳導至冷卻端。 該氣相的工作流體於冷卻端釋放熱量，藉由冷凝作用產生 工作流體之相改變而形成液相的工作流體，因此該液相的 工作流體將可用以吸收吸熱端之熱量。 1248667HeatSink)" discloses a semiconductor package structure 2, as shown in the figure, comprising - substrate H), at least - wafer 2G, heat sink Μ and a plurality of = Conductive Member 36 or solder balls. The wafer 2 is adhered to the substrate 1G and electrically connected to the substrate 1 (). The heat sink has a flat portion 40 and a support portion 32. The support portion 32 is used to support the flat portion 4 0 In a specific Gaotang, a 乂 上 上 如 如 如 该 该 该 该 该 该 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板 平板The surface 42 is exposed to a colloid 3 53⁄4 ice, outside the n T body 38, and the encapsulant 38 is used to encapsulate the wafer 20 and the heat sink 3G. The lower surface 44 is opposite to the upper surface 42'. A thickened portion 46 is formed at a position relative to the wafer 2, and one end surface of the thickened portion 46 has a plurality of flow paths (Fl〇w Channe-'where the gap 34 is formed in the thickened material The end surface is between the wafer 20. The conductive element 36 is connected to the substrate 1 to electrically connect the wafer to the Further, for example, U.S. Patent No. 6,433,42, entitled "Split Package With A Heat Sink Having Air Vent", discloses a semiconductor package. The structure 50, as shown in FIG. 2, comprises a substrate 6A, at least one wafer 7A, a heat sink 80, a plurality of conductive members (Conducive Members and a gel 88). The wafer 7 is adhered to the substrate. 6 ,, and electrically connected to the substrate 60. The heat sink 8 has a flat portion 1248667 and a plurality of support portions 82, wherein the flat portion has a tapered venting opening 92, the venting hole is: to >, - 7〇 and a 宕M rW ou see the opening facing the wafer opening relative to the wide opening, and the support 撺 the flat portion 9〇, and positioning the flat portion 9 above the wafer 7. Above:=::( C〇nductive A) 86 is fixed on the substrate 6. It is connected to an external component by a 7. The seal is kissed to seal the film 'and the heat sink 80, and a part of the heat sink 8 and the milk hole The narrow opening of 92 is exposed outside the encapsulant 88. However, due to the wafer The heat generated can only be dissipated by the heat sink exposed outside the sealant and the sealant usually has a low heat transfer coefficient, that is, it is not easy to dissipate heat, so it cannot meet the high heat dissipation requirement, high power or high. Speed semiconductor wafers such as graphics wafers, communication chips and network chips. Advanced technology has developed the use of heat pipes in semiconductor package structures where the furnace heat pipe system is a means of recirculating liquid by capillary action. To the evaporator/condenser unit of the evaporator. The heat pipe is a hollow pipe having a plurality of screens on the pipe wall. When one end of the heat pipe is heated (ie, the endothermic end) and the other end is cooled (ie, the cooling end), the working fluid of the heat pipe is evaporated at the endothermic end and is condensed at the cooling end. . The working fluid of the heat pipe receives heat at the endothermic end, and a phase change of the working fluid is generated by evaporation to form a working fluid of the gas phase, so that the working fluid of the gas phase conducts heat to the cooling end. The working fluid of the gas phase releases heat at the cooling end, and a phase change of the working fluid is generated by condensation to form a working fluid in the liquid phase, so that the working fluid of the liquid phase can be used to absorb the heat of the endothermic end. 1248667

另外，美國專利第5·，161，090號，標題為“用於晶片模 組之熱管電性連接整合（Heat Pipe_Electrical Interc〇nneQ integration for Chip Module ，揭示一種方法及裝置，其 用以控制至少一晶片之溫度，該晶片係位於一基板之表面 上，並用以提供複數條電性連接線於該晶片之間。該電性 連接線之一者或特定一組係設於該基板内，連接於該晶片 之電性70件，並且連接於高電性及導熱性柱材。該柱材係 設於該基板内，並直接熱性接觸於一熱管内之工作流體。 該熱管係被包封且設於該基板之内部，並電性及熱心觸 於該晶片之電性元件，諸如銲錫凸塊㈣化Μ — )。該埶 管之工作流體經由該導熱性柱材接收來自該電性元件之熱 量，藉由熱吸收產生工作流體之相改變（phasechange)，因 此將熱量傳導至位於另-處之散熱片。然@，由於該熱管 係設於該基板之㈣，因此將使得該基板㈣複雜化而影 響電路配置。再者’當該熱管被設於該基板之内部且該基 板係成形後’該基板將只具有一種熱管配置，％無法因應 不同晶片配置進行增加或減少熱管的數目或配置。 因此’便有需要提供一種半導體封裝構造，能夠解決前 述的缺點。 【發明内容】 本發明之-目的在於提供—種半導體封裝構造，其晶片 背面所產生的熱量可藉由至少―熱管快速傳導至一散 逸散。 為達上述目的，本發明接也 ..._ ^ 乃徒供一種半導體封裝構造包含一 1248667 載板、-晶片、一導熱性黏膠、一散熱片及至少—熱管。 該晶片係配置於該載板上，並具有相對之一主動表面、=一 背面’其中該主動表面係電性連接於該载板。該導熱= 膠係用以將該晶片之該背面固定於該載板上。該熱管係： 定於該載板上，並具有—吸熱端及一冷卻端，#中㈣ :係熱耦合於該晶片之該背面’且該冷卻端係連接於該散 熱片。 本發明之封裝構造，其晶片背面所產生的熱量可藉由該 熱管快速傳導至該散熱片逸散，因此可滿^具有高散敎需 求、高功率或高速度之半導體曰曰“，諸如繚圖晶片、通訊 晶片及網路晶片。再者’由於該熱管並非設於該基板之内 部，因此可適應不同晶片配置進行增加或減少熱管的數目 或配置 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯，下文將配合所附圖示，作詳細說明如下。 【實施方式】 參考第3 a及3 b圖，農_ ; 4日访丄a 0 八…員不根據本發明之一實施例之半 導體封裝構造，諸如球格陳別4 K柘1皁列封裝構造ί 〇〇。該球格陣列 封 1 構造 1 0 0 包含 一 ^ ic / j. 匕各戰扳（啫如，基板110)、一晶片120、 一散熱片130及至少一赦營#曰H / …、b 140。该晶片12〇係配置於該 基板110上，並具有柏斜> 祁對之一主動表面124及一背面126 及複數個接塾12 8位於贫士知生 my、4主動表面114上。該背面U6係 藉由一導熱性黏膠127固定於該基板U0 _L。該接塾128 係藉由複數條料122電性連接於該基板m之導電線路 1248667 (圖中未示）。該散熱片130係於該基板11〇上界定一处門 13[且-封膠體138係填封該空間…。複數個錫球 136係用以將該基板11〇之導電線路電性連接於一外部電 路板（圖中未示）。該散熱片13〇係藉由習知黏接或銲接方 ^固定於該基板110上。該黏接方式係藉由一黏膠（圖中未 不）黏著於該基板110上。該銲接方式係藉由一銲錫（圖中 未不）銲接於該基板110上之銲墊（圖中未示）上。 再參考第3b圖，該熱管140(諸如四個熱管）係固定於該 基板110上，諸如藉由黏膠（圖中未示）固定於該基板 上。本發明所屬技術領域中具有通常知識者可知，該熱管 140之配置須視熱散失需求、晶片數目及該基板之電路配 置等而定，並避免干擾銲線122配置。該熱管14〇係為一 種藉由毛細作用（capillary acti〇n)將液體回流至蒸發器之 蒸發器/冷凝器裝置，其具有一吸熱端142及一冷卻端144 分別位於該熱管1 40之兩端。該吸熱端丨42係熱耦合於該 晶片120之背面126，於本實施例中，其係可延伸至該導 熱性黏膠127内，以連接於該晶片12〇之背面126。該冷 部端144係連接於該散熱片13〇，諸如穿入該散熱片ι3〇 内’用以增加導熱接觸面積。該冷卻端14 4亦可藉由一導 熱性黏膠（圖中未示）黏著於該散熱片130。 當該熱管之吸熱端被加熱且冷卻端被冷卻時，則熱管内 之工作流體（working fluid)係於吸熱端被蒸發且係於冷卻 端被冷凝。該熱管之工作流體於吸熱端接收熱量，藉由蒸 發作用產生工作流體之相改變（phase change)而形成氣相 的工作流體’因此該氣相的工作流體將熱量傳導至冷卻 1248667 端。该亂相的工作流體於冷卻端釋放熱量，藉由冷凝作用 產生工作流體之相改變而形成液相的工作流體，因此該液 相的工作流體將可用以吸收吸熱端之熱量。 本發明之封裝構造，其晶片背面所產生的熱量可藉由該 熱官快速傳導至裸露於該封膠體外之散熱片逸散，因此可 “足具有高散熱需求、高功率或高速度之半導體晶片，諸 如、、、曰圖曰曰片、通訊晶片及網路晶片。再者，由於該熱管並 非。又於。亥基板之内部，因此可適應不同晶片配置進行增加 或減少熱管的數目或配置。 _ 參考第4圖，其顯示根據本發明之一替代實施例之半導 體封裝構造100，。該半導體封裝構造1〇〇，大體上類似於該 半導體封裝構^ 100,其中相似的元件標示相似的標號。 口亥封裝構造100’另&含一輔助散熱# 131，諸如銅製金屬 片。該輔助散熱M m II由習知黏接或銲接方式固定於該 基板110上。該晶片12〇之背面126係藉由一導熱性黏膠 127固定於該輔助散熱片131上。該熱管140具有一吸熱 端142及一冷卻端144分別位於該熱管14〇之兩端。該吸 # 熱端140係連接於該輔助散熱片131，諸如穿入該辅助散 熱片131内，用以增加導熱接觸面積。本發明所屬技術領 域中具有通常知識者可知，該吸熱端係可配置於該晶片之 背面與該輔助散熱片之間，或者該吸熱端係可配置於該輔 助散熱片與該基板之間。 本發明之封裝構造，其晶片背面所產生的熱量可先藉由 輔助散熱片傳導至熱管’然後藉由該熱管快速傳導至裸露 11 1248667 於該封膠體外之散熱片逸散’因此可滿足具有高散熱需 求、南功率或尚速度之半導體晶片。 參考第5a及5b圖，其顯示根據本發明之另一實施例之 半導體封裝構造200。該半導體封裝構造2〇〇包含一載板， 諸如導線架（lead frame)220 ’用以承載一晶片21〇。該導線 架220包含複數條外引腳222、内引腳224、一晶片承座 226及複數條支撐肋條228。該晶片210係藉由一導熱性黏 膠214 ’固定於該晶片承座226。該支撐肋條228係連接於 該晶片承座226。該導線架220之外引腳222係用以電性 連接至一外部電路板（圖中未示）。該晶片21〇具有一主動 表面2 11、一背面2 12及複數個接墊2 1 8位於該主動表面 211上。複數個接墊218係藉由複數條銲線（b〇nding wire)216電性連接至該導線架22〇之内引腳224。 至少一熱管240(諸如四個熱管）係固定於該晶片承座 226上’諸如藉由黏膠固定於該晶片承座226上。該熱管 240，諸如L狀熱管，具有一吸熱端242及一冷卻端244 分別位於該熱管24〇之兩端。該吸熱端242係連接於該晶 片210之背面212及該晶片承座226之上表面227，且延 伸至該導熱性黏膠214内。該冷卻端244係連接於_散熱 片230 °該散熱片230係可固定於該晶片承座226上，並 位於"亥曰曰片2 1 0及該晶片承座2 2 6之下方。該晶片2 1 〇、 该晶片承座226、該導線架之内引腳224、複數條銲線216 及熱官240係包覆於一封膠體230中。 本發明之封裝構造，其晶片背面所產生的熱量可藉由熱 12 1248667 管快速傳導至一散熱片逸散，因此可滿足具有高散熱需 求、高功率或高速度之半導體晶片。 芩考第6圖，其顯示根據本發明之一替代實施例之半導 體封裝構造200,。該半導體封裝構造200,大體上類似於該 半&體封裝構造2 0 0 ’其中相似的元件標示相似的標號。 至少一熱管240,係固定於該晶片承座226上。該熱管24〇, 具有一吸熱端242及一冷卻端244分別位於該熱管24〇,之 兩端。該吸熱端242係連接於該晶片承座226之下表面 229+，諸如藉由導熱性黏膠225連接於該晶片承座2%，且 緊鄰於該晶片21G附近。該冷卻端244係連接於_散熱片 230 ’諸如環狀散熱片。該散熱# 23〇，係彳固定於該晶片 承座226上，並位於該晶片21()及該晶片承座咖之下方。 本發明之封裝構造，並曰ΰI , 管快球值逡昼一 八曰曰片月面所產生的熱量可藉由熱 欠、」 一散熱片逸散，因此可滿足具有高散埶需 求、面功钱高速度之半導體晶[ 而 發明以前述實施例揭示’然其並非用以限定本 ι月#何本發明所屬技術本 脫離本發明之精神 ：識者，在不 口此本發明之保護範圍 …文。 為準。 7 <甲自月專利耗圍所界定者 圖 【圖式簡單說明】 第1圖為先 爾技術之一球袼陣列封裝構造 之剖面示意 第2圖為先前技術 之另 球袼陣列封裝構造 之剖面示 1248667 意圖。 之一實施例之封裝構造之剖面及 第3a及3b圖為本發明 上視示意圖。 第4圖為本發明之一 之剖面示意圖。 第5a及5b圖為本發 及上視示意圖。 替代實施例之球袼陣列封裝構造 明之另一 實施例之封裝構造 之剖面 第6圖為本發明之一替代實施例之具有導線架 構造之剖面示意圖。 /、于裝In addition, U.S. Patent No. 5,161,090, entitled "Heat Pipe_Electrical Interc〇nneQ integration for Chip Module, discloses a method and apparatus for controlling at least one The temperature of the wafer is located on a surface of a substrate and is used to provide a plurality of electrical connection lines between the wafers. One or a specific group of the electrical connection lines are disposed in the substrate and connected to The wafer is electrically 70 pieces and is connected to the high-electricity and thermal conductivity column. The column is disposed in the substrate and directly in thermal contact with the working fluid in a heat pipe. The heat pipe is encapsulated and provided. Inside the substrate, electrically and thermally contacting the electrical component of the wafer, such as a solder bump (4), the working fluid of the manifold receives heat from the electrical component via the thermally conductive pillar By heat absorption, a phase change of the working fluid is generated, thereby transferring heat to the heat sink located at another location. However, since the heat pipe is provided on the substrate (four), the base will be made (4) Complicating and affecting the circuit configuration. Furthermore, 'When the heat pipe is disposed inside the substrate and the substrate is formed, the substrate will have only one heat pipe configuration, and % cannot increase or decrease the number of heat pipes according to different wafer configurations. Therefore, there is a need to provide a semiconductor package structure that can solve the aforementioned disadvantages. SUMMARY OF THE INVENTION The present invention is directed to providing a semiconductor package structure in which heat generated on the back side of a wafer can be at least "heat pipe" In order to achieve the above object, the present invention is also provided in a semiconductor package structure comprising a 1248667 carrier, a wafer, a thermal conductive adhesive, a heat sink and at least a heat pipe. The wafer is disposed on the carrier and has a pair of active surfaces, a front surface, wherein the active surface is electrically connected to the carrier. The thermal conductivity is used to fix the back surface of the wafer. On the carrier board, the heat pipe system is defined on the carrier board and has a heat absorption end and a cooling end, #中(4): is thermally coupled to the back surface of the wafer And the cooling end is connected to the heat sink. The package structure of the present invention, the heat generated by the back surface of the wafer can be quickly transmitted to the heat sink by the heat pipe, so that the heat dissipation requirement can be high. Power or high-speed semiconductors, such as patterned wafers, communication chips, and network chips. Furthermore, since the heat pipe is not disposed inside the substrate, the number or configuration of the heat pipes can be increased or decreased to accommodate different wafer configurations. To make the above and other objects, features, and advantages of the present invention more apparent, the following will be The attached drawings are described in detail below. [Embodiment] Referring to Figures 3a and 3b, the invention is not a semiconductor package structure according to an embodiment of the present invention, such as a ball grid 4 K柘1 soap column package. Construct ί 〇〇. The ball grid array 1 structure 1 0 0 includes a ^ ic / j. 匕 each warp (for example, the substrate 110), a wafer 120, a heat sink 130, and at least one camp #曰H / ..., b 140 . The wafer 12 is disposed on the substrate 110 and has a pair of active surfaces 124 and a back surface 126 and a plurality of interfaces 12 8 on the poor active surface 4 of the poor. The back surface U6 is fixed to the substrate U0_L by a thermally conductive adhesive 127. The interface 128 is electrically connected to the conductive line 1248667 (not shown) of the substrate m by a plurality of strips 122. The heat sink 130 defines a door 13 on the substrate 11 (and the sealant 138 seals the space. A plurality of solder balls 136 are used to electrically connect the conductive lines of the substrate 11 to an external circuit board (not shown). The heat sink 13 is fixed to the substrate 110 by conventional bonding or soldering. The bonding method is adhered to the substrate 110 by an adhesive (not shown). The soldering method is soldered to a pad (not shown) on the substrate 110 by a solder (not shown). Referring again to Figure 3b, the heat pipe 140 (such as four heat pipes) is attached to the substrate 110, such as by an adhesive (not shown). It will be appreciated by those of ordinary skill in the art that the configuration of the heat pipe 140 depends on the heat dissipation requirements, the number of wafers, and the circuit configuration of the substrate, and avoids interference with the configuration of the bond wires 122. The heat pipe 14 is an evaporator/condenser device for returning liquid to the evaporator by capillary action, and has a heat absorption end 142 and a cooling end 144 respectively located at the heat pipe 140 end. The heat sink end 42 is thermally coupled to the back side 126 of the wafer 120. In this embodiment, it extends into the heat conductive adhesive 127 to be coupled to the back side 126 of the wafer 12. The cold end 144 is attached to the heat sink 13 〇, such as into the heat sink ι3 用以 to increase the thermal contact area. The cooling end 14 4 can also be adhered to the heat sink 130 by a heat conductive adhesive (not shown). When the endothermic end of the heat pipe is heated and the cooling end is cooled, the working fluid in the heat pipe is evaporated at the endothermic end and condensed at the cooling end. The working fluid of the heat pipe receives heat at the endothermic end, and a phase change of the working fluid is generated by evaporation to form a working fluid of the gas phase. Thus, the working fluid of the gas phase conducts heat to the end of the cooling 1248667. The chaotic phase of the working fluid releases heat at the cooling end, and a phase change of the working fluid is generated by condensation to form a working fluid in the liquid phase, so that the working fluid of the liquid phase can be used to absorb the heat of the endothermic end. In the package structure of the present invention, the heat generated by the back surface of the wafer can be quickly transmitted to the heat sink exposed outside the sealant by the heat, so that the semiconductor can have a high heat dissipation requirement, high power or high speed. Wafers, such as,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Referring to Figure 4, there is shown a semiconductor package construction 100 in accordance with an alternate embodiment of the present invention. The semiconductor package construction is substantially similar to the semiconductor package structure 100, wherein similar components are labeled similarly The envelope assembly 100's & includes an auxiliary heat sink #131, such as a copper metal sheet. The auxiliary heat sink M m II is fixed to the substrate 110 by conventional bonding or soldering. The 126 is fixed to the auxiliary heat sink 131 by a thermal conductive adhesive 127. The heat pipe 140 has a heat absorbing end 142 and a cooling end 144 respectively located at the two ends of the heat pipe 14〇. The heat sink 140 is connected to the auxiliary heat sink 131, such as into the auxiliary heat sink 131, for increasing the thermal contact area. It is known to those skilled in the art that the heat sink end can be configured. Between the back surface of the wafer and the auxiliary heat sink, or the heat absorbing end can be disposed between the auxiliary heat sink and the substrate. The package structure of the present invention can generate heat from the back surface of the wafer by auxiliary heat dissipation. The sheet is conducted to the heat pipe 'and then quickly conducted to the bare 11 1248667 by the heat pipe to dissipate the heat sink outside the sealant', thus meeting the semiconductor wafer with high heat dissipation requirement, south power or speed. Refer to Figures 5a and 5b A semiconductor package structure 200 in accordance with another embodiment of the present invention is shown. The semiconductor package structure 2 includes a carrier, such as a lead frame 220' for carrying a wafer 21. The lead frame 220 A plurality of outer leads 222, inner leads 224, a wafer holder 226 and a plurality of support ribs 228. The wafer 210 is fixed to the wafer by a thermal adhesive 214' The support rib 228 is connected to the wafer holder 226. The lead 222 outside the lead frame 220 is electrically connected to an external circuit board (not shown). The chip 21 has An active surface 2 11 , a back surface 2 12 and a plurality of pads 2 1 8 are located on the active surface 211. The plurality of pads 218 are electrically connected to the wires by a plurality of bonding wires 216 The inner leg 224 of the frame 22 is open. At least one heat pipe 240 (such as four heat pipes) is fixed to the wafer holder 226, such as by being glued to the wafer holder 226. The heat pipe 240, such as an L shape The heat pipe has a heat absorbing end 242 and a cooling end 244 respectively located at two ends of the heat pipe 24〇. The heat absorbing end 242 is connected to the back surface 212 of the wafer 210 and the upper surface 227 of the wafer holder 226 and extends into the thermal conductive adhesive 214. The cooling end 244 is connected to the heat sink 230. The heat sink 230 is fixed to the wafer holder 226 and is located below the "chip" 210 and the wafer holder 2266. The wafer 2 1 〇, the wafer holder 226, the inner lead 224 of the lead frame, the plurality of bonding wires 216 and the thermal officer 240 are wrapped in a colloid 230. In the package structure of the present invention, the heat generated on the back surface of the wafer can be quickly conducted to a heat sink by the heat 12 1248667 tube, thereby satisfying the semiconductor wafer having high heat dissipation demand, high power or high speed. Referring to Figure 6, there is shown a semiconductor package structure 200 in accordance with an alternate embodiment of the present invention. The semiconductor package construction 200 is generally similar to the half & body package construction 200' where similar elements are numbered similarly. At least one heat pipe 240 is fixed to the wafer holder 226. The heat pipe 24 〇 has a heat absorbing end 242 and a cooling end 244 respectively located at the ends of the heat pipe 24 。. The heat absorbing end 242 is attached to the lower surface 229+ of the wafer holder 226, such as 2% to the wafer holder by a thermally conductive adhesive 225, and in the immediate vicinity of the wafer 21G. The cooling end 244 is coupled to a heat sink 230' such as an annular heat sink. The heat sink is fixed on the wafer holder 226 and located below the wafer 21 () and the wafer holder. According to the package structure of the present invention, the heat generated by the moonball surface of the tube can be dissipated by the heat sink and the heat sink, so that the surface can meet the demand of high heat dissipation. The present invention is not limited to the scope of the present invention. Text. Prevail. 7 <A from the patent definition of the monthly patent consumption [simplified diagram] Figure 1 is a cross-sectional schematic diagram of one of the technology of the ball-on-array package. Figure 2 shows the structure of the ball-on-array package of the prior art. The section shows 1248667 intent. The cross-section of the package structure of one embodiment and the third and third views are schematic views of the present invention. Figure 4 is a schematic cross-sectional view showing one of the inventions. Figures 5a and 5b are schematic views of the present invention and the top view.袼 袼 Array Package Structure of Alternative Embodiment Section of Package Structure of Another Embodiment FIG. 6 is a cross-sectional view of a lead frame structure in accordance with an alternative embodiment of the present invention. /, in the loading

【主要元件符號說明】 2 半導體封裝構造 10 基板 20 晶片 28 側邊 30 散熱片 32 支撐部 34 間隙 36 導電元件 38 封膠體 40 平板部 42 上表面 44 下表面 46 增厚部分 48 流道 50 半導體封裝構造 60 基板 70 晶片 78 側邊 80 散熱片 82 支撐部[Main component symbol description] 2 Semiconductor package structure 10 Substrate 20 Wafer 28 Side 30 Heat sink 32 Support portion 34 Gap 36 Conductive member 38 Sealant 40 Flat portion 42 Upper surface 44 Lower surface 46 Thickened portion 48 Flow path 50 Semiconductor package Construction 60 substrate 70 wafer 78 side 80 heat sink 82 support

14 導電元件 88 封膠體 平板部 92 透氣孔 封裝構造 10(T 封裝構造 基板 晶片 122 銲線 主動表面 126 背面 導熱性黏膠 128 接墊 散熱片 131 輔助散熱片 空間 136 錫球 封膠體 140 熱管 吸熱端 144 冷卻端 封裝構造 20(Γ 封裝構造 晶片 211 主動表面 背面 214 導熱性黏膠 銲線 218 接墊 導線架 222 外引腳 内引腳 225 導熱性黏膠 晶片承座 227 上表面 支撐肋條 229 下表面 散熱片 230, 散熱片 封膠體 240 熱管14 Conductive component 88 Sealant flat part 92 Vented hole package structure 10 (T package structure substrate wafer 122 Bonded wire active surface 126 Back surface thermal conductive adhesive 128 Pad heat sink 131 Auxiliary heat sink space 136 Tin ball sealant 140 Heat pipe heat sink end 144 Cooling End Package Construction 20 (Γ Package Structure Wafer 211 Active Surface Back 214 Thermally Conductive Bonded Wire 218 Pad Lead Frame 222 Outer Pin Inner Pin 225 Thermally Conductive Silicone Holder 227 Upper Surface Support Rib 229 Lower Surface Heat sink 230, heat sink sealant 240 heat pipe

15 1248667 240’熱管 242 吸熱端 244 冷卻端15 1248667 240' heat pipe 242 endothermic end 244 cooling end

1616

Claims (1)

1248667 十、申請專利範圍： 1、一種半導體封裝構造，包含： 一載板； -晶片，配置於該載板上，該晶片係具有相對之一主 ，動表面及一背面，其中該主動表面係電性連接於該載 板， 散熱片；以及 至少一熱管，固定於該载板上，並具有一吸熱端及— 冷卻端’其中該吸熱端係熱耗合於該晶片之該背面，且 該冷卻端係連接於該散熱片。 2 依申請專利範圍第1項之半導體封裝構造，另包含-導 熱性黏膠，用以將該晶片之該背面固定於該載板上。 3、 ,申請專利範圍第2項之半導體封裝構造，其中該吸熱 端係延伸至該導熱性黏膠内。 4、 依申請專利範圍第i項之半導體封|構造，其中該冷卻 端係穿入該散熱片内，用以增加導熱接觸面積。 5、 :申請專利範圍第！項之半導體封裝構造，另包含一導 …性黏膠’用以將該冷卻端黏著於該散熱片。 6、 依申請專利範圍第1 係m 料構造，其中該載板 7、 依申請專利範圍第6項之半導體封I構造，立中 片係固定於該基板上，並位於 "^ ‘、、、 1徂y…亥日日片及該基板之上方。 17 1248667 依I明專利乾圍第6項之半導體封裝構造，另包含—輔 、、片配置於该基板與該晶片之間，其中該吸熱端係 連接於該輔助散熱片。 9't申Ϊ專利範圍第8項之半導體封裝構造，其中該吸熱 '端係牙入忒輔助散熱片内，用以增加導熱接觸面積。 10、 依申請專利範圍第8項之半導體封裝構造，其中該輔 助政熱片係為一金屬片。 11、 依中請專利範圍第1G項之半導體封裝構造，其中該 輔助散熱片係為鋼製金屬片。 12、 依申請專利範圍第1項之半導體封裝構造，其中該載 板係為一線架，並包含一晶片承座及複數條支撐肋條 連接於該該晶片承座。 13、 卫依申請專利範圍第12項之半導體封裝構造，其中該 月欠.、'、片係固定於該晶片承座上，並位於該晶片及該晶片 承座之下方。 14 種半導體封裝構造，包含： 一載板； 一輔助散熱片，固定於該載板上； 曰曰片，配置於該載板上，該晶片係具有相對之一主 2表面及一背面，其中該主動表面係電性連接於該載 一散熱片；以及 至少一熱管，固定於該載板上，並具有一吸熱端及一 18 1248667 15 冷卻端，其中該吸熱端係、連接於該辅 卻端係連接於該散熱片。 助散熱片 且該冷 上 ===== 利範圍第14項之半導體封褒構造，其㈠ 而係牙入該散熱片内，用以增加導熱接觸面積。1248667 X. Patent application scope: 1. A semiconductor package structure comprising: a carrier board; a wafer disposed on the carrier board, the wafer system having a relative main surface, a moving surface and a back surface, wherein the active surface system Electrically connected to the carrier, a heat sink; and at least one heat pipe fixed to the carrier, and having a heat absorbing end and a cooling end, wherein the heat absorbing end is thermally consuming to the back surface of the wafer, and The cooling end is connected to the heat sink. 2 The semiconductor package structure according to claim 1 of the patent application, further comprising a heat-conductive adhesive for fixing the back surface of the wafer to the carrier. 3. The semiconductor package structure of claim 2, wherein the endothermic end extends into the thermally conductive adhesive. 4. The semiconductor package structure according to item i of the patent application scope, wherein the cooling end penetrates into the heat sink to increase the thermal contact area. 5: The scope of application for patents! The semiconductor package structure further includes a conductive adhesive for adhering the cooling end to the heat sink. 6. According to the first patent structure of the patent application scope, wherein the carrier board 7 is in accordance with the semiconductor package I structure of claim 6 of the patent application scope, the center plate is fixed on the substrate and located at "^', , 1徂y...Hai Ri and the top of the substrate. The semiconductor package structure of the sixth aspect of the invention is further characterized in that: the auxiliary package is disposed between the substrate and the wafer, wherein the heat absorption end is connected to the auxiliary heat sink. 9't claim to claim the semiconductor package structure of claim 8, wherein the endothermic end is inserted into the auxiliary heat sink to increase the thermal contact area. 10. The semiconductor package structure according to item 8 of the patent application scope, wherein the auxiliary thermal film is a metal piece. 11. The semiconductor package structure of claim 1G of the patent scope, wherein the auxiliary heat sink is a steel metal sheet. 12. The semiconductor package structure of claim 1, wherein the carrier is a wire frame and includes a wafer holder and a plurality of support ribs connected to the wafer holder. 13. The semiconductor package structure of claim 12 of the patent application, wherein the month owing, ', the film is fixed on the wafer holder and located below the wafer and the wafer holder. The semiconductor package structure comprises: a carrier board; an auxiliary heat sink fixed on the carrier board; and a chip disposed on the carrier board, the chip has a main main surface and a back surface, wherein The active surface is electrically connected to the heat sink; and at least one heat pipe is fixed on the carrier, and has a heat absorbing end and a cooling end of 18 1248667 15 , wherein the heat absorbing end is connected to the auxiliary The end is connected to the heat sink. The heat sink and the cold upper ===== the semiconductor sealing structure of item 14 of the benefit range, wherein (i) the teeth are inserted into the heat sink to increase the thermal contact area. 17、 一、請專利範圍第14項之半導體封裝構造，另包令 u黏膠’用以將該冷卻端黏著於該散熱片。 18、 依申請專利範圍第14項之半導體封裝構造，其中該 載板係為一基板。 19、 依申請專利範圍第14項之半導體封裝構造，並中兮 散熱片係固定於該基板上，並位於該晶片及該基板之I 方0 20、依申請專利範圍 吸熱端係配置於該 第18項之半導體封裝構造，其中該 晶片之該背面與該輔助散熱片之間。17. The semiconductor package structure of claim 14 of the patent scope is further provided, wherein the adhesive layer is used to adhere the cooling end to the heat sink. 18. The semiconductor package structure of claim 14, wherein the carrier is a substrate. 19. The semiconductor package structure according to claim 14 of the patent application scope, wherein the heat sink is fixed on the substrate, and is located on the wafer and the substrate of the substrate 0 20, according to the patent application range, the heat absorption end is disposed in the first The semiconductor package structure of claim 18, wherein the back side of the wafer is between the auxiliary heat sink. 21、 依申請專利範圍第18項之半導體封裝構造’其中該 吸夂端係牙入该輔助散熱片θ ’用以增加導熱接觸面 積0 22、 依申請專利範圍第18項之半導體封裝構造，其中該 吸熱端係配置於該輔助散熱片與該基板之間。 23、 依申请專利範圍第丨4項之半導體封裝構造，其中該 輔助散熱片係為一金屬片。 19 1248667 24 依申請專利範圍箓？ Μ热〃圍弟23項之半導體封裝構造，其中該 政.、、、片係為鋼製金屬片。 25、載：：！專利範圍第14項之半導體封裝構造，其中該 :::為—導線架’並包含一晶片承座及複數條支撐肋 ir、連接於該晶片承座， 曰 '片。 且该日日片承座係為該輔助散熱 依申明專利範圍第25項之半導體封裝構造，其中， '、、、而係配置於该晶片之該背面與該輔助散熱片之間21. The semiconductor package structure of claim 18, wherein the suction end is inserted into the auxiliary heat sink θ' to increase the thermal contact area 0 22, and the semiconductor package structure according to claim 18 of the patent application scope, wherein The heat absorbing end is disposed between the auxiliary heat sink and the substrate. 23. The semiconductor package structure of claim 4, wherein the auxiliary heat sink is a metal piece. 19 1248667 24 According to the scope of application for patents? The semiconductor package structure of 23 enthusiasm, including the steel sheet metal. 25, contains::! The semiconductor package structure of claim 14 wherein the ::: is a lead frame and comprises a wafer holder and a plurality of support ribs ir connected to the wafer holder. And the Japanese wafer carrier is the semiconductor package structure of the auxiliary heat dissipation according to claim 25, wherein ', , is disposed between the back surface of the wafer and the auxiliary heat sink 〜依中請專利範圍第25項之半導體封裝構造，其中 而係牙入邊輔助散熱片内，用以增加導熱接觸适 積0 依申明專利|巳圍帛25項之半導體封裝構造，其中該 吸熱係配置於該輔助散熱片上。 29、依申睛專利範圍第25項之半導體封裝構造，其中該 散熱片係固定於該晶片承座上，並位於該晶片及該晶片 承座之下方。 20~ The semiconductor package structure of the 25th patent scope of the patent, wherein the tooth-in-side auxiliary heat sink is used to increase the thermal conductivity contact product. According to the patent package, the semiconductor package structure of 25 items, wherein the heat absorption It is disposed on the auxiliary heat sink. 29. The semiconductor package structure of claim 25, wherein the heat sink is attached to the wafer holder and below the wafer and the wafer holder. 20
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