TW468256B

TW468256B - Ball grid array packaging device for chip scale/size package and the packaging method thereof

Info

Publication number: TW468256B
Application number: TW090100421A
Authority: TW
Inventors: Rung-Jen Juang
Original assignee: Rung-Jen Juang
Priority date: 2001-01-09
Filing date: 2001-01-09
Publication date: 2001-12-11

Abstract

The present invention provides a ball grid array packaging device for chip scale/size package and the packaging method thereof which includes the following steps: configuring a pre-defined welding pad array on one chip; forming the inner solder balls or solder bumps on top of each pads; covering the chip surface and the inner solder balls or solder bumps with an encapsulation and making part of it extrude to the outer surface of the encapsulation for use as the external contacts; configuring with a plurality of packaging solder balls on top of the extruded external contacts of each inner solder balls or solder bump respectively; using the effect of the inner solder balls or the solder bumps to form the electrical connection between the chip and the packaging solder balls. The present invention is characterized in reducing package dimensions to the chip size, shortening heat dissipation paths, providing better electrical properties and reducing cost.

Description

4 6 8 256 五、發明說明α) 發明領域：本發明係有關一種球柵陣列封裝（Ba 11 Gr i d Array，BGA)，特別是關於一種具有封裝體特徵嵌入晶片垾墊之晶片尺寸封裝（Chip Scale/Size Package，CSP) 的球柵陣列封裝及其製造方法。發明背景：縮小封裝尺寸一直是半導體業者所追求的目標，在半導體製程技術不斷推陳出新的過程中，細微化製程的進步使得半導體晶片尺寸一直都有突破性的發展，不但大幅縮小晶片尺寸，亦提供更多的功能，有效降低製造成本。但傳統式利用導線架（Lead frame)的封裝型式因外型尺寸之限制1不僅無法提供局功能晶片之需求（I / 0引腳數有限），且無法縮小 SMT( Surface Mount Technology)組裝面積。球柵陣列（Ba 1 1 G r i d A r r ay， BG A)封裝提供了多引腳的解決方案，其係在相同的組裝面積下，BGA封裝能提供更多引腳數；利用BGA技術，半導體晶片使用谭球 (s ο 1 d e r b a 1 I)直接與封裝基板上的球狀焊料黏合，如覆晶（f丨i p _ c h i p)的技術，其係提供許多優於傳統封裝上的優點’例如將輪入/輸出直接黏合縮短距離以利訊號高速傳輸’但其卻有封裝面積較大之缺失。因此，為了因應高密度的封裝裝置，以發展更輕、薄、短、小的電子系統產品，晶片尺寸封裝（Csp)技術 4 6 8 25 6 五、發明說明（2) 應運而生，其基本定義為封裝後的I C寬度小於原始晶片寬度的1. 2倍，或其平面面積小於晶粒面積的1 . 4倍'，而CSP 所使用的技術基本上源於上述之BGA技術，差別者僅為焊球的尺寸縮小；而一般CSP封裝之製程係以晶片矩陣式排列於同一封裝基板上，以保護層覆蓋於基板上形成一大封裝體，再利用切割的方式切成獨立之封裝單元，此製程具有產量大之優點。然而，上述封裝結構之共通點皆是將晶片安裝在導線架或封裝基板上，再利用引線形成電連接，使封裝後之積體電路裝置可利用焊球或引腳而安裝在其他裝置上；然此種封裝受限於導線架、封裝基板及引線的存在，使得縮小封裝尺寸的發展受到相當多的限制，無法真正縮至最小；且在紅外線回流（I R re f 1 ow)或在可靠性測試時，由於引線太長，所以易產生引線損壞之問題，而影響該封裝裝置之電性。因此，本發明以輕薄短小的設計準則配合對高散熱/ 高傳導速率的電性需求，提出一種無使用導線架或封裝基板之晶片尺寸球柵陣列封裝裝置。4 6 8 256 V. Description of the invention α) Field of the invention: The present invention relates to a ball grid array package (Ba 11 Gr id Array, BGA), in particular to a chip size package (Chip) with package features embedded in a wafer pad. Scale / Size Package (CSP) ball grid array package and manufacturing method thereof. Background of the Invention: Reducing the package size has always been a goal pursued by semiconductor industry. In the process of continuously innovating the semiconductor process technology, the progress of miniaturization has led to breakthrough developments in the size of semiconductor wafers. More features effectively reduce manufacturing costs. However, due to the size limitation of the traditional lead frame package type1, not only cannot provide the requirements of local function chips (the number of I / 0 pins is limited), but also cannot reduce the SMT (Surface Mount Technology) assembly area. Ball grid array (Ba 1 1 G rid A rr ay, BG A) package provides a multi-pin solution, which is under the same assembly area, BGA package can provide more pins; using BGA technology, semiconductor The chip uses Tan Ball (s ο 1 derba 1 I) to directly adhere to the spherical solder on the packaging substrate, such as flip-chip (f 丨 ip_chip) technology, which provides many advantages over traditional packaging. The input / output of the wheels is directly bonded to shorten the distance to facilitate the high-speed transmission of signals. However, it has the disadvantage of a large package area. Therefore, in order to respond to high-density packaging devices to develop lighter, thinner, shorter, and smaller electronic system products, the chip size package (Csp) technology 4 6 8 25 6 V. Description of the invention (2) came into being, its basic Defined as the IC width after packaging is less than 1.2 times the original wafer width, or its planar area is less than 1.4 times the die area ', and the technology used by CSP is basically derived from the above BGA technology, the difference is only In order to reduce the size of the solder ball, the general CSP packaging process is arranged in a matrix of wafers on the same packaging substrate, a protective layer is covered on the substrate to form a large package, and then cut into independent packaging units by cutting. This process has the advantage of large output. However, the common points of the above package structures are that the chip is mounted on a lead frame or a package substrate, and then the leads are used to form an electrical connection, so that the packaged integrated circuit device can be mounted on other devices using solder balls or pins; However, this kind of package is limited by the existence of lead frames, package substrates and leads, which makes the development of reducing the size of the package quite limited, and cannot be truly minimized; and in the infrared reflow (IR re f 1 ow) or in the reliability During the test, because the lead is too long, it is easy to cause the problem of lead damage, which affects the electrical property of the packaging device. Therefore, the present invention proposes a wafer-size ball grid array packaging device without using a lead frame or a packaging substrate according to light, thin and short design criteria to meet the electrical requirements for high heat dissipation / high conduction rate.

4 6 8 256 ;五、發明說明（3) 本發明之另一目的係在運用現有封裝廠線上的成熟製程與設備，來達成縮小封裝體SMT面積之功效，ii可利用 BGA之結構，提供封裝體較多之引腳以提供電氣訊號的連接，同時達到提高功能、縮小尺寸之雙重效益。本發明之再一目的係在提供一種兼具散熱途徑短與電性傳導路徑短之晶片尺寸球柵陣列封裝裝置，使其具有良好的散熱效果與電性。本發明又一目的係在降低製造封裝裝置的成本，避免耗費不必要之材料。為達到上述之目的，本發明在封裝焊球位置的各項定義與晶片焊墊陣列的各項定義完全相同之條件下，在一晶片上的焊墊陣列中，在每一焊墊上各形成一内焊球或焊料凸塊，一封裝膠體係覆蓋在晶片表面並包覆該内焊球或焊料凸塊，並使其部份凸出該封裝膠體外表面作為外接點，另有一封裝焊球陣列，使每一封裝焊球分別位於每一内焊球或焊料凸塊凸出之外接點正上方，以形成電連接。底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術内容、特點及其所達成之功效。圖號說明： 10 晶片 12 悍墊陣列 14 焊墊 16 内焊球 1 8 封裝膠體 20 外接點4 6 8 256; V. Description of the invention (3) Another object of the present invention is to use mature processes and equipment on the existing packaging factory line to achieve the effect of reducing the SMT area of the package. Ii The structure of the BGA can be used to provide packaging. There are more pins in the body to provide the connection of electrical signals, and at the same time, the dual benefits of increased functions and reduced size are achieved. Another object of the present invention is to provide a wafer size ball grid array packaging device having both a short heat dissipation path and a short electrical conduction path, so that it has a good heat dissipation effect and electrical properties. Another object of the present invention is to reduce the cost of manufacturing the packaging device and avoid the consumption of unnecessary materials. In order to achieve the above-mentioned object, in the present invention, under the condition that the definitions of the package solder ball positions and the definitions of the wafer pad array are exactly the same, in the pad array on a wafer, one is formed on each pad. Inner solder balls or solder bumps, an encapsulant system covers the surface of the wafer and covers the inner solder balls or solder bumps, and makes part of it protrude from the outer surface of the encapsulant as an external point. , So that each package solder ball is located directly above each of the inner solder ball or solder bump protruding outer contacts to form an electrical connection. In the following, detailed descriptions will be made with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features and functions of the present invention. Description of drawing number: 10 chips, 12 hard pad arrays, 14 solder pads, 16 inner solder balls, 1 8 packaging gel, 20 external points

第6頁 /16 3 25 6 五、發明說明¢4) 2 4 金屬板 2 8 焊球 22 封裝焊球 2 6 焊料凸塊詳細說明· 本發明之主要特點係在利用中心點、中心線等條件，定義出晶片焊墊與封装焊球之相對位置，使每一封裝能夠恰好垂直位於晶片焊墊之正上方，以達到本發明之目的與功效。如第一圖所示’為本發明欲封裝之封裝焊球2 2位置的各項疋義’包括封裝中心點（package central p〇int) P1、封裝中心線 X轴（package central line X axle) P 2、封裝中心線 Y軸（package central line Y axle) P3 ’封裝焊球陣列P4及其内之封裝焊球中心點（Package bal I central point) P5、封裝焊球中心線 χ轴（Package ba i 1 centra 1 1 i ne X ax 1 e) P6、封裝焊球中心線 γ軸 (Package ball central line Υ axle) Ρ7、封裂焊球 χ 軸間距（Package ball pitch X axle) P8、封裝焊球 γ軸間距（Package ba11 pitch Y ax丨e) Ρ9、封裝焊球陣列χ 軸間距（Package ball matrix pitch X axle) Ρ10' 封裝焊球陣列 Y轴間距（P a c k a g e b a 1 1 m a t r i x p i t c h Y axle) PI 1以及封裝焊球總數（Package ball total number in matrix) P12。而關於本發明晶片上之焊墊陣列位置的各項定義如第二圖所示，包括晶片中心點（C h i p central point) Cl、晶片中心線 X钟（Chip centralPage 6/16 3 25 6 V. Description of the invention ¢ 4) 2 4 Metal plate 2 8 Solder ball 22 Package solder ball 2 6 Detailed description of solder bumps · The main feature of the present invention is the use of the center point, center line and other conditions The relative positions of the wafer pads and the package solder balls are defined so that each package can be positioned directly directly above the wafer pads in order to achieve the purpose and effect of the present invention. As shown in the first figure, 'the meanings of the 2 positions of the package solder ball 22 to be packaged according to the present invention' include package central point P1, package central line X axle P 2. Package central line Y axle P3 'Package ball array P4 and the package ball I central point (Package bal I central point) P5 Package X line axis (Package ba i 1 centra 1 1 i ne X ax 1 e) P6, Package ball central line Υ axle P7, Package ball pitch X axle P8, Package ball pitch X axle γ-axis pitch (Package ba11 pitch Y ax 丨 e) P9, Package ball matrix pitch χ axis pitch (Package ball matrix pitch X axle) P10 'Package solder ball array Y-axis pitch (P ackageba 1 1 matrixpitch Y axle) PI 1 and Package ball total number in matrix P12. The definitions of the pad array positions on the wafer of the present invention are shown in the second figure, including the wafer center point (C h i p central point) Cl, the wafer center line X clock (Chip central

第7頁〇 8 25 6 五、發明說明（5) 1 i n e X a X 1 e) C 2、晶片中心線 Y軸（C h i p c e n t r a 1 1 i n e Y ax U) C3，晶片焊墊陣列C4及其内之晶片焊墊·中心點 C5、晶片焊墊中心線X軸C6、晶片焊墊中心線Y軸C7、晶片焊墊X轴間距C 8、晶片焊墊Y軸間距C 9、晶片焊墊陣列X軸間距C 1 0、晶片焊墊陣列Y軸間距C 1 1以及晶片焊墊總數 C12° 由於封裝焊球位置必須完全對應至晶片上之每一焊墊，因此封裝焊球位置的各項定義必須與晶片焊墊陣列的各項定義完全相同，換言之，在封裝中心點P1等於晶片中心點C1、封裝中心線X軸P2等於晶片中心線X軸C2與封裝中心線Y軸P 3等於晶片中心線Y軸C 3的條件下，請同時參考第三圖所示，其他定義必須完全相同，即封裝焊球陣列P4等於晶片焊墊陣列C4、封裝焊球中心點P5等於晶片焊墊中心 -點C5、封裝焊球中心線X軸P6等於晶片焊墊中心線X軸C6、 -封裝焊球中心線Y轴P 7等於晶片焊墊中心線Y軸C 7、封裝焊球X軸間距P8等於晶片焊墊X柏間距C8、封裝焊球Y軸間距 P 9等於晶片焊墊Y轴間距C 9、封裝焊球陣列X軸間距P 1 0等於晶片焊墊陣列X軸間距C 1 0、封裝焊球陣列Y軸間距P 1 1等於晶片焊墊陣列Y軸間距C 1 1以及封裝焊球總數P 1 2等於晶片焊墊總數C 1 2 ;在上述特徵成立下，本發明之焊球恰可對應至其正下方之晶片焊墊上，以呈現一垂直關係位置來達到本發明之功效。因此，下面實施例即是在上述各項條件皆成立之定義下所得到之封裝結構及其封裝方法。一晶片尺寸球柵陣列封裝裝置，如第四圖所示，一晶Page 7 〇 8 25 6 V. Description of the invention (5) 1 ine X a X 1 e) C 2. Chip centerline Y axis (C hipcentra 1 1 ine Y ax U) C3, wafer pad array C4 and its inside Wafer pads · Center point C5, Wafer pad centerline X-axis C6, Wafer pad centerline Y-axis C7, Wafer pad X-axis distance C 8, Wafer pad Y-axis distance C 9, Wafer pad array X Axial distance C 1 0, wafer pad array Y-axis distance C 1 1 and total number of wafer pads C12 ° Since the position of the package solder ball must completely correspond to each pad on the wafer, each definition of the package solder ball position must It is exactly the same as each definition of the wafer pad array, in other words, at the package center point P1 is equal to the wafer center point C1, the package centerline X axis P2 is equal to the wafer centerline X axis C2, and the package centerline Y axis P3 is equal to the wafer centerline. Under the condition of Y axis C 3, please also refer to the third figure. The other definitions must be the same, that is, the package solder ball array P4 is equal to the wafer pad array C4, and the package solder ball center point P5 is equal to the wafer pad center-point C5 The center line X axis P6 of the package solder ball is equal to the center line X axis C6 of the wafer pad, -Package ball centerline Y axis P 7 is equal to wafer pad centerline Y axis C 7, package solder ball X axis spacing P8 is equal to wafer pad X Pitch C8, package solder ball Y axis spacing P 9 is equal to wafer pad Y Axial distance C 9, package X ball array X axis distance P 1 0 is equal to wafer pad array X axis distance C 1 0, package solder ball array Y axis distance P 1 1 is equal to wafer pad array Y axis distance C 1 1 and package The total number of solder balls P 1 2 is equal to the total number of wafer pads C 1 2. With the above characteristics established, the solder balls of the present invention can correspond to the wafer pads directly below them to present a vertical relationship to achieve the effect of the present invention. . Therefore, the following embodiments are packaging structures and packaging methods obtained under the above-mentioned conditions. A wafer size ball grid array packaging device, as shown in the fourth figure, a crystal

第8頁 4 6 8 25 6 五、發明說明（6) _ 片1 0上係設有排列整齊的焊墊陣列1 2，在兮θ 之複數焊墊14中，每二相鄰焊墊14之水平列上2内相鄰焊墊1 4之垂直間距亦相等，其中水平 ’母二垂直間距’且該焊墊1 4間距係大於習知晶片夂寺於在每一焊墊1 4之正上方設有一内焊球i 6，〜壯1間距: 覆蓋在晶片1 〇表面並包覆該焊墊i 4及内烊埭：體1 8係球1 6部份凸出該封裝膠體丨8外表面，以作為外接點t内焊有一封裝焊球陣列之複數封裝焊球2 2，分別位於每_ ’另球1 6凸出之外接點2 〇正上方，以形成電連接，节内焊 j.. , c 叹利用内煤豕1 6之作用’使晶片1 0與封裝焊球2 2形成電性相接到傳遞電性訊號之目的。 ’ Μ達 /、中在上述晶片1 0之另一表面更黏接一金屬板24 如第五圖所示，金屬板2 4之尺寸係略大於晶片1 〇尺寸，，封裝膠體1 8係同時包覆晶片1 0及内焊球1 6 ’而預留内俨且 1 6頂端部份凸出封裝膠體1 8外，以作為電連接封裝焊球求，外接點2 0 ;此具有金屬板2 4之封裝裝置除可増加其、2 2 效果外，更可藉由金屬板2 4之尺寸來定義出整個封裴萝 =尺寸’若晶片1 〇與金屬板24尺彳相同，則封裴大小^ =至晶片尺寸，且完成後之封裝裝釁沒有導線架或封二 $與引線之結構，以兼具有縮小尺十及提高對外弓丨數f 之特性。叫歎量一現就上述之結構來說明本發明之封裝方法，第六圖 :為本發明製作第四圖之封裝裝置結構的流程示意圖，斤所不，該封裝方法係包括下列步驟：先提供—晶片丨〇，°Page 8 4 6 8 25 6 V. Description of the invention (6) _ The 10 pads are provided with an array of regularly arranged pads 12. Among the plural pads 14 of θ, every two adjacent pads 14 The vertical spacing between adjacent pads 14 in 2 in the horizontal column is also equal, in which the horizontal 'mother-two vertical spacing' and the spacing between the pads 14 are larger than the conventional wafers. An inner solder ball i 6 is provided, with a pitch of ~ 1: covering the surface of the wafer 10 and covering the pad i 4 and the inner pad: the body 1 8 series ball 1 6 partly protrudes from the outer surface of the encapsulant 丨 8 As an external point t, a plurality of packaged solder balls 22 with an array of packaged solder balls are welded, which are located directly above each of the other balls 16 protruding outside the contact 2 〇 to form an electrical connection, soldering in the joint. ., c sigh The purpose of using the function of the inner coal mine 16 to make the chip 10 and the package solder ball 22 to be electrically connected to each other to transfer electrical signals. 'Μ 达 /, a metal plate 24 is more adhered to the other surface of the above-mentioned wafer 10 As shown in the fifth figure, the size of the metal plate 24 is slightly larger than the size of the wafer 10, and the packaging gel 18 is simultaneously Cover the wafer 10 and the inner solder ball 16 'while leaving the inner part 16 and the top part of the 16 protruding out of the packaging gel 18 to be used as the electrical connection packaging solder ball. The outer point 2 0; this has a metal plate 2 In addition to the 2 and 2 2 effects of the packaging device, the entire seal can be defined by the size of the metal plate 2 4 = size 'If the wafer 1 〇 is the same as the metal plate 24 feet, the size of the seal is ^ = To the chip size, and the completed package assembly does not have a lead frame or a package structure with leads and leads, in order to have the characteristics of reducing the size of ten and increasing the number of external bows f. Let ’s sigh now to explain the packaging method of the present invention based on the above structure. The sixth figure is a schematic flow chart of the packaging device structure of the fourth figure of the present invention. However, the packaging method includes the following steps: —Chip 丨〇, °

第9頁 468 256 五、發明說明（7) 其上係設有焊墊陣列1 2 ;在該晶片焊墊陣列丨2 1 A Jl 人一 ^P4 万以焊接技術形成有内焊球1 6後’使其經 '第—士 4 3 = Ϊ處理；再利用注模成型或印刷成型將-封裝；Ϊ ^後盘在晶片1 〇表面並包覆所有内焊球1 6，並預留每I 焊球i6之頂端部份，使其凸出封裝膠體1 8外作為外接點 2 〇 ’最後’在每一内焊球丨6凸出之外接點2 〇正上方封裝焊球22 ’並使其經第二次紅外線回流處理，$ 曰tip-u丄，战一曰日乃人τ球柵陣列封裝裝置。而如第五圖所示之增加金屬板24結構的封裝方法係如第七其係'在—晶片1 G之每—焊墊1 4上形成有内焊球1 6 j、.生第一次紅外線回流處理後；在晶片丨〇之另一表面黏接二金屬板24’然後藉一封裝膠體18包覆該晶片1〇及所有内焊球1 6 ’並使内焊球丨6之部份凸出封裝膠體丨8外作為外接 =2 0 ’之後在每一内焊球丨6凸出之外接點2 〇上形成有封裝 4球22並經第二次紅外線回流處理後，亦可形成—晶尺寸球柵陣列封裝裝置。曰日另外’本發明除了在晶片10焊墊14上形成複數内焊球 1 6作為導電接點以電連接封裝焊球22之外，更可藉焊料凸塊2 6電連接晶片與封裝焊球’如第八圖所示，此封裝裝置係在一晶片1 0上設有複數焊墊i 4，複數焊料凸塊26係分位於每一焊墊1 4上，一封裝膠體〗8係覆蓋在晶片〗〇表面 ^覆該焊塾14及焊料凸塊26，並使痒料凸塊2 四 f該封裝#體W表面，以作為外接.點20,並有複數U 焊球22分別電連接至每1料凸塊26凸出之外接==裝Page 9 468 256 V. Description of the invention (7) There is a pad array 1 2; on the wafer pad array 丨 2 1 A Jl ^ P4 million After the inner solder ball 16 is formed by welding technology 'Make it through' first-taxi 4 3 = Ϊ treatment; then use injection molding or printing molding to-package; Ϊ ^ back disk on the surface of the wafer 10 and cover all inner solder balls 16, and reserve each I The top part of the solder ball i6 makes it protrude from the outside of the encapsulation gel 1 8 as the external connection point 2 〇 'finally' on each inner solder ball 6 protrudes outside the contact 2 2 and encapsulates the solder ball 22 'directly above it After the second infrared reflow process, the tip-u 丄 is called the Japanese-style τ ball grid array packaging device. As shown in the fifth figure, the packaging method for increasing the structure of the metal plate 24 is as seventh. It is based on the formation of inner solder balls 1 6 on each of the wafer 1 G and the pads 14. After the infrared reflow treatment, two metal plates 24 'are adhered to the other surface of the wafer, and then the encapsulation gel 18 is used to cover the wafer 10 and all the inner solder balls 16', and to make a part of the inner solder balls 6 Envelope encapsulation 丨 8 outer as external connection = 2 0 ′ After each inner solder ball 丨 6 embossed outer contact 2 〇 Encapsulation 4 ball 22 is formed and after the second infrared reflow treatment, it can also be formed— Crystal size ball grid array packaging device. "In addition to the present invention, in addition to forming a plurality of internal solder balls 16 on the solder pads 14 of the wafer 10 as conductive contacts to electrically connect the package solder balls 22, the present invention can also use the solder bumps 26 to electrically connect the chip and the package solder balls. 'As shown in the eighth figure, this packaging device is provided with a plurality of solder pads i 4 on a wafer 10, a plurality of solder bumps 26 are located on each of the solder pads 14, and a packaging gel is covered by 8 The surface of the chip is covered with the solder pad 14 and the solder bump 26, and the bump bump 2 is formed on the surface of the package as an external connection. The point 20 is provided, and a plurality of U solder balls 22 are respectively electrically connected to Every 1 material bumps 26 protruding and connected == installed

第10頁働 8 25 6 五、發明說明（8) 其中，在晶片1 0之另一表面更黏接一金屬板24，如第九圖所示。如第十圖所示，其係為本發明製作第八圖之封裝裝置結構的流程示意圖，如圖所示，此封裝方法係先準備一具有複數焊墊1 4之晶片1 0，在每一焊墊1 4上以焊接技術形成有焊料凸塊26;再形成一封裝膠體18包覆所有焊墊14及焊料凸塊2 6，並使每一焊料凸塊2 6頂端部份凸出封裝膠體1 8 外，以作為外接點2 0 ;而後再於每一焊料凸塊2 6凸出之外接點2 0上形成有封裝焊球2 2，使其經過紅外線回流處理，以形成一具焊料凸塊2 6結構之晶片尺寸球柵陣列封裝裝置。其中，如第十一圖所示，若在形成該封裝膠體步驟之前，先於上述晶片1 0之另一表面黏接一金屬板2 4，則可形成如第九圖所示之封裝裝置。本發明係以内焊球及焊料凸塊等導電接點使晶月與封裝焊球形成電連接，此外，更可以更簡單之結構表示之，如第十二圖所示，其係在晶片1 〇焊墊1 4上直接安裝有焊球 28，一封裝膠體1 8包覆晶片1 0表面及其上之焊墊1 4與小部份之焊球2 8，使大部分之焊球2 8Λ出該封裝膠體1 8外，以作為電連接至其他裝置的對外接點；並可於晶片1 0之另一表面設有一金屬板24，如第十三圖所示。此種封裝裝置之封裝方法大致與上述方法相同，故於此不再贅述。其中，在上述之各種實施例中所使用之晶片焊墊陣列 1 2 (封裝焊球陣列）係為如第三圖所示之完全陣列（F u i 1 matrix)，此外，另有一種如第十四圖所示之不完全陣列Page 10 働 8 25 6 V. Description of the invention (8) Among them, a metal plate 24 is more adhered to the other surface of the wafer 10, as shown in the ninth figure. As shown in the tenth diagram, it is a schematic flow chart of the packaging device structure of the eighth diagram of the present invention. As shown in the figure, the packaging method is to first prepare a wafer 10 with a plurality of pads 14 and Solder bumps 26 are formed on the solder pads 14 by soldering technology; an encapsulation gel 18 is formed to cover all the solder pads 14 and the solder bumps 26, and the top part of each solder bump 26 is projected from the packaging gel. 1 8 is used as an external connection point 20; and then, each solder bump 26 is projected with an external solder joint 22 formed on the external contact point 20, which is subjected to infrared reflow treatment to form a solder bump. Wafer size ball grid array packaging device of block 26 structure. Among them, as shown in FIG. 11, if a metal plate 24 is adhered to the other surface of the wafer 10 before the step of forming the packaging colloid, a packaging device as shown in FIG. 9 can be formed. The present invention uses a conductive contact such as an internal solder ball and a solder bump to form an electrical connection between the crystal moon and the package solder ball. In addition, it can be expressed in a simpler structure. As shown in Figure 12, it is on the wafer 1 〇 There are solder balls 28 directly mounted on the solder pads 14, a package gel 18 covers the surface of the wafer 10 and the solder pads 14 on the surface and a small number of solder balls 2 8 so that most of the solder balls 2 8 The encapsulant 18 is used as an external connection point for electrical connection to other devices; a metal plate 24 may be provided on the other surface of the chip 10, as shown in the thirteenth figure. The packaging method of such a packaging device is substantially the same as the above method, so it will not be repeated here. Among them, the wafer pad array 12 (package solder ball array) used in the above-mentioned various embodiments is a full array (Fui 1 matrix) as shown in the third figure. Incomplete array shown in four figures

,3 256_ 五、發明說明（9) (P a r t i a 1 in a t r i X)，其係將該晶片焊墊陣列1 2 (或是封裝焊球陣列）平均區分為二左右部份，其正中央則為一中空區域，且該封裝焊球位置的各項定義係必須與晶片焊墊陣列的各項定義完全相同，使此種不完全陣列亦可應用於上述之封裝裝置中。職是，本發明係以封裝體特徵嵌入晶片烊墊之晶片尺寸球柵陣列封裝裝置為訴求標的，且其並無使用任何導線架或封裝基板與引線，以確實將封裝尺寸縮至最小的晶片般尺寸，並有效縮短散熱途徑與電性傳導路徑，使晶片尺寸球柵陣列封裝裝置具有良好的散熱效果與電子電性；由於直接省略導線架、封裝基板與引線等不必要材料之支出，故可降低製造整個封裝製程的成本。再者，本發明係運用現有封裝廠線上的成熟製程與設備，來達成縮小封裝體SMT面積之效益，並藉由球柵陣列封裝的多焊球引腳以提供電氣訊號的連接，同時達到提高功能、縮小尺寸之雙重效益。以上所述實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精祌所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍内。3, 256_ V. Description of the invention (9) (P artia 1 in atri X), which divides the wafer pad array 1 2 (or packaged solder ball array) into two parts on the average, and the center is A hollow area and the definitions of the positions of the package solder balls must be exactly the same as the definitions of the wafer pad array, so that this incomplete array can also be applied to the above-mentioned packaging device. The purpose is that the present invention is based on a wafer-size ball grid array packaging device with package characteristics embedded in a wafer pad, and it does not use any lead frame or packaging substrate and leads to truly reduce the package size to the smallest chip. General size, and effectively shorten the heat dissipation path and electrical conduction path, so that the chip size ball grid array packaging device has good heat dissipation effect and electronic electrical properties; since the unnecessary expenditure of lead frames, packaging substrates and leads is directly omitted, so Can reduce the cost of manufacturing the entire packaging process. Furthermore, the present invention uses mature processes and equipment on the existing packaging factory line to achieve the benefits of reducing the SMT area of the package, and provides multiple electrical ball connections by using ball grid array packages with multiple solder ball pins, while achieving improved The dual benefits of function and size reduction. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. When the scope of the patent of the present invention cannot be limited, Any equivalent changes or modifications made according to the essence disclosed in the present invention should still be covered by the patent scope of the present invention.

第12頁 8 25 6 圖式簡單說明圖式說明· 第一圖為本發明欲封裝之封裝焊球位置的各項定’義。第二圖為本發明晶片上之焊墊陣列位置的各項定義。第三圖為本發明之封裝焊球與晶片焊墊陣列結構配置條件示意圖。第四圖為本發明具内焊球結構之封裝裝置結構示意圖。弟五圖為弟四圖增設金屬板之結構不意圖。第六圖為第四圖所示封裝裝置之封裝方法。第七圖為第五圖所示封裝裝置之封裝方法。第八圖為本發明具焊料凸塊結構之封裝裝置結構示意圖。第九圖為第八圖增設金屬板之結構示意圖。第十圖為第八圖所示封裝裝置之封裝方法。第十一圖為第九圖所示封裝裝置之封裝方法。第十二圖為本發明之另一實施例。第十三圖為第十二圖增設金屬板之結構示意圖。第十四圖為本發明之封裝焊球與晶片焊墊陣列結構之另一實施例。Page 12 8 25 6 Brief Description of Drawings Description of Drawings · The first drawing shows the definitions of the positions of the package solder balls to be packaged according to the present invention. The second figure is the definitions of the pad array positions on the wafer of the present invention. The third figure is a schematic view showing the configuration conditions of the package solder ball and wafer pad array structure of the present invention. The fourth figure is a schematic structural diagram of a packaging device with an inner solder ball structure according to the present invention. Brother Wutu is the intention to add a metal plate to Brother Wutu. The sixth figure is a packaging method of the packaging device shown in the fourth figure. The seventh figure is a packaging method of the packaging device shown in the fifth figure. FIG. 8 is a schematic structural diagram of a packaging device with a solder bump structure according to the present invention. The ninth figure is a schematic structural diagram of an additional metal plate in the eighth figure. The tenth figure is a packaging method of the packaging device shown in the eighth figure. The eleventh figure is a packaging method of the packaging device shown in the ninth figure. The twelfth figure is another embodiment of the present invention. The thirteenth figure is a structural schematic diagram of adding a metal plate to the twelfth figure. The fourteenth figure is another embodiment of the package ball and wafer pad array structure of the present invention.

Claims

46 8 256 Six 'application patent scope 1 · A wafer-size ball grid array packaging device, comprising: at least one wafer on which a pad array is arranged, and the level of every two adjacent pads in the pad array The spacing is equal, and the vertical spacing of every two adjacent pads is also equal; a plurality of conductive contacts are formed on each of the pads separately; a packaging gel covering the pads and the conductive contacts, and making some conductive contacts The point part protrudes from the outside of the encapsulant as an external point; and a plurality of package solder balls are located on the protruded outer contacts of the conductive contact to form an electrical connection. 2. The wafer-size ball grid array packaging device described in item 1 of the scope of patent application, wherein the pad array is divided into two parts on the average, and a hollow area is at the center of the pad array. 3. The wafer-size ball grid array packaging device described in item 1 of the scope of the patent application, wherein the type of the conductive contact is selected from the group consisting of pins, solder balls, solder bumps, and studs. 4. The wafer-size ball grid array packaging device described in item 1 of the patent application scope, wherein a metal plate is further provided on the other surface of the wafer. 5. The wafer-size ball grid array packaging device described in item 1 of the patent application scope, wherein the packaging gel further covers the wafer. 6. The wafer size ball grid array packaging device described in item 1 of the scope of patent application, wherein the forming method of the packaging colloid is selected from one of injection molding and printing molding. 7. A wafer size ball grid array packaging method, including the following steps: A wafer is provided, and a pad array is provided on the wafer, and the pad array is provided on the wafer.

Page 14 468256 6. Within the scope of the patent application, the horizontal spacing of every two adjacent pads is the same, and the vertical spacing of every two adjacent pads is also the same; · An inner surface is formed on each of the pads of the wafer After the solder ball is subjected to the first infrared reflow treatment; the solder pad and the inner solder ball are covered with an encapsulating gel, and the inner solder ball part protrudes from the outer surface of the encapsulating gel as an external point; and Package solder balls are formed on the contacts protruding from the solder balls and subjected to a second infrared reflow process to form a wafer-size ball grid array packaging device. 8. The wafer size ball grid array packaging method described in item 7 of the scope of the patent application, wherein the pad array is divided into two parts on average, and a hollow area is at the center of the pad array. 9. The wafer size ball grid array packaging method as described in item 7 of the scope of patent application, wherein a metal plate may be adhered to the other surface of the wafer before the step of forming the packaging colloid. 10. The wafer size ball grid array packaging method according to item 7 of the scope of patent application, wherein the packaging gel further covers the wafer. 1 1. The wafer size ball grid array packaging method according to item 7 of the scope of the patent application, wherein the method of forming the packaging colloid is selected from one of injection molding and printing molding. 1 2. A wafer size ball grid array packaging method, including the following steps: Provide a wafer on which a pad array is arranged, and within the pad array, the horizontal spacing between every two adjacent pads is equal, and The vertical distance between every two adjacent pads is also equal;

Page 15 468256 6. The scope of the patent application: solder bumps are formed on each of the solder pads of the wafer; a solder paste is used to cover the solder pads and solder bumps, and the solder bumps partially protrude from the package. The outer body of the colloid is used as an external connection point; and a package solder ball is formed on each of the solder bump protruding external contacts, and is subjected to infrared reflow treatment to form a wafer-size ball grid array packaging device. 1 3 · The wafer-size ball grid array packaging method as described in item 12 of the scope of patent application, wherein the pad array is divided into two parts on the average, and a hollow area is at the center of the pad array. 14. The wafer size ball grid array packaging method according to item 12 of the scope of the patent application, wherein before the step of forming the packaging gel, a metal plate may be adhered to the other surface of the wafer. 1 5. The wafer size ball grid array packaging method as described in item 12 of the patent application scope, wherein the packaging gel further covers the wafer. 16. The wafer-size ball grid array packaging method according to item 12 of the scope of the patent application, wherein the method of forming the packaging colloid is selected from one of injection molding and printing molding. 17. A wafer size ball grid array packaging device, comprising: at least one wafer on which a pad array is arranged; in the pad array, the horizontal spacing between every two adjacent pads is equal, and every two phases The vertical distances between adjacent solder pads are also equal; a plurality of solder balls are formed on each of the solder pads separately; and a packaging gel covering the solder pads and some solder balls, and most of the solder balls protrude from the packaging gel Outside as a contact point for outside.

Page 16 4 6 8 25 6 VI. Patent application scope 1 8. The wafer size ball grid array packaging device described in item 17 of the patent application scope, wherein the pad array is divided into two parts on average. 'The center is a hollow area. 19. The wafer-size ball grid array packaging device according to item 17 of the scope of patent application, wherein a metal plate is further provided on the other surface of the wafer. 20. The wafer-size ball grid array packaging device described in item 17 of the scope of patent application, wherein the packaging gel further covers the wafer. 2 1. The wafer-size ball grid array packaging device described in item 17 of the scope of the patent application, wherein the formation method of the packaging colloid is selected from one of injection molding and printing molding. 2 2. A wafer size ball grid array packaging method, including the following steps: Provide a wafer on which a pad array is arranged, in which the horizontal spacing between every two adjacent pads is equal, and The vertical distance between each two adjacent solder pads is also equal; after forming solder balls on each of the solder pads of the wafer, an infrared reflow treatment is performed; and the solder pads and some solder balls are covered with a packaging gel, and Most of the solder balls protrude out of the encapsulating plastic body as external contacts to form a wafer-size ball grid array packaging device. 2 3. The wafer-size ball grid array packaging method described in item 22 of the scope of the patent application, wherein the pad array is divided into two parts on the average, and a hollow area is at the center of the pad array. 2 4. The wafer-size ball grid array packaging method as described in item 22 of the scope of the patent application, wherein, before the step of forming the packaging colloid, it may be preceded by the crystal.

Page 17 Preview 4 6 8 25 6 VI. Scope of patent application The other surface of the sheet is bonded to a metal plate. 25. The wafer-size ball grid as described in item 22 of the patent application > car train packaging method, wherein the packaging gel further covers the wafer. 26. The wafer size ball grid array packaging method described in item 22 of the scope of the patent application, wherein the method of forming the packaging colloid is selected from one of injection molding and printing molding.

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