CN102683329A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

Info

Publication number
CN102683329A
CN102683329A CN2011100845875A CN201110084587A CN102683329A CN 102683329 A CN102683329 A CN 102683329A CN 2011100845875 A CN2011100845875 A CN 2011100845875A CN 201110084587 A CN201110084587 A CN 201110084587A CN 102683329 A CN102683329 A CN 102683329A
Authority
CN
China
Prior art keywords
substrate
semiconductor package
packing colloid
package part
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011100845875A
Other languages
English (en)
Other versions
CN102683329B (zh
Inventor
方颢儒
钟兴隆
张卓兴
蔡宗贤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN102683329A publication Critical patent/CN102683329A/zh
Application granted granted Critical
Publication of CN102683329B publication Critical patent/CN102683329B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

一种半导体封装件及其制法。该半导体封装件包括：表面具有多个半导体元件的基板、覆盖在该基板与各该半导体元件上的封装胶体、以及形成在该封装胶体的外露表面上的金属层，该封装胶体具有沟槽以划分多个封装单元，令每一个封装单元具有一个半导体元件，且该金属层还形成在该沟槽中，使每一个半导体元件的外侧封装胶体上均包覆有金属层，可避免各该半导体元件之间相互电磁波干扰。本发明还提供该半导体封装件的制法。

Description

半导体封装件及其制法
技术领域
本发明有关一种半导体封装件，尤指一种具有防内部电子元件相互电磁波干扰功能的半导体封装件及其制法。
背景技术
随着半导体技术的演进，半导体产品已开发出不同形状的封装产品，而为提升电性品质，多种半导体产品具有屏蔽的功能，以防止电磁干扰(Electromagnetic Interference，EMI)产生，如第5557142号美国专利。
第7125744B2号美国专利提供一种避免EMI的射频(Radiofrequency，RF)模组的方式。如图1A及图1B所示，该第7125744B2号美国专利所揭示的射频模组1将多个半导体元件11a，11b电性连接在一基板10上，再以如环氧树脂的封装胶体12包覆各该半导体元件11a，11b及基板10，并于该封装胶体12上罩设一金属薄膜13。该射频模组1由该封装胶体12保护该半导体元件11a，11b及基板10，并避免外界水气或污染物的侵害，且由该金属薄膜13保护该些半导体元件11a，11b免受外界EMI影响。
第7701040B2号美国专利揭示一种多个模组相互堆叠的封装件。如图2所示，该第7701040B2号美国专利所揭示的射频模组2于外围包覆有屏障(shielding)层23，以避免该射频模组2与其他模组产生相互电磁干扰。
但是，现有技术中的射频模组1，2的外围虽可由包覆金属材以达到避免EMI的目的，却无法避免其内部各该半导体元件11a，11b之间的电磁波干扰(EMI)，导致讯号容易发生错误。
因此，如何提供一种能避免射频模组内部的电子元件相互电磁波干扰的半导体封装件，实为一重要课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的一目的在提供一种半导体封装件及其制法，以避免各该半导体元件之间相互电磁波干扰。
为达上述及其他目的，本发明提供一种半导体封装件，其主要包括一具有相对的第一表面及第二表面的基板、接置且电性连接于该基板的第一表面上的多个半导体元件、覆盖于该基板的第一表面与各该半导体元件上的封装胶体、以及形成于该基板与封装胶体上的金属层；其中，该封装胶体具有沟槽，以于该基板上划分多个封装单元，令每一个该封装单元具有至少一个该半导体元件，且该金属层复形成于该沟槽中，以包覆各该封装单元的周围，且令该基板的第二表面外露该金属层。
由上可知，本发明的半导体封装件，由沟槽的设计，使基板上划分出多个封装单元，令每一封装单元之间由金属层作包覆，使各该半导体元件之间不会相互受电磁波干扰。
另外，本发明还提供一种据上述结构的半导体封装件的制法。
附图说明
图1A及图1B为现有技术中射频模组的示意图，其中，图1A为立体图，图1B为剖面图。
图2为为现有技术中堆叠多个模组的封装件的剖面图。
图3A至图3E为本发明半导体封装件的制法的剖面示意图；其中，图3A’为图3A的另一实施例，图3D’为图3D的立体图。
主要元件符号说明
1、2              射频模组
10                基板
11a，11b，31，31’半导体元件
12，32            封装胶体
13                金属薄膜
23                屏障层
3                 半导体封装件
3’               封装单元
3a            承载件
3b            封装件预制品
30            基板
30a           上表面
30b           下表面
30c           侧表面
300           电性接触垫
310           焊线
310’         焊球
32a           顶面
32b           底面
32c           侧面
320           沟槽
33            金属层
L             预定切割线。
具体实施方式
以下由特定的具体实施例说明本发明的实施方式，熟悉此技术的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“一”、“二”及“下”等的用语，也仅是为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
请参阅图3A至图3E，为本发明半导体封装件的制法的示意图。于本实施例中，所述半导体封装件3可发出电磁波者，例如为射频(Radiofrequency，RF)模组。
如图3A及图3A’所示，提供一承载件3a，具有多个基板30(如图中的虚线作区分)，且各该基板30具有上表面(定义为第一表面)30a及下表面(定义为第二表面)30b；接着，接置多个半导体元件31于承载件3a上，亦即各该基板30的上表面30a上。
所述基板30的上表面30a及下表面30b上均具有多个电性接触垫300。
所述半导体元件31为射频芯片，例如：蓝芽芯片或Wi-Fi(Wireless Fidelity)芯片。
再者，如图3A所示，该半导体元件31以打线方式，即由焊线310，对应电性连接该基板30上表面30a上的电性接触垫300；或如图3A’所示，该半导体元件31’以覆晶方式，即由焊球310’，对应电性连接至该基板30上表面30a上的电性接触垫300。
如图3B所示，接续图3A的制程，将封装胶体32覆盖于该承载件3a(或基板30)的上表面30a及各该半导体元件31(含该焊线310)上。
所述封装胶体32具有外露的顶面32a及结合至该基板30上表面30a的底面32b。
如图3C所示，沿着各该基板30边缘的预定切割线L(如图3B所示)，切割该封装胶体32及该承载件3a，以形成多个分离的封装件预制品3b。该封装件预制品3b包括具有侧表面30c、上表面30a及下表面30b的基板30、接置于该基板30上表面30a上的多个半导体元件31、及覆盖于该基板30上表面30a与各该半导体元件31上的封装胶体32，且该封装胶体32经切割而具有侧面32c。
如图3D及图3D’所示，以镭射烧灼或机械切割，例如刀具切割方式，形成沟槽320于该封装件预制品3b的封装胶体32上，以于该基板30的上表面30a上划分多个封装单元3’，令每一个封装单元3’仅具有一个半导体元件31，但非指不可包括其他无影响电磁波干扰的电子元件。
所述沟槽320贯穿该封装胶体32以连通该封装胶体32的顶面32a与该基板30的部分上表面30a。
再者，于本实施例中，其中一个半导体元件31为蓝芽芯片，而另一个半导体元件31为Wi-Fi芯片。
如图3E所示，以例如化学镀膜的方式，如溅镀(sputtering)，形成金属层33于该沟槽320中、该封装胶体32的顶面32a与侧面32c上、该基极30的侧表面30c及其外露的上表面30a上，以包覆各该封装单元3’的周围，且令该基板的第二表面外露该金属层，俾形成该半导体封装件3，并由该金属层33作为电磁波屏障(EMI Shielding)，以防止各该半导体元件31之间相互电磁波干扰。也可以由涂布(coating)与回焊(reflow)方式形成该金属层33。
于本实施例中，由该金属层33，以防止蓝芽芯片与Wi-Fi芯片之间的讯号相互干扰。
再者，形成该金属层33的材质如铜(Cu)、镍(Ni)、铁(Fe)、铝(Al)、不锈钢(Sus)等。
因此，本发明的半导体封装件3及其制法，由该沟槽320的设计，使该半导体封装件3上划分出多个封装单元3’，令每一封装单元3’之间由金属层33的包覆，以避免该半导体封装件3上的各该半导体元件31之间发生电磁波相互干扰的问题。
上述实施例用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此项技术的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如本发明的权利要求所列。

Claims (14)

1.一种半导体封装件，其特征在于，包括：
基板，具有相对的第一表面及第二表面；
多个半导体元件，接置且电性连接于该基板的第一表面上；
封装胶体，覆盖于该基板的第一表面与各该半导体元件上，且该封装胶体具有沟槽，以于该基板上划分多个封装单元，令每一个该封装单元具有至少一个该半导体元件；以及
金属层，形成于该基板与封装胶体上、及该沟槽中，以包覆各该封装单元的周围，且令该基板的第二表面外露该金属层。
2.如权利要求1所述的半导体封装件，其特征在于，该半导体封装件为射频模组。
3.如权利要求1所述的半导体封装件，其特征在于，该半导体元件为射频芯片。
4.如权利要求1所述的半导体封装件，其特征在于，该封装胶体具有外露的顶面与侧面、及结合至该基板的第一表面的底面，且该沟槽贯穿该封装胶体以连通该顶面与该基板的第一表面。
5.如权利要求4所述的半导体封装件，其特征在于，该金属层形成于该封装胶体的顶面与侧面上。
6.如权利要求1所述的半导体封装件，其特征在于，该金属层选自铜、镍、铁、铝或不锈钢材质。
7.一种半导体封装件的制法，其特征在于，包括：
准备一封装件预制品，包含：
基板，具有相对的第一表面及第二表面；
多个半导体元件，接置且电性连接于该基板的第一表面上；及
封装胶体，覆盖于该基板的第一表面与各该半导体元件上；
形成沟槽于该封装件预制品的封装胶体上，以于该基板上划分多个封装单元，令每一个该封装单元具有至少一个该半导体元件；以及
形成金属层于该基板与封装胶体上、及该沟槽中，以包覆各该封装单元的周围，且令该基板的第二表面外露该金属层。
8.如权利要求7所述的半导体封装件的制法，其特征在于，该半导体封装件为射频模组。
9.如权利要求7所述的半导体封装件的制法，其特征在于，该封装件预制品的制程，包括：
提供一承载件；
接置各该半导体元件于该承载件上；
将该封装胶体覆盖于该承载件上，以包覆各该半导体元件；以及
切割该封装胶体及承载件，以形成多个分离的该封装件预制品，其中，该经切割的承载件该封装件预制品的基板。
10.如权利要求7所述的半导体封装件的制法，其特征在于，该半导体元件为射频芯片。
11.如权利要求7所述的半导体封装件的制法，其特征在于，该封装胶体具有外露的顶面与侧面、及结合至该基板的第一表面的底面，且该沟槽贯穿该封装胶体以连通该顶面与该基板的第一表面。
12.如权利要求11所述的半导体封装件的制法，其特征在于，该金属层形成于该封装胶体的顶面与侧面上。
13.如权利要求7所述的半导体封装件的制法，其特征在于，形成该沟槽的方式为镭射或机械切割。
14.如权利要求7所述的半导体封装件的制法，其特征在于，该金属层选自铜、镍、铁、铝或不锈钢材质。
CN201110084587.5A 2011-03-18 2011-03-31 半导体封装件及其制法 Active CN102683329B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW100109271 2011-03-18
TW100109271A TWI438885B (zh) 2011-03-18 2011-03-18 半導體封裝件及其製法

Publications (2)

Publication Number Publication Date
CN102683329A true CN102683329A (zh) 2012-09-19
CN102683329B CN102683329B (zh) 2015-05-13

Family

ID=46815024

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110084587.5A Active CN102683329B (zh) 2011-03-18 2011-03-31 半导体封装件及其制法

Country Status (3)

Country Link
US (1) US20120235259A1 (zh)
CN (1) CN102683329B (zh)
TW (1) TWI438885B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617053A (zh) * 2013-11-05 2015-05-13 天工方案公司 涉及陶瓷基板上射频装置封装的装置和方法
CN105448899A (zh) * 2014-09-30 2016-03-30 矽品精密工业股份有限公司 半导体封装件及其制法
CN106981457A (zh) * 2017-02-13 2017-07-25 武汉澳谱激光科技有限公司 用于屏蔽集成电路高密度封装电磁干扰方法及激光加工设备
CN107887344A (zh) * 2016-09-30 2018-04-06 矽品精密工业股份有限公司 电子封装结构及其制法
CN108735716A (zh) * 2017-04-25 2018-11-02 力成科技股份有限公司 封装结构
CN111696963A (zh) * 2020-07-14 2020-09-22 立讯电子科技（昆山）有限公司 封装结构及其制作方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201434129A (zh) * 2013-02-21 2014-09-01 矽品精密工業股份有限公司 多晶片封裝件及其製法
TWI554196B (zh) * 2013-07-31 2016-10-11 環旭電子股份有限公司 電子封裝模組及其製造方法
US9144183B2 (en) * 2013-07-31 2015-09-22 Universal Scientific Industrial (Shanghai) Co., Ltd. EMI compartment shielding structure and fabricating method thereof
JP5576542B1 (ja) * 2013-08-09 2014-08-20 太陽誘電株式会社 回路モジュール及び回路モジュールの製造方法
US10134729B2 (en) 2013-09-27 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical noise reduction in 3D stacked semiconductor devices
US20170117229A1 (en) * 2015-10-22 2017-04-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit package with trench features to provide internal shielding between electronic components
US10134682B2 (en) 2015-10-22 2018-11-20 Avago Technologies International Sales Pte. Limited Circuit package with segmented external shield to provide internal shielding between electronic components
US10163808B2 (en) 2015-10-22 2018-12-25 Avago Technologies International Sales Pte. Limited Module with embedded side shield structures and method of fabricating the same
TWI632662B (zh) * 2016-04-22 2018-08-11 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004172176A (ja) * 2002-11-18 2004-06-17 Taiyo Yuden Co Ltd 回路モジュール
CN101339940A (zh) * 2008-02-05 2009-01-07 日月光半导体制造股份有限公司 封装结构及其封装方法
CN101887860A (zh) * 2009-05-14 2010-11-17 群登科技股份有限公司 电子元件制造方法及其封装结构
CN101958254A (zh) * 2009-07-13 2011-01-26 日月光半导体制造股份有限公司 芯片封装体及其制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI489610B (zh) * 2010-01-18 2015-06-21 矽品精密工業股份有限公司 具電磁遮蔽之封裝結構之製法
US8576574B2 (en) * 2010-04-21 2013-11-05 Stmicroelectronics Pte Ltd. Electromagnetic interference shielding on semiconductor devices
US20120223231A1 (en) * 2011-03-01 2012-09-06 Lite-On Singapore Pte. Ltd. Proximity sensor having electro-less plated shielding structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004172176A (ja) * 2002-11-18 2004-06-17 Taiyo Yuden Co Ltd 回路モジュール
CN101339940A (zh) * 2008-02-05 2009-01-07 日月光半导体制造股份有限公司 封装结构及其封装方法
CN101887860A (zh) * 2009-05-14 2010-11-17 群登科技股份有限公司 电子元件制造方法及其封装结构
CN101958254A (zh) * 2009-07-13 2011-01-26 日月光半导体制造股份有限公司 芯片封装体及其制作方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617053A (zh) * 2013-11-05 2015-05-13 天工方案公司 涉及陶瓷基板上射频装置封装的装置和方法
US10771101B2 (en) 2013-11-05 2020-09-08 Skyworks Solutions, Inc. Devices and methods related to packaging of radio-frequency devices on ceramic substrates
CN104617053B (zh) * 2013-11-05 2020-09-11 天工方案公司 涉及陶瓷基板上射频装置封装的装置和方法
CN105448899A (zh) * 2014-09-30 2016-03-30 矽品精密工业股份有限公司 半导体封装件及其制法
CN105448899B (zh) * 2014-09-30 2018-11-23 矽品精密工业股份有限公司 半导体封装件及其制法
CN107887344A (zh) * 2016-09-30 2018-04-06 矽品精密工业股份有限公司 电子封装结构及其制法
CN107887344B (zh) * 2016-09-30 2019-11-01 矽品精密工业股份有限公司 电子封装结构及其制法
CN106981457A (zh) * 2017-02-13 2017-07-25 武汉澳谱激光科技有限公司 用于屏蔽集成电路高密度封装电磁干扰方法及激光加工设备
CN108735716A (zh) * 2017-04-25 2018-11-02 力成科技股份有限公司 封装结构
CN108735716B (zh) * 2017-04-25 2020-02-14 力成科技股份有限公司 封装结构
CN111696963A (zh) * 2020-07-14 2020-09-22 立讯电子科技（昆山）有限公司 封装结构及其制作方法

Also Published As

Publication number Publication date
TW201240056A (en) 2012-10-01
CN102683329B (zh) 2015-05-13
US20120235259A1 (en) 2012-09-20
TWI438885B (zh) 2014-05-21

Similar Documents

Publication Publication Date Title
CN102683329B (zh) 半导体封装件及其制法
CN105448899B (zh) 半导体封装件及其制法
CN105304582B (zh) 封装结构及其制法
CN108807304B (zh) 半导体封装元件
CN105097784A (zh) 半导体封装件及其制法
CN107910319B (zh) 半导体封装装置及其制造方法
TWI491010B (zh) 微小化電磁干擾防護結構及其製作方法
JP6571124B2 (ja) 電子部品モジュールの製造方法
US20220020699A1 (en) Package structure and method of manufacturing the same
CN103165563B (zh) 半导体封装件及其制法
CN102760715A (zh) 嵌埋电子组件的封装结构及其制法
CN107104094A (zh) 封装结构及其制法
CN105990318A (zh) 半导体装置封装和其制造方法
KR20170067947A (ko) 측면 차폐부를 가지는 반도체 패키지 및 제조 방법
CN103915408A (zh) 半导体封装件及其制法
CN104009006A (zh) 封装基板及其制法暨半导体封装件及其制法
CN108074826A (zh) 电子封装件及其制法
CN102867801A (zh) 半导体承载件暨封装件及其制法
CN103021969B (zh) 基板、半导体封装件及其制法
CN105304583A (zh) 封装结构及其制法
CN103632980A (zh) 封装基板的制法
CN104576616B (zh) 模块集成电路封装结构及其制作方法
CN104124212A (zh) 半导体封装件及其制法
US9704812B1 (en) Double-sided electronic package
CN102543961B (zh) 防静电破坏及防电磁波干扰的封装件及其制法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant