CN101958254A - 芯片封装体及其制作方法 - Google Patents

芯片封装体及其制作方法 Download PDF

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CN101958254A
CN101958254A CN2009102619443A CN200910261944A CN101958254A CN 101958254 A CN101958254 A CN 101958254A CN 2009102619443 A CN2009102619443 A CN 2009102619443A CN 200910261944 A CN200910261944 A CN 200910261944A CN 101958254 A CN101958254 A CN 101958254A
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packing
chip
substrate
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廖国宪
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Advanced Semiconductor Engineering Inc
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Abstract

一种芯片封装体，包括防护层，其中防护层共形地覆盖其下的封装胶体。防护层可平滑地覆盖封装胶体并配置于封装胶体的圆的或钝的顶部边缘上，以加强电磁干扰的防护效果。

Description

芯片封装体及其制作方法
技术领域
本发明涉及一种半导体元件，特别是涉及一种芯片封装体。
背景技术
对于大部分的电子元件或系统而言，电磁干扰(Electro-magneticinterference，EMI)是一个严重且具有挑战性的问题。由于电磁干扰通常会中断、降低或是限制电子元件或是电子系统的所有电路的有效性能，因此，电子元件或系统需具有有效的电磁干扰防护以确保可有效且安全的运作。
电磁干扰防护对于小尺寸且高密度的封装体或是高频运作的敏感性电子元件特别地重要。在已知技术中，电磁干扰的防护方式是在电子元件上贴附或固定金属片及/或导电垫片，然而，前述防护方式会增加制作成本。
发明内容
本发明提供一种芯片封装体的制作方法，其设计弹性较高且较为简易。
本发明提供一种芯片封装体，其对于电磁干扰的防护功效较佳。
本发明提出一种芯片封装体的制作方法如下所述。首先，提供基板条，基板条具有多个基板单元，且多条锯切线定义出各基板单元。接着，提供至少一芯片于各基板单元上，其中芯片电性连接至基板单元。然后，在基板条上形成封装胶体以包覆芯片。之后，沿着锯切线对封装胶体进行研磨工艺，以使封装胶体的多个顶部边缘呈非直角状，以及进行切单工艺，以沿着锯切线切穿基板条而形成多个独立的芯片封装体。之后，在封装胶体上形成防护层，以共形地覆盖封装胶体。
本发明提出一种芯片封装体，包括基板、至少一芯片、封装胶体以及防护层。芯片配置于基板上并电性连接至基板。封装胶体配置于基板上，并至少包覆芯片与部分基板，其中封装胶体的多个顶部边缘呈非直角状。防护层配置于封装胶体上，其中防护层共形地覆盖封装胶体的顶部边缘、顶面与多个侧壁，且防护层电性连接至基板。
本发明提出一种芯片封装体，包括基板、至少一芯片、封装胶体以及防护层。芯片配置于基板上，并电性连接至基板。封装胶体配置于基板上，并至少包覆芯片与部分基板。防护层配置于封装胶体上，其中防护层的顶部边缘呈非直角状，且防护层电性连接至基板。
在此，本发明可避免防护层在封装胶体的垂直弯角或边缘上容易产生裂缝的问题，且防护层可均匀地覆盖芯片封装体的封装胶体并提供有效的芯片封装体电磁干扰防护。在本发明中，由于有完整的防护层覆盖，故可提升封装体的可靠度以及防护的效果。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A～图1G绘示本发明实施例的芯片封装体的工艺剖面图。
图2A～图2C绘示本发明另一实施例的芯片封装体的工艺中的某些步骤的剖面图。
图3绘示本发明实施例的芯片封装体的剖面图。
图4绘示本发明另一实施例的芯片封装体的剖面图。
图5绘示本发明另一实施例的芯片封装体的剖面图。
附图标记说明
10、30、40、50：芯片封装体
100：基板条
102：基板
102a：顶面
102b：底面
104：接点
106：凸块
108：接地通道
109：接地面
120：芯片
130：封装胶体
130a：顶面
130b：侧壁
130e：顶部边缘
135：研磨纹路
135a、135b：斜面
137：沟槽
140：防护层
140e：顶部边缘
a、A：宽度
d：研磨深度
D：厚度
θ1、θ2、θ3：钝角
具体实施方式
本发明的芯片封装体的制作方法可用来制作各种封装结构，且较适于制作堆叠式封装体、多芯片封装体或高频元件封装体(包括射频元件封装体)
图1A～图1G绘示本发明实施例的芯片封装体的工艺剖面图。图1D’与图1D”绘示图1D的结构的立体图，图1D的结构具有放大图A或放大图B中的研磨槽(grinding trench)。
请参照图1A，提供基板条100，基板条100具有多个基板102(之后将形成的多条切割线可定义出这些基板102，切割线如图1A中的虚线所示)，其中各基板102包括多个配置于其上的接点104以及配置于其中的至少一接地通道(ground via)108。在倒装接合时，接点104可作为凸块垫。基板条100可为压合板(laminate substrate)，例如印刷电路板(printed circuit board，PCB)。本实施例包括现行的各种接地通道108，接地通道108位于基板102中。对于压合板而言，接地通道可贯穿整个基板(例如从顶面延伸至底面)，或者是从顶面或底面延伸至基板的内层，又或者是延伸于基板的二内层之间。接地通道的尺寸可依据产品的电性品质来作调整，且镀通孔(platedthrough-hole，PTH)或是填满焊料的槽孔可构成接地通道/插塞(plug)。此外，可用配置有导电焊料块的接地垫来取代接地通道，其中导电焊料块位于基板的上表面上。
请参照图1B，至少一芯片120配置在各基板102的顶面102a上。虽然本实施例是在基板102上配置芯片120，然而，在其他实施例中，也可以是在基板102上配置其他的表面粘着元件。芯片120通过多个凸块106电性连接至基板102的多个接点104，其中凸块106位于芯片120与接点104之间。虽然在此描述的是倒装接合技术，在其他实施例中，亦可以是应用引线接合技术(例如通过导线连接)。芯片120优选地配置在基板102的中心区域中。
请参照图1C，进行封胶工艺，以在基板条100上形成封装胶体130，其中封装胶体130包覆芯片120、接点104、凸块106以及至少部分的基板102。封胶工艺例如为覆盖成型工艺(over-molding process)。封装胶体130的材料例如为环氧树脂(epoxy resin)或硅胶(silicon resin)。
请参照图1D，进行研磨工艺，以移除部分的封装胶体130而形成多条研磨纹路(研磨槽)135。研磨纹路135位于芯片120的周边。优选地，封装胶体130中的研磨纹路135位于各基板102的边界或边缘的正上方。图1D’与图1D”绘示图1D的结构的立体图，图1D的结构具有放大图A或放大图B中的研磨槽。如图1D与图1D’所示，研磨纹路135位于基板102的边界线(虚线)上。在本实施例中，之后的锯切工艺(sawing process)将切过研磨纹路135，其中研磨纹路135位于锯切线(sawing line)上(如虚线所示)。研磨工艺例如为斜圆盘研磨工艺(oblique disc grinding process)。斜圆盘研磨工艺是将具有斜刀片的研磨圆盘切进封装胶体中以形成内壁倾斜的沟槽。以位于各基板102的边界正上方的研磨纹路135为例，研磨工艺可在封装胶体130内形成环形沟槽(ring-shaped trench)，其中环形沟槽沿着各基板102的边界。
详细而言，如图1D、图1D’以及图1D”所示，研磨纹路135优选为具有反帽型(reverse-hat)截面的环状沟槽(例如沟槽的底部较窄且沟槽的顶部较宽)。换言之，研磨工艺可使封装胶体130的顶部边缘130e呈非正交(non-orthogonal)状或非直角(non-right-angular)状。优选地，研磨工艺可磨钝封装胶体130的顶部边缘130e。封装胶体130的顶部边缘130e不是具有一个钝角θ1(如放大图A所示)就是具有二个钝角θ2、θ3(如放大图B所示)。举例来说，对于研磨纹路135而言，钝角θ1(夹于研磨纹路135的斜面135a以及封装胶体130的顶面130a之间)的角度范围约介于95°～165°之间，而钝角θ2(夹于研磨纹路135的斜面135a以及斜面135b之间)与钝角θ3(夹于研磨纹路135的斜面135b与封装胶体130的顶面130a之间)的角度范围约介于100°～160°之间。优选地，研磨深度d的范围约为封装胶体130的厚度D的1/5倍至1/3倍。一般而言，研磨纹路135的深度大小可依防护需求(shielding requisite)、封装体的电性品质或是工艺参数而调整。
请参考图1E，可选择性地进行半切切割工艺(half-cutting process)以移除部分的封装胶体130，直到暴露出基板102的部分顶面102a。一般来说，半切切割工艺是切过锯切线上的研磨纹路135，并切透封装胶体130直至基板条100，以形成预定深度并形成多个沟槽137。优选地，半切切割工艺的切割宽度(例如沟槽137的宽度a)小于研磨纹路135的宽度A(例如研磨工艺的研磨宽度A)。在本实施例中，即使在半切切割工艺之后，封装胶体130仍然保有钝化的顶部边缘130e。接地通道的位置或排列可随产品需求而调整。接地通道例如位于锯切线上，且半切切割工艺或切单工艺(singulationprocess)可切过接地通道。在图1E中，半切切割工艺是切进位于锯切线上的接地通道108。虽然在本实施例中，半切切割工艺是在研磨工艺之后进行，但是，在其他实施例中，也可以是在研磨工艺之前进行半切切割工艺。当半切切割工艺是在研磨工艺之前进行时，随后的研磨工艺仍可钝化半切切割封装胶体的顶部边缘。
之后，请参照图1F，在封装胶体130上形成防护层140，以共形地(conformally)覆盖封装胶体130的顶面130a、侧壁130b以及顶部边缘130e。形成防护层140的方法例如是以喷涂法(spray coating method)、电镀法(plating method)或是溅镀法(sputtering method)沉积金属材料(未绘示)，以共形地覆盖封装胶体130以及基板条100的被沟槽137所暴露出的部分。金属材料例如为铝、铜、铬、金、银、镍、焊料或是前述的组合。
原则上，封装胶体的顶部边缘既非锐角亦非直角，因为锐角或直角的顶部边缘的披覆性质较差(例如披覆层易形成裂缝)。由于本实施例的封装胶体130的顶部边缘130e不是钝的就是圆的，因此，有助于增加防护层140的覆盖性(coverage)以及顺应性(conformity)。由于防护层很少或是没有裂缝，且防护层均匀地覆盖弯角或边缘，故可增加防护层的防护性以及提升封装体的可靠度。
请参照图1G，对基板条100的底面102b进行切单工艺以切割锯切线并切穿基板条100，以形成多个独立的芯片封装体10。切单工艺例如为刀具切割工艺或激光切割工艺。
在下述的实施例中，可进一步地修改以及描述述图1A至图1G所示的芯片封装体的制作方法。又或者是，依序进行图1A至图1C的工艺步骤，然后进行切单工艺，以沿着锯切线切穿封装胶体130以及基板条100，从而形成多个独立的芯片封装体10。切单工艺亦切穿基板条100中的接地通道108。切单工艺例如为刀具切割工艺或激光切割工艺。在此，封装胶体130的顶面130a与侧壁130b的交界处标示为封装胶体130的顶部边缘130e。如图2A所示，在切单工艺之后，封装胶体130的顶部边缘130e大致上呈直角状。
之后，请参照图2B，进行研磨工艺，以钝化芯片封装体10的封装胶体130的顶部边缘130e。当切单工艺切过锯切线时，在封装胶体130的顶部边缘130e上进行研磨工艺，其中顶部边缘130e位于各基板102的边界或周边的正上方。承上述，在研磨工艺之前，顶部边缘130e实质上呈直角状，而研磨工艺可使封装胶体130的顶部边缘130e钝化或圆化。研磨工艺例如为斜圆盘研磨工艺或圆研磨工艺。如图2B所示，封装胶体130的顶部边缘130e在经过研磨工艺之后会被圆化。无论如何，在本发明的实施例中，封装胶体130的顶部边缘130e不是钝的(例如具有至少一钝角，如图1D中的放大图A与放大图B所示)就是圆的(例如具有圆弧面，如图2B中的上方放大图所示)。此外，可依据工艺参数而调整钝的或圆的顶部边缘的角度或曲率。
在图2B之后，如图2C所示，在封装胶体130上共形地形成防护层140，以覆盖封装胶体130的顶面130a、侧壁130b以及圆的顶部边缘130e。形成防护层140的方法例如是以喷涂法、电镀法或是溅镀法沉积金属材料(未绘示)，以覆盖封装胶体130以及各基板102的侧壁。
换言之，由于防护层140共形地覆盖封装胶体130的钝的或圆的顶部边缘130e(如图2C中上方局部放大图所示)，故防护层140亦具有钝的或圆的顶部边缘140e(例如在封装胶体130的顶部边缘130e上方的圆滑面)。
图3绘示本发明实施例的芯片封装体的剖面图。请参照图3，本实施例的芯片封装体30包括基板102、多个接点104、多个凸块106、至少一芯片120、封装胶体130以及防护层140。基板102可为压合板，例如双层或四层压合印刷电路板。芯片120可为半导体芯片，例如射频(radio-frequency，RF)芯片。防护层140的材料例如是铜、铬、金、银、镍、铝或是前述的合金或是焊料。芯片120通过接点(凸块垫)104以及凸块106电性连接至基板102。封装胶体130包覆部分基板102、凸块106以及芯片120。如图3所示，防护层140配置于封装胶体130上，以覆盖封装胶体130的顶面130a、侧壁130b以及钝的顶部边缘130e。封装胶体130的顶面130a与侧壁130b的交界之处在此标示为封装胶体130的顶部边缘130e，而封装胶体130的钝的顶部边缘130e的详细剖面图形相似于图1D的放大图B。由于半切切割工艺沿着锯切线切穿封装胶体130是在形成防护层140之前进行，因此，封装胶体130可完全被防护层140所覆盖而不会暴露于芯片封装体30之外。防护层140通过直接接触基板102的至少一接地通道108而电性连接至基板102，且防护层140可通过接地通道108而接地。因此，利用基板的金属线或通道，本实施例的防护层可通过基板的接地面而在封装结构中接地。防护层可在封装结构中建立接地路径，而毋须使用外加的接地面。
图4绘示本发明另一实施例的芯片封装体的剖面图。请参照图4，芯片封装体40主要相似于图3的封装结构，两者的差异之处在于芯片封装体40的封装胶体130的圆的顶部边缘130e。封装胶体130的圆的顶部边缘130e的详细剖面图形相似于图2B的放大图。由于在形成防护层140之前切单工艺沿着锯切线切穿封装胶体130与基板条100，因此，基板102的侧壁与封装胶体130可全面地被防护层140所覆盖且不会暴露于芯片封装体40外。防护层140通过直接接触基板102的至少一接地通道(例如为接地插塞/填满焊料的槽孔)108而电性连接至基板102，且防护层140可通过接地通道108而接地。
图5绘示本发明另一实施例的芯片封装体的剖面图。请参照图5，芯片封装体50主要相似于图4的封装结构。此外，封装胶体130的钝的顶部边缘130e的详细剖面图相似于图1D的放大图A。基板102与封装胶体130的侧壁被防护层140全面覆盖，且不会暴露于芯片封装体50之外。防护层140通过直接接触基板102的至少一接地面109而电性连接至基板102，且可通过接地面109而接地。
简言之，由于研磨工艺有钝化或圆化的效果，故可钝化(具有钝角)或圆化封装胶体的顶部边缘以及顶部弯角，且之后形成的防护层可覆盖封装胶体而无裂缝。在本实施例的芯片封装结构中，配置在封装胶体与基板上的防护层可作为电磁干扰防护，以保护封装体免于受到周围辐射源(radiationsource)的电磁干扰。在本实施例中，均匀覆盖封装胶体(特别是在顶部边缘与弯角的周围)的防护层可有效加强封装体对于电磁干扰的防护效果。此外，封装体的可靠度增加。因为封装结构的顶部边缘以及顶部弯角被圆化或是钝化，故可减少发生在弯角的漏损量，进而提升封装结构的电性效能。因此，此种设计可应用在高频率的封装元件中，特别是射频元件。
虽然本发明已以实施例披露如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求所界定为准。

Claims (20)

1.一种芯片封装体的制作方法，包括：
提供基板条，该基板条具有多个基板单元，且多条锯切线定义出各基板单元；
提供至少一芯片于各基板单元上，其中该芯片电性连接至该基板单元；
在该基板条上形成封装胶体以包覆该多个芯片；
沿着该多条锯切线对该封装胶体进行研磨工艺，以使该封装胶体的多个顶部边缘呈非直角状；
进行切单工艺，以沿着该多条锯切线切穿该基板条而形成多个独立的芯片封装体；以及
在该封装胶体上形成防护层，以共形地覆盖该封装胶体。
2.如权利要求1所述的芯片封装体的制作方法，其中在进行该切单工艺之前，先进行该研磨工艺。
3.如权利要求2所述的芯片封装体的制作方法，其中在形成该防护层之前，先进行该切单工艺。
4.如权利要求2所述的芯片封装体的制作方法，其中该研磨工艺包括斜圆盘研磨工艺。
5.如权利要求2所述的芯片封装体的制作方法，还包括：
在进行该研磨工艺之后，对该封装胶体进行半切切割工艺；以及
在该半切切割工艺之后并在该切单工艺之前，形成该防护层。
6.如权利要求5所述的芯片封装体的制作方法，其中该半切切割工艺的切割宽度小于该研磨工艺的研磨宽度。
7.如权利要求2所述的芯片封装体的制作方法，还包括：
在进行该研磨工艺之前，对该封装胶体进行半切切割工艺；以及
在该研磨工艺之后并在该切单工艺之前，形成该防护层。
8.如权利要求1所述的芯片封装体的制作方法，其中该研磨工艺在进行该切单工艺之后才进行，且该研磨工艺沿着各基板单元的边界线在各独立的芯片封装体的该封装胶体上进行。
9.如权利要求8所述的芯片封装体的制作方法，其中该研磨工艺包括圆研磨工艺或斜圆盘研磨工艺。
10.如权利要求1所述的芯片封装体的制作方法，其中该防护层的形成方法包括喷涂法、电镀法或溅镀法。
11.一种芯片封装体，包括：
基板；
至少一芯片，配置于该基板上并电性连接至该基板；
封装胶体，配置于该基板上，并至少包覆该芯片与部分该基板，其中该封装胶体的多个顶部边缘呈非直角状；以及
防护层，配置于该封装胶体上，其中该防护层共形地覆盖该封装胶体的该多个顶部边缘、顶面与多个侧壁，且该防护层电性连接至该基板。
12.如权利要求11所述的芯片封装体，其中该防护层通过该基板的至少一接地通道电性连接该基板。
13.如权利要求11所述的芯片封装体，其中该封装胶体的非直角的该多个顶部边缘是钝的或圆的。
14.如权利要求13所述的芯片封装体，其中该封装胶体的钝的该多个顶部边缘具有至少一钝角，且该钝角夹于该封装胶体的该侧壁与该顶面之间。
15.如权利要求14所述的芯片封装体，其中该钝角的角度范围介于95°～165°之间。
16.一种芯片封装体，包括：
基板；
至少一芯片，配置于该基板上，并电性连接至该基板；
封装胶体，配置于该基板上，并至少包覆该芯片与部分该基板；以及
防护层，配置于该封装胶体上，其中该防护层的多个顶部边缘呈非直角状，且该防护层电性连接至该基板。
17.如权利要求16所述的芯片封装体，其中该防护层通过该基板的至少一接地通道电性连接该基板。
18.如权利要求16所述的芯片封装体，其中该防护层的非直角的该多个顶部边缘是钝的或圆的。
19.如权利要求18所述的芯片封装体，其中该防护层的钝的该多个顶部边缘具有至少一钝角，该钝角的角度范围介于95°～165°之间。
20.如权利要求16所述的芯片封装体，其中该防护层的材料包括铝、铜、铬、金、银、镍、焊料或是前述的组合。
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