CN105261570A - 半导体封装及其制造方法 - Google Patents
半导体封装及其制造方法 Download PDFInfo
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- CN105261570A CN105261570A CN201510404234.7A CN201510404234A CN105261570A CN 105261570 A CN105261570 A CN 105261570A CN 201510404234 A CN201510404234 A CN 201510404234A CN 105261570 A CN105261570 A CN 105261570A
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- semiconductor chip
- groove
- mold layer
- semiconductor substrate
- semiconductor
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Abstract
本发明构思的实施方式提供了半导体封装及其制造方法。该方法包括形成凹槽以使第一半导体芯片彼此分离。形成凹槽包括:在半导体基板的底表面上进行第一切片工艺以在相对于该底表面倾斜的方向上切割半导体基板以及模层的一部分,以及进行第二切片工艺以在基本上垂直于半导体基板的底表面的方向上切割模层。通过第一切片工艺形成在半导体基板中的凹槽的最小宽度可以大于通过第二切片工艺形成在模层中的凹槽的宽度。
Description
技术领域
本发明构思涉及半导体,更具体地,涉及具有穿孔(through-via)的多芯片半导体封装及其制造方法。
背景技术
随着电子产业的发展,可以以低价提供轻、小、高速且高性能的电子产品。集成电路芯片可以被容纳在半导体封装中从而在电子产品中使用。已经进行了各种研究以改善半导体封装的性能。具体地,由于需要高性能的半导体封装,所以已经发展了硅穿孔(TSV)技术代替常规引线接合技术用于半导体封装。
发明内容
本发明构思的实施方式针对具有多个层叠的半导体芯片的可靠半导体封装及其制造方法。
在一个方面中,一种制造半导体封装的方法可以包括:提供具有顶表面的半导体基板,芯片叠层安装在该顶表面上,每个芯片叠层包括多个层叠的半导体芯片;在半导体基板的顶表面上形成覆盖芯片叠层的模层(moldlayer);以及通过在半导体基板的底表面上进行切片工艺(sawingprocess),形成穿透半导体基板和模层的凹槽。该凹槽可以包括:第一侧壁,与半导体基板的顶表面相邻并在相对于半导体基板的底表面倾斜的方向上延伸;第二侧壁,连接到第一侧壁并在基本上垂直于半导体基板的底表面的方向上延伸;以及边缘,形成在第一侧壁与第二侧壁相接的位置处。该边缘可以形成在模层中。
在一些实施方式中,形成在半导体基板中的凹槽的最大宽度可以大于形成在模层中的凹槽的最大宽度。
在一些实施方式中,形成凹槽可以包括:从半导体基板的底表面朝向模层切割半导体基板以形成具有第一侧壁的第一凹槽,该模层沿着第一凹槽的第一侧壁暴露;以及切割通过第一凹槽暴露的模层以形成具有第二侧壁的第二凹槽。
在一些实施方式中,第一侧壁可以与半导体基板的底表面成钝角。
在一些实施方式中,半导体基板可以包括基底半导体芯片,该基底半导体芯片具有穿过其的穿孔,芯片叠层可以分别电连接到基底半导体芯片。
在一些实施方式中,半导体基板可以通过凹槽被分成基底半导体芯片并且模层可以通过凹槽被分成单元模层(unitmoldlayer)。彼此相邻的基底半导体芯片之间的最小距离可以大于分别设置在彼此相邻的基底半导体芯片上的单元模层之间的最小距离。
在一些实施方式中,芯片叠层的半导体芯片的有源表面可以面对半导体基板。
在一些实施方式中,凹槽可以穿过设置在一对相邻的芯片叠层之间的模层。
在一些实施方式中,半导体基板可以包括:覆盖底表面的硅氮化物层;以及形成在底表面上的外部端子诸如焊球。硅氮化物层可以被暴露。
在另一方面中,一种制造半导体封装的方法可以包括:制备包括第一半导体芯片的半导体基板;在半导体基板的顶表面上安装第二半导体芯片;在半导体基板的顶表面上形成覆盖第二半导体芯片的模层;以及形成穿透半导体基板和模层的凹槽以使第一半导体芯片彼此分离。形成凹槽可以包括:在半导体基板的底表面上进行第一切片工艺以在相对于半导体基板的底表面倾斜的方向上切割半导体基板以及模层的一部分;以及进行第二切片工艺以在基本上垂直于半导体基板的底表面的方向上切割模层。通过第一切片工艺形成在半导体基板中的凹槽的最小宽度可以大于通过第二切片工艺形成在模层中的凹槽的宽度。
在一些实施方式中,可以进行第二切片工艺以与半导体基板间隔开。
在一些实施方式中,通过第一切片工艺形成的凹槽可以具有倾斜侧壁,并且半导体基板和模层可以沿着倾斜侧壁暴露。
在一些实施方式中,第一半导体芯片可以包括:第一集成电路层;覆盖第一集成电路层的钝化层;穿透第一半导体芯片并连接到第一集成电路层的第一穿孔;以及电连接到第一集成电路层的外部端子诸如焊球。钝化层(例如,硅氮化物层)可以被暴露。
在一些实施方式中,该方法还可以包括:在第二半导体芯片上安装第三半导体芯片。每个第二半导体芯片可以具有穿透每个第二半导体芯片的穿孔。
在一些实施方式中,半导体基板可以通过第一切片工艺被分成第一半导体芯片,模层可以通过第二切片工艺被分成单元模层。彼此相邻的第一半导体芯片之间的最小距离可以大于分别设置在彼此相邻的第一半导体芯片上的单元模层之间的最小距离。
在另一个方面中,一种半导体封装可以包括:第一半导体芯片,具有底表面、与底表面相反的顶表面以及侧壁;第二半导体芯片,安装在第一半导体芯片的顶表面上;以及模层,提供在第一半导体芯片的顶表面上并覆盖第二半导体芯片的侧壁。第一半导体芯片的侧壁可以与第一半导体芯片的底表面成钝角。模层可以包括:倾斜侧壁,与第一半导体芯片的侧壁基本上共平面;竖直侧壁,提供在倾斜侧壁上并在垂直于第一半导体芯片的底表面的方向上延伸;以及边缘,形成在倾斜侧壁与竖直侧壁相接的位置处。
在一些实施方式中,模层的外侧壁之间的最大宽度可以大于第一半导体芯片的最大宽度。
在一些实施方式中,第一半导体芯片可以具有穿过第一半导体芯片的第一穿孔,第一半导体芯片的底表面可以是有源表面。第二半导体芯片的有源表面可以面对第一半导体芯片。
在一些实施方式中,第一半导体芯片的宽度可以从第一半导体芯片的底表面朝向顶表面逐渐变大。
在一些实施方式中,半导体封装还可以包括安装在第二半导体芯片上的第三半导体芯片。第二半导体芯片可以具有穿过该第二半导体芯片的穿孔。
在一些实施方式中,第三半导体芯片的厚度可以不同于第二半导体芯片的厚度。
在一些实施方式中,第一半导体芯片可以包括:设置在其底表面上的钝化层(例如,硅氮化物层);以及电连接到穿孔的外部端子(例如,焊球)。钝化层可以被暴露。
在一些实施方式中,第一半导体芯片的底表面可以不用聚合物层覆盖,第一半导体芯片的侧壁可以不用模层覆盖。
在一些实施方式中,半导体封装还可以包括设置在第一和第二半导体芯片之间的凸块。第二半导体芯片可以通过凸块电连接到第一半导体芯片。
在一些实施方式中,第三半导体芯片的顶表面通过模层暴露。
在一些实施方式中,一种制造半导体封装的方法可以包括:提供具有顶表面的半导体基板,芯片叠层安装在该顶表面上,每个芯片叠层包括多个层叠的半导体芯片;在半导体基板的顶表面上形成覆盖芯片叠层的模层;以及形成穿过半导体基板的第一凹槽,该第一凹槽具有相对于半导体基板的底表面倾斜的第一侧壁;以及形成穿过模层且在基本上垂直于半导体基板的底表面的方向上延伸的第二凹槽,以形成彼此分离的封装单元,其中第二凹槽包括连接到第一侧壁的第二侧壁,第二凹槽通过第一凹槽暴露。
在一些实施方式中,边缘形成在第一侧壁与第二侧壁相接的位置处,其中边缘形成在模层中。
在一些实施方式中,边缘形成在第一侧壁与第二侧壁相接的位置处,其中边缘形成在半导体芯片的侧壁上。
在一些实施方式中,形成第一凹槽包括:利用具有V形截面的刀片在半导体基板的底表面上朝向模层进行切片工艺以形成第一凹槽,其中形成第二凹槽包括:利用具有基本上矩形截面的第二刀片在通过第一凹槽暴露的模层上进行另一切片工艺。
在一些实施方式中,形成在模层中的第二凹槽的宽度小于第一凹槽在半导体基板的底表面处的宽度,其中形成在模层中的第二凹槽的宽度基本上等于第一凹槽在半导体基板的顶表面处的宽度。
附图说明
考虑到附图以及伴随的详细说明,本发明构思将变得更明显。
图1A至1F是示出根据本发明构思的一些实施方式的制造半导体封装的方法的截面图;
图1G是在诸如切片工艺的分离(singulation)工艺之后封装单元的放大截面图;
图1H是示出根据本发明构思的一些实施方式制造的封装单元中的一个的截面图;
图1I是图1H的第一半导体芯片和模层的放大图;
图2A和2B是示出根据本发明构思的另一些实施方式的制造半导体封装的方法的截面图;
图2C是示出在诸如切片工艺的分离工艺之后封装单元的示例的截面图;
图2D是示出根据本发明构思的另一些实施方式制造的封装单元中的一个的截面图;
图2E是图2D的第一半导体封装和模层的放大图;
图3A和3B是示出根据本发明构思的另一些实施方式的制造半导体封装的方法的截面图;
图3C是示出在诸如切片工艺的分离工艺之后封装单元的示例的截面图;
图3D是示出根据本发明构思的另一些实施方式制造的封装单元中的一个的截面图;
图3E是图3D的第一半导体封装和模层的放大图;
图4是示出包含根据本发明构思的实施方式的半导体封装的封装模块的示例的图示;
图5是示出包括根据本发明构思的实施方式的半导体封装的电子系统的示例的示意性方框图;以及
图6是示意性框图,示出包括根据本发明构思的实施方式的半导体封装的存储卡的示例。
具体实施方式
在下文将参照附图更全面地描述本发明构思,附图中示出了本发明构思的示范性实施方式。本发明构思的优点和特征以及实现它们的方法将从以下示范性实施方式而变得明显,将参照附图更详细地描述这些示范性实施方式。然而,应当理解,本发明构思不限于以下示范性实施方式,而是可以以各种形式实现。因此,示范性实施方式仅被提供来公开本发明构思并让本领域技术人员了解本发明构思的范畴。在附图中,本发明构思的实施方式不限于这里提供的特定示例,并且为了清晰而被夸大。
这里使用的术语仅是为了描述具体实施方式的目的,而不意在限制本发明。当在这里使用时,单数术语“一”和“该”也旨在包括复数形式,除非上下文另外清楚地表示。当在这里使用时,术语“和/或”包括一个或多个相关所列项目的任意和所有组合。将理解,当一元件被称为“连接”或“联接”到另一元件时,它可以直接连接或联接到该另一元件或者可以存在居间元件。
类似地,将理解,当一元件诸如层、区域或基板被称为“在”另一元件“上”时,它可以直接在该另一元件上,或者可以存在居间元件。相反,术语“直接”表示没有居间元件。还将理解,当在这里使用时,术语“包括”、“包含”表示所述特征、整数、步骤、操作、元件和/或部件的存在,但是不排除一个或更多其它特征、整数、步骤、操作、元件、部件和/或其组的存在或添加。
另外,详细描述中的实施方式将通过作为本发明构思的理想示范性视图的截面图来描述。因此,示范性视图的形状可以根据制造技术和/或容许误差改变。因此,本发明构思的实施方式不限于示范性视图中示出的特定形状,而是可以包括可根据制造工艺产生的其它形状。在附图中举例说明的区域具有一般的性质,并用于示出元件的特定形状。因而,这不应被解释为限于本发明构思的范围。
还将理解,尽管这里可以使用术语第一、第二、第三等来描述各种元件,但是这些元件不应受到这些术语限制。这些术语仅用于将一个元件与另一元件区别开。因此,在一些实施方式中的第一元件可以在另一些实施方式中被称为第二元件,而没有背离本发明构思的教导。这里说明和示出的本发明构思的各方面的示范性实施方式包括它们的互补对应物。相同的附图标记或相同的参考指示符在整个说明书中表示相同的元件。
此外,这里参照截面图和/或平面图描述示范性实施方式,这些图是理想化的示范性图示。因而,由例如制造技术和/或公差引起的图示形状的偏差是可预期的。因而,示范性实施方式不应被解释为限于这里示出的区域的形状,而是将包括由例如制造引起的形状偏差。例如,被示出为矩形的蚀刻区域可以具有圆化或弯曲的特征。因而,附图中示出的区域在本质上是示意性的,它们的形状不旨在示出器件的区域的实际形状,并且不旨在限制示范实施方式的范围。
如本发明构思实体理解的,根据这里描述的各种实施方式的器件和形成器件的方法可以体现在诸如集成电路的微电子器件中,其中根据这里描述的不同实施方式的多个器件被集成在同一微电子器件中。因此,这里示出的截面图可以在微电子器件中的两个不同方向(它们不需要垂直)上重复。因此,体现根据这里描述的不同实施方式的器件的微电子器件的平面图可以基于微电子器件的功能而包括成阵列和/或二维图案的多个器件。
根据这里描述的各种实施方式形成的器件可以根据微电子器件的功能性而配置于其它器件当中。此外,根据这里描述的各种实施方式形成的微电子器件可以在可垂直于所述两个不同方向的第三方向上重复,以提供三维集成电路。
因此,这里示出的截面图提供对于根据这里描述的各种实施方式的多个器件的支持,该多个器件在平面图中沿着两个不同方向延伸和/或在透视图中在三个不同方向上延伸。例如,当单个有源区在器件/结构的截面图中示出时,该器件/结构可以包括多个有源区以及在其上的晶体管结构(或存储器单元结构、栅结构等,根据情况而定),如将由该器件/结构的平面图所示出的。
在下文将描述根据本发明构思的实施方式的制造半导体封装的方法。
图1A至图1F是示出根据本发明构思的一些实施方式的制造半导体封装的方法的截面图。
参照图1A,第一半导体芯片110可以设置在载体基板105上。例如,包括一个或多个第一半导体芯片110的半导体基板100可以通过插置在其间的载体粘合层106而接合到载体基板105的顶表面。半导体基板100可以是由半导体诸如硅形成的晶片级半导体基板。第一半导体芯片110可以包括第一集成电路层111和第一穿孔115。第一集成电路层111可以与第一半导体芯片110的底表面110a相邻。第一集成电路层111可以包括存储器电路、逻辑电路或其组合。第一穿孔115可以穿透第一半导体芯片110并可以电连接到第一集成电路层111。钝化层诸如硅氮化物层113可以覆盖第一集成电路层111。外部端子诸如外部焊球114可以提供在第一半导体芯片110的底表面110a上并可以通过焊盘112电连接到第一集成电路层111。第一半导体芯片110的底表面110a可以包含有源表面。硅氮化物层113可以不覆盖外部焊球114。根据本发明构思的一些实施方式,聚合物层(未示出)诸如光敏聚酰亚胺层可以不形成在硅氮化物层113上。因而,硅氮化物层113可以在第一半导体芯片110的底表面110a处暴露。
参照图1B,芯片叠层S可以安装在半导体基板100的每个第一半导体芯片110上。每个芯片叠层S可以包括多个层叠的半导体芯片120和130。第二半导体芯片120可以安装在第一半导体芯片110上以形成晶片上芯片(COW)结构。第二半导体芯片120可以包括第二集成电路层121和第二穿孔125。第二集成电路层121可以包括存储器电路。第二穿孔125可以穿透第二半导体芯片120并可以电连接到第二集成电路层121。第二半导体芯片120的底表面120a可以包含有源表面。第一凸块109可以形成在第二半导体芯片120的底表面120a上以将第二半导体芯片120电连接到第一半导体芯片110。例如,第一凸块109可以形成在第一半导体芯片110和第二半导体芯片120之间。在图1B中,多个第二半导体芯片120可以顺序地层叠在第一半导体芯片110上。可选地,单个第二半导体芯片120可以设置在第一半导体芯片110上。如果提供多个第二半导体芯片120,则第二凸块119可以形成在层叠的第二半导体芯片120之间。
第三半导体芯片130可以安装在第二半导体芯片120上。第三半导体芯片130的底表面130a可以包含有源表面。第三半导体芯片130可以包括第三集成电路层131。第三集成电路层131可以包括存储器电路。第三集成电路层131可以不具有穿孔。第三半导体芯片130的厚度可以不同于第二半导体芯片120的厚度。第三半导体芯片130的厚度可以被调节以控制完成的半导体封装的总厚度。第三凸块129可以形成在第二半导体芯片120和第三半导体芯片130之间。第三半导体芯片130可以通过第三凸块129电连接到第二半导体芯片120。在另一些实施方式中,第三半导体芯片130可以被省略。
由绝缘材料诸如聚合物形成的粘合层140可以提供在半导体芯片110、120和130之间。例如,每个粘合层140可以包括包含绝缘材料的聚合物带。粘合层140可以设置在凸块109、119和129之间以基本上防止凸块109、119和129的短路。第一凸块119和聚合物粘合层140可以附着于第二半导体芯片120的底表面120a,第二半导体芯片120的底表面120a可以通过面向下安装技术而面对半导体基板100的顶表面100b。第二半导体芯片120可以利用第一凸块109和第二凸块119安装在第一半导体芯片110上。粘合层140也可以提供在第二半导体芯片120和第三半导体芯片130之间以基本上防止第三凸块129之间的电短路。
在一些实施方式中,下填充层(未示出)可以形成在半导体芯片110、120和130之间。在该情形下,下填充层(未示出)可以覆盖第二半导体芯片120的侧壁并可以填充第一凸块109、第二凸块119和第三凸块129之间的空间。形成下填充层(未示出)的工艺可以在第二半导体芯片120的安装工艺和第三半导体芯片130的安装工艺的每个期间进行,或可以在第二半导体芯片120和第三半导体芯片130的安装工艺完成之后进行。
参照图1C,模层200可以形成在半导体基板100的顶表面100b上以覆盖第二半导体芯片120和第三半导体芯片130。模层200可以包括绝缘聚合物材料(例如,环氧树脂模制化合物)。可以在模层200的顶表面上进行研磨工艺或其它适合的平坦化工艺。在图1C中,虚线示出在进行研磨工艺之前模层200的顶表面。模层200的一部分可以通过例如研磨工艺去除以暴露第三半导体芯片130的顶表面。第三半导体芯片130也可以被研磨以调整第三半导体芯片130的厚度。可选地,第三半导体芯片130可以不被研磨。
参照图1D,粘合剂膜300可以粘合到模层200。具有粘合剂膜300的所得结构可以被翻转,因此半导体基板100可以设置在粘合剂膜300上方。半导体基板100的顶表面100b可以面对粘合剂膜300。在以下切片工艺的描述中,术语“顶表面”和“底表面”将如参照图1A至1C所描述地使用,而与上下方向无关。
参照图1E,可以去除载体基板105和载体粘合层106。可以在半导体基板100的底表面100a上朝向模层200进行第一切片工艺以形成第一凹槽G1。第一切片工艺可以利用第一刀片410进行以产生导致第一侧壁Gc的切口(即第一凹槽G1),第一侧壁Gc相对于半导体基板100的底表面100a以角度θ1倾斜。第一刀片410可以是具有倾斜面的斜面刀并可以具有基本上V形的截面。因此,第一凹槽G1可以具有从半导体基板100的底表面100a倾斜的第一侧壁Gc。第一半导体芯片110和模层200可以沿着第一侧壁Gc暴露。半导体基板100的底表面100a与第一侧壁Gc之间的角度θ1可以是钝角。半导体基板100可以通过第一凹槽G1而划分成一个或多个第一半导体芯片110。第一凹槽G1在半导体基板100的底表面100a处的宽度W1可以大于第一凹槽G1在半导体基板100的顶表面100b处的宽度W2。
参照图1F,可以在通过第一凹槽G1暴露的模层200上进行第二切片工艺以在每对在水平方向上相邻的第二半导体芯片120之间形成第二凹槽G2。第二切片工艺可以利用其截面具有基本上矩形形状的第二刀片420进行。第二切片工艺可以在基本上垂直于半导体基板100的顶表面100a的方向上进行,因而,第二凹槽G2可以具有与半导体基板100的底表面100a基本上垂直的第二侧壁Gd。因为第二切片工艺没有在半导体基板100上进行,所以第二侧壁Gd可以与半导体基板100间隔开。第二凹槽G2可以形成在模层200中从而连接到第一凹槽G1。第二凹槽G2可以进一步延伸到粘合剂膜300的一部分中。第二侧壁Gd可以从第一侧壁Gc延伸。第一侧壁Gc与第二侧壁Gd之间的角度θ2可以是钝角。例如,第一侧壁Gc和第二侧壁Gd之间的角度θ2可以在约135度至约150度的范围内,但是不限于此。边缘Ge可以形成在模层200中第一侧壁Gc与第二侧壁Gd相接的位置处。形成在模层200中的第二凹槽G2的宽度W3可以小于半导体基板100中的第一凹槽G1的最小宽度。换言之,通过第二切片工艺形成在模层200中的第二凹槽G2的宽度W3可以小于在半导体基板100中的第一凹槽G1的最小宽度。例如,形成在模层200中的第二凹槽G2的宽度W3可以小于第一凹槽G1在半导体基板100的顶表面100b处的宽度W2。在本实施方式中,第二凹槽G2可以与半导体基板100间隔开。换言之,第一凹槽G1可以包括形成在半导体基板100中的第一区域以及形成在模层200的一部分中的第二区域,第一凹槽G1的第二区域可以插置在第二凹槽G2与第一凹槽G1的第一区域之间。在一些实施方式中,形成在半导体基板100中的第一凹槽G1的最大宽度(例如,宽度W1)可以大于形成在模层200中的第一凹槽G1的最大宽度(例如,宽度W2)。换言之,第一凹槽G1从较大宽度渐缩到较小宽度。
第二凹槽G2可以形成在模层200中在芯片叠层S之间。模层200可以通过第二凹槽G2而划分成一个或多个单元模层210。单元模层210可以分别提供在彼此分离的第一半导体芯片110上。第一半导体芯片110、芯片叠层S以及覆盖第一半导体芯片110和芯片叠层S的单元模层210可以组成封装单元1。在彼此相邻的封装单元1中,第一半导体芯片110之间的最小距离(例如,W2)可以大于分别设置在第一半导体芯片110上的单元模层210之间的最小距离(例如,W3)。随后,粘合剂膜300可以被去除以完成封装单元1的制造。封装单元1可以对应于根据本发明构思的一些实施方式的半导体封装。
图1G是在诸如切片工艺的分离工艺之后封装单元的放大截面图。在下文将描述实施方式的切片工艺。
参照图1F和1G,如果封装单元1通过第一和第二凹槽G1和G2而彼此分离,则粘合剂膜300会收缩。结果,粘合剂膜300的形状会改变。进而,封装单元1会彼此接触,导致对第一半导体芯片110的损坏。根据本发明构思的一些实施方式,因为边缘Ge可以形成在模层200中,所以第一半导体芯片110可以不彼此接触。例如,形成在半导体基板100中的第一凹槽G1的最大宽度W1可以大于形成在模层200中的凹槽G2的最小宽度(例如,宽度W3),如图1F所示。因而,单元模层210会通过粘合剂膜300的变形而彼此接触,如图1G所示。
第一半导体芯片110的物理强度会弱于模层200/单元模层210的物理强度。例如,第一半导体芯片110的含硅材料的机械和物理强度可以弱于聚合物(例如,环氧树脂模制化合物)的机械和物理强度。如果在第一半导体芯片110的底表面110a上没有形成额外的聚合物层,则硅氮化物层113会被暴露。彼此分离的第一半导体芯片110的侧壁110c会没有被单元模层210覆盖。对第一半导体芯片110的损伤会使半导体封装的可靠性劣化。根据本发明构思的一些实施方式,如果粘合剂膜300变形,则单元模层210可以彼此接触。换言之,即使当封装单元1彼此接触时,第一半导体芯片110也不彼此接触。因此,能够基本上防止或减少对第一半导体芯片110的损坏。因此,能够改善半导体封装的可靠性。第二刀片420可以在第二切片工艺期间与第一半导体芯片110间隔开,因此由第二刀片420引起的裂纹不会形成在第一半导体芯片110上。此外,在切片工艺期间暴露第一半导体芯片110的时间可以减短以更有效地防止对第一半导体芯片110的损坏。
在下文将描述根据一些实施方式制造的封装单元(即,半导体封装)。
图1H是示出根据本发明构思的一些实施方式制造的封装单元中的一个的截面图,图1I是图1H的第一半导体芯片和模层的放大图。在下文,为了说明的容易和方便,与以上提及的相同描述将被省略或被简要地描述。
参照图1H和1I,封装单元1可以包括顺序层叠的第一半导体芯片110、第二半导体芯片120和第三半导体芯片130。第一至第三半导体芯片110、120和130可以分别与参照图1A至1F描述的半导体芯片110、120和130基本上相同或类似。在一些实施方式中,可以提供多个第二半导体芯片120。第三半导体芯片130可以被省略。第一半导体芯片110可以具有底表面110a、顶表面110b以及连接在底表面110a的边缘和顶表面110b的边缘之间的侧壁110c。单元模层210可以沿着侧壁110c暴露并可以相对于底表面110a倾斜。例如,底表面110a和侧壁110c之间的角度θ1可以是钝角。由于第一半导体芯片110具有倾斜的侧壁110c,所以其可以不被外部冲击容易地损坏。第一半导体芯片110的宽度可以从底表面110a朝向顶表面110b逐渐变大。换言之,第一半导体芯片110的底表面110a的宽度W4可以小于第一半导体芯片110的顶表面110b的宽度W5。
单元模层210可以具有倾斜侧壁210c和竖直侧壁210d。倾斜侧壁210c可以与第一半导体芯片110的相应侧壁110c基本上共平面,并因此可以以与相应侧壁110c基本上相同的角度倾斜。倾斜角θ1可以相对于底表面110a为钝角。每个倾斜侧壁210c可以提供在第一半导体芯片110的底表面110a与每个竖直侧壁210d之间。竖直侧壁210d可以基本上垂直于第一半导体芯片110的底表面110a。竖直侧壁210d可以与第一和第二半导体芯片110和120间隔开。倾斜侧壁210c和竖直侧壁210d之间的角度θ2可以是钝角。边缘可以形成在在单元模层210上在倾斜侧壁210c与竖直侧壁210d相接的位置处。单元模层210的宽度W6可以大于第一半导体芯片110的最大宽度(例如,顶表面110b的宽度W5)。参照图1F描述的第一凹槽G1的第一侧壁Gc可以对应于第一半导体芯片110的侧壁110c和单元模层210的倾斜侧壁210c。参照图1F描述的第二凹槽G2的第二侧壁Gd可以对应于单元模层210的竖直侧壁210d。第三半导体芯片130的顶表面可以在一对单元模层210之间暴露。
图2A和2B是示出根据本发明构思的另一些实施方式的制造半导体封装的方法的截面图,图2C是示出在诸如切片工艺的分离工艺之后封装单元的示例的截面图。与以上实施方式中描述的相同说明将被省略或被简要地提及以避免重复。换言之,在下文将主要描述本实施方式与以上实施方式之间的差异。
参照图2A,可以在半导体基板100的底表面100a上进行第一切片工艺。例如,可以在半导体基板100的顶表面100b上形成第二半导体芯片120、第三半导体芯片130和模层200,如参照图1A至1C描述的。如参照图1D描述的,粘合剂膜300可以粘合到模层200,因此半导体基板100的顶表面100b(或有源表面)可以面对粘合剂膜300。
可以在半导体基板100的底表面100a上朝向模层200进行第一切片工艺,从而在每对相邻的第一半导体芯片110之间形成第一凹槽G1。第一凹槽G1可以具有相对于半导体基板100的底表面100a倾斜的第一侧壁Gc。半导体基板100的底表面100a与第一侧壁Gc之间的角度θ1可以是钝角。半导体基板100和模层200可以沿着第一侧壁Gc暴露。第一凹槽G1在半导体基板100的底表面100a处的宽度W1可以大于第一凹槽G1在半导体基板100的顶表面100b处的宽度W2。半导体基板100可以通过第一凹槽G1划分成多个第一半导体芯片110。
参照图2B,可以在通过第一凹槽G1暴露的模层200上进行第二切片工艺以形成第二凹槽G2。第二切片工艺可以在基本上垂直于半导体基板100的底表面100a的方向上进行。因而,第二凹槽G2可以具有基本上垂直于半导体基板100的底表面100a的第二侧壁Gd。第二切片工艺可以与半导体基板100相邻地进行。然而,可以不在半导体基板100上进行第二切片工艺。因此,可以减少在切片工艺期间第一半导体芯片110被暴露的时间。此外,第一半导体芯片110可以不被第二刀片420物理地损坏。例如,不会在第一半导体芯片110中引起裂纹。
第二凹槽G2可以形成在第一凹槽G1中,因此第一侧壁Gc的一部分可以被去除。在形成第二凹槽G2之后,第一半导体芯片110可以沿着侧壁Gc被暴露,但是可以不通过模层200暴露。模层200可以沿着第二凹槽G2暴露,该第二凹槽G2可以连接到第一凹槽G1。第二侧壁Gd可以从第一侧壁Gc延伸。第一侧壁Gc与第二侧壁Gd之间的角度θ2可以是钝角。在本实施方式中,边缘Ge可以形成在模层200与第一半导体芯片110之间的界面处。
形成在模层200中的凹槽G2的宽度W3可以小于凹槽G1在半导体基板100的底表面100a处的宽度W1,并可以基本上等于凹槽G1在半导体基板100的顶表面100b处的宽度W2。
第二凹槽G2可以形成在模层200中在芯片叠层S之间。模层200可以通过第二凹槽G2而划分成一个或多个单元模层210。单元模层210可以分别提供在第一半导体芯片110上。通过第二凹槽G2,封装单元2可以彼此分离。每个封装单元2可以包括第一半导体芯片110、设置在第一半导体芯片110上的芯片叠层S、以及覆盖第一半导体芯片110和芯片叠层S的单元模层210。封装单元2对应于根据本实施方式的半导体封装。在彼此相邻的封装单元2中,第一半导体芯片110之间的最小距离可以基本上等于或大于分别设置在第一半导体芯片110上的单元模层210之间的最小距离。
参照图2C和2B,如果封装单元2通过第一和第二凹槽G1和G2而彼此分离,则粘合剂膜300会收缩。如图2B所示,形成在模层200中的第二凹槽G2的最大宽度W3可以基本上等于形成在半导体基板100中的第一凹槽G1的最小宽度(例如,在顶表面100b处的宽度W2)。即使粘合剂膜300变形,相邻的封装单元2的单元模层210也可以彼此接触。在另一些实施方式中,相邻的封装单元2中的一个封装单元的单元模层210可以与相邻的封装单元2中的另一个封装单元的第一半导体芯片110接触。根据本实施方式,第一半导体芯片110会很难彼此接触。因而,可以改善半导体封装的可靠性。
在下文将描述根据本实施方式的封装单元2。
图2D是示出根据本发明构思的另一些实施方式制造的封装单元中的一个的截面图,图2E是图2D的第一半导体封装和模层的放大图。与以上描述的相同说明将被省略或简要地提及以避免重复。
参照图2D和2E,封装单元2可以包括顺序层叠的第一半导体芯片110、第二半导体芯片120和第三半导体芯片130。第一至第三半导体芯片110、120和130可以分别与以上描述的半导体芯片110、120和130相同或类似。第一半导体芯片110的侧壁110c可以连接在底表面110a的边缘与顶表面110b的边缘之间并可以倾斜。底表面110a与侧壁110c之间的角度θ1可以是钝角。第一半导体芯片110的宽度可以从底表面110a朝向顶表面110b逐渐变大。例如,第一半导体芯片110的底表面110a的宽度W4可以小于第一半导体芯片110的顶表面110b的宽度W5。与其中底表面与侧壁之间的角度是直角的半导体芯片相比,根据本实施方式的第一半导体芯片110可以不被外部冲击损坏。
单元模层210可以具有竖直侧壁210d。竖直侧壁210d可以基本上垂直于第一半导体芯片110的底表面110a。单元模层210的竖直侧壁210d与第一半导体芯片110的侧壁110c之间的角度θ2可以是钝角。边缘可以形成在第一半导体芯片110与单元模层210之间的界面处。单元模层210的外侧壁之间的宽度W6可以基本上等于第一半导体芯片110的顶表面110b的宽度W5,并可以大于第一半导体芯片110的底表面110a的宽度W4。第一半导体芯片110的侧壁110c可以对应于参照图2A和2B描述的第一侧壁Gc,单元模层210的竖直侧壁210d可以对应于参照图2B描述的第二侧壁Gd。
图3A和3B是示出根据本发明构思的另一些实施方式的制造半导体封装的方法的截面图。图3C是示出在诸如切片工艺的分离工艺之后封装单元的示例的截面图。与以上实施方式中的描述的相同说明将被省略或被简要地提及以避免重复。换言之,在下文将主要描述本实施方式与以上实施方式之间的差异。
参照图3A,可以在半导体基板100的底表面100a上进行第一切片工艺。例如,第二半导体芯片120、第三半导体芯片130和模层200可以提供在半导体基板100的顶表面100b上,如参照图1A至1C所述的。如参照图1D所述的,粘合剂膜300可以粘合到模层200,因此半导体基板100的顶表面(或有源表面)100b可以面对粘合剂膜300。
可以在半导体基板100的底表面100a上朝向模层200进行第一切片工艺,从而在每对相邻的第一半导体芯片110之间形成第一凹槽G1。第一凹槽G1可以具有相对于半导体基板100的底表面100a倾斜的第一侧壁Gc。半导体基板100的底表面100a与第一侧壁Gc之间的角度θ1可以是钝角。半导体基板100以及模层200的部分可以沿着第一侧壁Gc暴露。在另一些实施方式中,半导体基板100可以沿着第一侧壁Gc暴露,而模层200没有沿着第一侧壁Gc暴露。
参照图3B,可以在第一凹槽G1中进行第二切片工艺以形成第二凹槽G2。第二切片工艺可以在垂直于半导体基板100的底表面100a的方向上进行。因此,第二凹槽G2可以具有在基本上垂直于半导体基板100的底表面100a的方向上延伸的第二侧壁Gd。在第二切片工艺中使用的第二刀片420可以切割通过第一凹槽G1暴露的半导体基板100和模层200。第一侧壁Gc的部分可以在形成第二凹槽G2时被去除。在形成第二凹槽G2之后,第一半导体芯片110可以沿着第一侧壁Gc暴露,但是可以不通过模层200暴露。第二凹槽G2可以连接到第一凹槽G1或与第一凹槽G1连通,并且第二侧壁Gd可以分别从第一侧壁Gc延伸。半导体基板100和模层200可以沿着第二侧壁Gd暴露。第一侧壁Gc和第二侧壁Gd之间的角度θ2可以是钝角。在本实施方式中,边缘Ge可以形成在第一半导体芯片110的侧壁上在第一侧壁Gc与第二侧壁Gd相接的位置处。形成在模层200中的第二凹槽G2的宽度W3可以小于第一凹槽G1在半导体基板100的底表面100a处的宽度W1,并可以基本上等于第一凹槽G1在半导体基板100的顶表面100b处的宽度W2。
通过第一凹槽G1和第二凹槽G2,半导体基板100可以被划分成一个或多个第一半导体芯片110并且模层200可以被划分成一个或多个单元模层210。因此,可以制造封装单元3。封装单元3对应于根据本实施方式的半导体封装。在彼此相邻的封装单元3中,第一半导体芯片110之间的最小距离可以等于或大于分别设置在第一半导体芯片110上的单元模层210之间的距离。
在下文将更详细地描述本实施方式的切片工艺。
参照图3C和3B,粘合剂膜300的形状可能改变,因此封装单元3会彼此接触。根据本实施方式,具有钝角的边缘Ge可以形成在第一和第二凹槽G1和G2中。因此,第一半导体芯片110可以承受外部冲击。此外,第一半导体芯片110之间接触的可能性可以减小。例如,封装单元3中的一个封装单元的单元模层210可以接触相邻的封装单元3的第一半导体芯片110。结果,可以改善封装单元(即半导体封装)的可靠性。
在下文将描述根据本实施方式制造的封装单元。
图3D是示出根据本发明构思的另一些实施方式制造的封装单元之一的截面图,图3E是图3D的第一半导体封装和模层的放大图。与以上描述的相同说明将被省略或被简要地提及以避免重复。
参照图3D和3E,封装单元3可以包括顺序层叠的第一半导体芯片110、第二半导体芯片120和第三半导体芯片130。第一至第三半导体芯片110、120和130可以分别与以上描述的半导体芯片110、120和130相同或类似。第一半导体芯片110可以具有提供在底表面110a和顶表面110b之间的第一侧壁110c和第二侧壁110d。第一侧壁110c可以邻近于底表面110a。底表面110a和第一侧壁110c之间的角度θ1可以是钝角。因此,与其中底表面与侧壁之间的角度是直角的半导体芯片相比,本实施方式的第一半导体芯片110可以承受外部冲击。第二侧壁110d可以基本上垂直于底表面110a。第二侧壁110d可以邻近于顶表面110b并可以连接在顶表面110b与第一侧壁110c之间。第一侧壁110c和第二侧壁110d之间的角度θ2可以是钝角。边缘Ge可以形成在第一半导体芯片110的侧壁上在第一侧壁110c与第二侧壁110d相接的位置处。第一半导体芯片110的宽度可以从底表面110a到边缘Ge逐渐变大,并可以从边缘Ge到顶表面110b是均一的。第一半导体芯片110的底表面110a的宽度W4可以小于第一半导体芯片110的顶表面110b的宽度W5。第一侧壁110c和第二侧壁110d可以被单元模层210暴露。
单元模层210可以具有竖直侧壁210d。竖直侧壁210d可以基本上垂直于第一半导体芯片110的底表面110a。竖直侧壁210d可以从第一半导体芯片110的第二侧壁110d延伸并可以与第二侧壁110d基本上共平面。单元模层210的宽度W6可以基本上等于第一半导体芯片110的顶表面110b的宽度W5,并可以大于第一半导体芯片110的底表面110a的宽度W4。第一半导体芯片110的第一侧壁110c可以对应于参照图3B描述的第一凹槽G1的第一侧壁Gc。第一半导体芯片110的第二侧壁110d和单元模层210的竖直侧壁210d可以对应于参照图3B描述的第二凹槽G2的第二侧壁Gd。
在以上描述的实施方式中,第二凹槽G2在第一凹槽G1之后形成。然而,虽然没有示出,但是取决于根据本发明构思的一些其它实施方式的应用,第一凹槽G1可以在第二凹槽G2之后形成。此外,以下也是可以的,在本发明构思的精神和范围内,第一凹槽G1和第二凹槽G2可以利用合适的刀片(例如,兼备基本上矩形截面和基本上V形截面的刀片)在相同的工艺中形成。
应用
图4是示出包括根据本发明构思的实施方式的半导体封装的封装模块的示例的图示。图5是示出包括根据本发明构思的实施方式的半导体封装的电子系统的示例的示意性方框图。图6是示出包括根据本发明构思的实施方式的半导体封装的存储卡的示例的示意性方框图。
参照图4,封装模块1200可以包括利用四方扁平封装(QFP)技术封装的一个或多个第一半导体器件1220以及第二半导体器件1230。半导体器件1220和1230可以包括根据本发明构思的实施方式的半导体封装1至3中的至少一个。封装模块1200可以通过提供在板1210的一侧上的外部连接端子1240连接到外部电子设备。
参照图5,电子系统1300可以包括控制器1310、输入/输出器件(I/O)1320以及存储器器件1330。控制器1310、I/O器件1320和存储器器件1330可以通过数据总线1350彼此通信。数据总线1350可以对应于电信号通过其传输的路径。例如,控制器1310可以包含微处理器、数字信号处理器、微控制器以及具有与其中任一个类似的功能的其它逻辑器件中的至少一种。控制器1310和存储器器件1330中的至少一个可以包括根据本发明构思的前述实施方式的半导体封装1至3中的至少一个。I/O器件1320可以包括键区、键盘和显示单元中的至少一个。存储器器件1330可以是存储数据的器件。存储器器件1330可以存储数据和/或由控制器1310执行的命令。存储器器件1330可以包括易失性存储器器件和非易失性存储器器件中的至少一个。在一些实施方式中,存储器器件1330可以包括快闪存储器器件。例如,应用有本发明构思的技术的快闪存储器器件可以被安装在信息处理系统诸如移动装置或台式计算机中。快闪存储器器件可以被实现为固态盘(SSD)。在此情形下,电子系统1300可以在存储器器件1330中稳定地存储大量数据。电子系统1300还可以包括将电数据传送到通信网络或从通信网络接收电数据的接口单元1340。接口单元1340可以通过无线或电缆操作。例如,接口单元1340可以包括天线或无线/电缆收发器。虽然在附图中没有示出,但是电子系统1300还可以包括应用芯片组和/或照相机图像处理器(CIS)。
电子系统1300可以被实现为可移动系统、个人计算机、工业计算机或多功能逻辑系统。例如,可移动系统可以是个人数字助理(PDA)、便携式计算机、网络本、无线电话、移动式电话、膝上型计算机、数字音乐播放器、存储卡和信息发送/接收系统中的一个。如果电子系统1300是能够进行无线通信的装置,则电子设备1300可以被用于通信接口协议诸如第三代通信系统(例如,CDMA、GSM、NADC、E-TDMA、WCDMA、CDMA2000)中。
参照图6,存储卡1400可以包括非易失性存储器器件1410和存储器控制器1420。非易失性存储器器件1410和存储器控制器1420可以存储数据或可以读取所存储的数据。存储器器件1410和存储器控制器1420中的至少一个可以包括根据本发明构思的前述实施方式的半导体封装1至3中的至少一个。存储器控制器1420可以响应主机1430的读/写请求而从非易失性存储器器件1410读取数据/将数据存储到非易失性存储器器件1410中。
根据本发明构思的实施方式,凹槽可以通过切片工艺形成并可以具有成钝角的边缘。第一半导体芯片可以通过凹槽而彼此分离。此外,单元模层也可以通过凹槽而彼此分离。当单元模层彼此分离时,粘合剂膜可能变形。在此情形下,封装单元(即,半导体封装)会彼此接触。因为凹槽的边缘具有钝角,所以在彼此相邻的封装单元中,第一半导体芯片之间的距离可以等于或大于分别设置在第一半导体芯片上的单元模层之间的距离。因此,可以减小第一半导体芯片之间接触的可能性并可以防止第一半导体芯片在切片工艺期间被损坏。
第一半导体芯片的底表面可以与第一半导体芯片的侧壁成钝角。因此,可以防止第一半导体芯片被外部冲击损坏从而改善半导体封装的可靠性。
虽然已经参照示例实施方式描述了本发明构思,但是对于本领域技术人员来说显然的是,可以进行各种改变和变形而没有脱离本发明构思的精神和范围。因此,应当理解,以上实施方式不是限制性的,而是说明性的。因此,本发明构思的范围将由权利要求书及其等同物的最宽可允许解释来确定,而不应受以上描述约束或限制。
本申请要求享有2014年7月11日在韩国知识产权局提交的韩国专利申请No.10-2014-0087676的优先权,其公开内容通过引用整体结合于此。
Claims (25)
1.一种制造半导体封装的方法,所述方法包括:
提供具有顶表面的半导体基板,多个芯片叠层安装在该顶表面上,每个所述芯片叠层包括多个层叠的半导体芯片;
在所述半导体基板的所述顶表面上形成覆盖所述芯片叠层的模层;以及
通过在所述半导体基板的底表面上进行切片工艺,形成穿透所述半导体基板和所述模层的凹槽,
其中所述凹槽包括:
第一侧壁,与所述半导体基板的所述顶表面相邻并在相对于所述半导体基板的所述底表面倾斜的方向上延伸;
第二侧壁,连接到所述第一侧壁并在基本上垂直于所述半导体基板的所述底表面的方向上延伸;以及
边缘,形成在所述第一侧壁与所述第二侧壁相接的位置处,
其中所述边缘形成在所述模层中。
2.根据权利要求1所述的方法,其中形成在所述半导体基板中的所述凹槽的最大宽度大于形成在所述模层中的所述凹槽的最大宽度。
3.根据权利要求1所述的方法,其中形成所述凹槽包括:
从所述半导体基板的所述底表面朝向所述模层切割所述半导体基板以形成具有所述第一侧壁的第一凹槽,所述模层沿着所述第一凹槽的第一侧壁被暴露;以及
切割通过所述第一凹槽暴露的所述模层以形成具有所述第二侧壁的第二凹槽。
4.根据权利要求1所述的方法,其中所述第一侧壁与所述半导体基板的所述底表面成钝角。
5.根据权利要求1所述的方法,其中所述半导体基板包括多个基底半导体芯片,每个基底半导体芯片具有从其穿过的穿孔,以及
其中每个所述芯片叠层电连接到相应的基底半导体芯片。
6.根据权利要求5所述的方法,其中所述半导体基板通过所述凹槽而被划分成所述基底半导体芯片,所述模层通过所述凹槽而被划分成单元模层,并且
其中,一对相邻的基底半导体芯片之间的距离大于一对相邻的单元模层之间的距离。
7.根据权利要求1所述的方法,其中所述芯片叠层的所述半导体芯片的有源表面面对所述半导体基板。
8.根据权利要求1所述的方法,其中所述凹槽穿过设置在一对相邻的芯片叠层之间的所述模层。
9.根据权利要求1所述的方法,其中所述半导体基板包括:覆盖所述底表面的钝化层;以及形成在所述底表面上的外部端子,并且
其中所述钝化层被暴露。
10.一种制造半导体封装的方法,所述方法包括:
制备包括多个第一半导体芯片的半导体基板;
在所述半导体基板的顶表面上安装第二半导体芯片;
在所述半导体基板的所述顶表面上形成覆盖所述第二半导体芯片的模层;以及
形成穿透所述半导体基板和所述模层的凹槽以使所述第一半导体芯片彼此分离,
其中形成所述凹槽包括:
在所述半导体基板的底表面上进行第一切片工艺以在相对于所述半导体基板的所述底表面倾斜的方向上切割所述半导体基板以及所述模层的一部分;以及
进行第二切片工艺以在基本上垂直于所述半导体基板的所述底表面的方向上切割所述模层,
其中通过所述第一切片工艺形成在所述半导体基板中的所述凹槽的最小宽度大于通过所述第二切片工艺形成在所述模层中的所述凹槽的宽度。
11.根据权利要求10所述的方法,其中进行所述第二切片工艺而与所述半导体基板间隔开。
12.根据权利要求10所述的方法,其中通过所述第一切片工艺形成的所述凹槽具有倾斜侧壁,并且
其中所述半导体基板和所述模层沿着所述倾斜侧壁暴露。
13.根据权利要求10所述的方法,其中所述第一半导体芯片包括:
第一集成电路层;
钝化层,覆盖所述第一集成电路层;
第一穿孔,穿过所述第一半导体芯片并连接到所述第一集成电路层;以及
外部端子,电连接到所述第一集成电路层,
其中所述钝化层被暴露。
14.根据权利要求10所述的方法,还包括:
在所述第二半导体芯片上安装第三半导体芯片,
其中每个所述第二半导体芯片具有穿透相应的第二半导体芯片的穿孔。
15.根据权利要求10所述的方法,其中所述半导体基板通过所述第一切片工艺而被划分成所述第一半导体芯片,
其中所述模层通过所述第二切片工艺而被划分成单元模层,并且
一对相邻的第一半导体芯片之间的最小距离大于分别设置在彼此相邻的所述第一半导体芯片上的一对相邻的单元模层之间的最小距离。
16.一种半导体封装,包括:
第一半导体芯片,具有底表面、与所述底表面相反的顶表面以及在所述顶表面与所述底表面之间延伸的侧壁;
第二半导体芯片,安装在所述第一半导体芯片的所述顶表面上;以及
模层,提供在所述第一半导体芯片的所述顶表面上并覆盖所述第二半导体芯片的侧壁,
其中所述第一半导体芯片的所述侧壁与所述第一半导体芯片的所述底表面成钝角,并且
其中所述模层包括:
倾斜侧壁,与所述第一半导体芯片的所述侧壁基本上共平面;
竖直侧壁,在基本上垂直于所述第一半导体芯片的所述底表面的方向上从所述倾斜侧壁延伸;以及
边缘,形成在所述倾斜侧壁与所述竖直侧壁相接的位置处。
17.根据权利要求16所述的半导体封装,其中在封装中的所述模层的外侧壁之间的最大宽度大于所述第一半导体芯片的最大宽度。
18.根据权利要求16所述的半导体封装,其中所述第一半导体芯片具有穿过所述第一半导体芯片的第一穿孔,
其中所述第一半导体芯片的所述底表面是有源表面,并且
其中所述第二半导体芯片的有源表面面对所述第一半导体芯片。
19.根据权利要求16所述的半导体封装,其中所述第一半导体芯片的宽度从所述第一半导体芯片的所述底表面朝向所述顶表面逐渐变大。
20.根据权利要求16所述的半导体封装,还包括:
第三半导体芯片,安装在所述第二半导体芯片上,
其中所述第二半导体芯片具有穿过所述第二半导体芯片的穿孔。
21.根据权利要求20所述的半导体封装,其中所述第三半导体芯片的顶表面通过所述模层暴露。
22.一种制造半导体封装的方法,所述方法包括:
提供具有顶表面的半导体基板,多个芯片叠层安装在该顶表面上,每个所述芯片叠层包括多个层叠的半导体芯片;
在所述半导体基板的所述顶表面上形成覆盖所述芯片叠层的模层;
形成穿过所述半导体基板的第一凹槽,所述第一凹槽具有相对于所述半导体基板的底表面倾斜的第一侧壁;以及
形成穿透所述模层且在基本上垂直于所述半导体基板的所述底表面的方向上延伸的第二凹槽,以形成彼此分离的封装单元,
其中所述第二凹槽包括连接到所述第一侧壁的第二侧壁,所述第二凹槽通过所述第一凹槽暴露。
23.根据权利要求22所述的方法,其中边缘形成在所述第一侧壁与所述第二侧壁相接的位置处,其中所述边缘形成在所述模层中。
24.根据权利要求22所述的方法,其中边缘形成在所述第一侧壁与所述第二侧壁相接的位置处,其中所述边缘形成在所述半导体芯片的侧壁上。
25.根据权利要求22所述的方法,其中形成所述第一凹槽包括利用具有基本上V形截面的刀片在所述半导体基板的所述底表面上朝向所述模层进行切片工艺以形成所述第一凹槽,其中形成所述第二凹槽包括利用具有基本上矩形截面的第二刀片在通过所述第一凹槽暴露的所述模层上进行另一切片工艺。
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KR102171286B1 (ko) | 2020-10-29 |
KR20160008053A (ko) | 2016-01-21 |
US20160013174A1 (en) | 2016-01-14 |
US9905550B2 (en) | 2018-02-27 |
CN105261570B (zh) | 2019-04-02 |
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