JP4390775B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
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- JP4390775B2 JP4390775B2 JP2006030407A JP2006030407A JP4390775B2 JP 4390775 B2 JP4390775 B2 JP 4390775B2 JP 2006030407 A JP2006030407 A JP 2006030407A JP 2006030407 A JP2006030407 A JP 2006030407A JP 4390775 B2 JP4390775 B2 JP 4390775B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 128
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 239000011347 resin Substances 0.000 claims abstract description 33
- 230000003014 reinforcing effect Effects 0.000 claims description 16
- 239000011521 glass Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims 5
- 238000000034 method Methods 0.000 abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 37
- 229910052710 silicon Inorganic materials 0.000 description 37
- 239000010703 silicon Substances 0.000 description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 239000000463 material Substances 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 7
- 229910007637 SnAg Inorganic materials 0.000 description 5
- 238000000465 moulding Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 229910007116 SnPb Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
前記薄化された半導体ウエハの前記第1面上に前記複数の半導体チップを積層することができる。更に、前記複数の半導体チップを前記半導体ウエハ上に積層する前に、前記第1面上に再配線層を形成することができる。
112 Siウエハ
114 貫通電極
118,217 再配線
120 チップ積層体
124,224 モールド樹脂
215,330 接着剤
232,332 ガラス板
W Siウエハ
Claims (4)
- 第1面及び前記第1面と反対側の第2面とを有するインターポーザ用の半導体ウエハを準備する工程と;
前記半導体ウエハの前記第2面側に露出部分を有する貫通電極を形成する工程と;
補強用基材を準備する工程と;
前記補強用基材を前記半導体ウエハの前記第2面側に接着させる工程と;
前記半導体ウエハの前記第1面を切削し、前記貫通電極を露出させる工程と;
前記半導体ウエハの前記第1面上に、前記貫通電極と電気的に接続される積層された複数の半導体チップを搭載する工程と;
前記半導体ウエハの前記第1面上に、前記複数の半導体チップを覆うように封止樹脂を形成する工程と;
前記補強用基材を前記半導体ウエハから除去する工程と;
前記半導体ウエハの前記第2面上に、前記貫通電極と電気的接続される外部端子を形成する工程と;
前記封止樹脂及び前記半導体ウエハを前記半導体チップの周辺にて切断する工程とを有することを特徴とする半導体パッケージの製造方法。 - 第1面及び前記第1面と反対側の第2面とを有するインターポーザ用の半導体ウエハを準備する工程と;
前記半導体ウエハの前記第2面側に露出部分を有する貫通電極を形成する工程と;
前記半導体ウエハの前記第2面上に、前記貫通電極と電気的接続される外部端子を形成する工程と;
補強用基材を準備する工程と;
前記補強用基材を前記半導体ウエハの前記第2面側に接着させる工程と;
前記半導体ウエハの前記第1面を切削し、前記貫通電極を露出させる工程と;
前記半導体ウエハの前記第1面上に、前記貫通電極と電気的に接続される積層された複数の半導体チップを搭載する工程と;
前記半導体ウエハの前記第1面上に、前記複数の半導体チップを覆うように封止樹脂を形成する工程と;
前記補強用基材を前記半導体ウエハから除去する工程と;
前記封止樹脂及び前記半導体ウエハを前記半導体チップの周辺にて切断する工程とを有することを特徴とする半導体パッケージの製造方法。 - 前記封止樹脂を形成する工程は、前記ウエハ上で一括して行われることを特徴とする請求項1又は2に記載の半導体パッケージの製造方法。
- 前記補強用基材は、ガラス板であることを特徴とする請求項1乃至3のいずれかに記載の半導体パッケージの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006030407A JP4390775B2 (ja) | 2006-02-08 | 2006-02-08 | 半導体パッケージの製造方法 |
US11/593,039 US7413925B2 (en) | 2006-02-08 | 2006-11-06 | Method for fabricating semiconductor package |
CN2006101604589A CN101017786B (zh) | 2006-02-08 | 2006-11-24 | 半导体封装的制造方法 |
KR1020060117686A KR101347633B1 (ko) | 2006-02-08 | 2006-11-27 | 반도체 패키지의 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006030407A JP4390775B2 (ja) | 2006-02-08 | 2006-02-08 | 半導体パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007214220A JP2007214220A (ja) | 2007-08-23 |
JP4390775B2 true JP4390775B2 (ja) | 2009-12-24 |
Family
ID=38334576
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006030407A Active JP4390775B2 (ja) | 2006-02-08 | 2006-02-08 | 半導体パッケージの製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7413925B2 (ja) |
JP (1) | JP4390775B2 (ja) |
KR (1) | KR101347633B1 (ja) |
CN (1) | CN101017786B (ja) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7968379B2 (en) * | 2006-03-09 | 2011-06-28 | SemiLEDs Optoelectronics Co., Ltd. | Method of separating semiconductor dies |
US7452739B2 (en) * | 2006-03-09 | 2008-11-18 | Semi-Photonics Co., Ltd. | Method of separating semiconductor dies |
JP2009071095A (ja) * | 2007-09-14 | 2009-04-02 | Spansion Llc | 半導体装置の製造方法 |
KR101013556B1 (ko) * | 2008-02-01 | 2011-02-14 | 주식회사 하이닉스반도체 | 스택 패키지의 제조방법 |
US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
KR20100058359A (ko) * | 2008-11-24 | 2010-06-03 | 삼성전자주식회사 | 다층 반도체 패키지, 그것을 포함하는 반도체 모듈 및 전자신호 처리 시스템 및 다층 반도체 패키지의 제조 방법 |
US20120032323A1 (en) * | 2009-04-30 | 2012-02-09 | Masahiro Matsumoto | Semiconductor device and method of manufacturing the same |
JP2011061004A (ja) | 2009-09-10 | 2011-03-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8252665B2 (en) | 2009-09-14 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection layer for adhesive material at wafer edge |
TWI419302B (zh) * | 2010-02-11 | 2013-12-11 | Advanced Semiconductor Eng | 封裝製程 |
US20110221053A1 (en) * | 2010-03-11 | 2011-09-15 | Qualcomm Incorporated | Pre-processing to reduce wafer level warpage |
US8298863B2 (en) * | 2010-04-29 | 2012-10-30 | Texas Instruments Incorporated | TCE compensation for package substrates for reduced die warpage assembly |
JP2011243725A (ja) | 2010-05-18 | 2011-12-01 | Elpida Memory Inc | 半導体装置の製造方法 |
KR101692955B1 (ko) | 2010-10-06 | 2017-01-05 | 삼성전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
JP2012109437A (ja) | 2010-11-18 | 2012-06-07 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2012209545A (ja) * | 2011-03-17 | 2012-10-25 | Sekisui Chem Co Ltd | 半導体積層体の製造方法 |
US8937309B2 (en) * | 2011-08-08 | 2015-01-20 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
TWI500123B (zh) * | 2011-08-09 | 2015-09-11 | Soitec Silicon On Insulator | 包含內有一個或多個電性、光學及流體互連之互連層之黏附半導體構造之形成方法及應用此等方法形成之黏附半導體構造 |
KR101332857B1 (ko) * | 2011-12-22 | 2013-11-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US8912045B2 (en) * | 2012-06-12 | 2014-12-16 | International Business Machines Corporation | Three dimensional flip chip system and method |
CN104321866B (zh) * | 2012-09-14 | 2018-03-02 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
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KR101569123B1 (ko) | 2014-03-26 | 2015-11-13 | 앰코 테크놀로지 코리아 주식회사 | 팬인 타입 반도체 패키지 구조 및 제조 방법 |
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JP6437805B2 (ja) * | 2014-12-03 | 2018-12-12 | 東京応化工業株式会社 | 積層体の製造方法、封止基板積層体の製造方法及び積層体 |
JP6421083B2 (ja) | 2015-06-15 | 2018-11-07 | 株式会社東芝 | 半導体装置の製造方法 |
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