CN101017786A - 半导体封装的制造方法 - Google Patents

半导体封装的制造方法 Download PDF

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CN101017786A
CN101017786A CNA2006101604589A CN200610160458A CN101017786A CN 101017786 A CN101017786 A CN 101017786A CN A2006101604589 A CNA2006101604589 A CN A2006101604589A CN 200610160458 A CN200610160458 A CN 200610160458A CN 101017786 A CN101017786 A CN 101017786A
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CN101017786B (zh
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江川良实
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Oki Electric Industry Co Ltd
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Abstract

本发明提供各工序间的操作变得容易、可谋求作业性的提高的半导体封装的制造方法。在与本发明有关的半导体封装的制造方法中，在介入片用的半导体晶片的第1面上层叠上述多个半导体芯片；形成模塑树脂，以覆盖上述半导体芯片的整体；其后，通过切割上述半导体晶片，对分成了各个小片的多个半导体封装进行成形。

Description

半导体封装的制造方法
技术领域
本发明涉及在具有贯通电极的介入片上层叠多个半导体芯片而构成的半导体封装的制造方法。
背景技术
近年来，以高密度安装放置了集成电路的多个半导体芯片、在短的期间内实现高功能的系统的“封装中的系统”(System in Package)技术越来越引人注目。特别是，以三维方式层叠多个半导体芯片、可实现大幅度的小型化的层叠型封装的要求越来越多。作为适应这样的要求的技术，例如，如在特开2005-236245号公报中公开的那样，提出了在半导体芯片的内部形成贯通电极、在被称为介入片的安装用的芯片上层叠了的半导体封装结构。
【专利文献1】特开2005-236245号公报
在制造上述那样的半导体封装结构时，以前准备减薄了的、分成了各个小片的介入片、在该分成了各个小片的介入片上层叠多个半导体芯片(功能芯片)。
但是，如果按照上述的以前的制造方法，则减薄了的、分成了各个小片的介入片的操作(handling)是困难的，难以谋求作业性的提高。其结果，在半导体芯片中容易发生裂纹不良等，有时会使成品率下降。因此，可考虑通过增加介入片的厚度来谋求操作性能的提高，但存在不仅封装整体的厚度增加、而且贯通电极的形成或电极材料填充变得显著地困难这样的不良情况。
发明内容
本发明是鉴于上述这样的状况形成的，其目的在于提供各工序间的操作变得容易、可谋求作业性的提高的半导体封装的制造方法。
为了达到上述目的，在与本发明有关的半导体封装的制造方法中，在半导体晶片状态的上述半导体晶片的第1面上层叠上述多个半导体芯片；形成模塑树脂，以覆盖上述半导体芯片的整体；其后，通过切割上述半导体晶片，对分成了各个小片的多个半导体封装进行成形。
较为理想的是，在上述树脂模塑工序之后，通过从上述半导体晶片的与上述第1面相反的第2面一侧研磨来减薄上述半导体晶片；在上述半导体晶片的被研磨了的第2面上形成安装用的外部端子。
或者，在上述半导体晶片上层叠上述多个半导体芯片之前，最好在上述半导体晶片状态的上述半导体晶片的与上述第1面相反的第2面上粘接增强用基体材料。作为增强用基体材料，可使用玻璃板。在上述半导体晶片的上述第2面上粘接了上述增强用基体材料后，通过研磨上述半导体晶片的上述第1面来减薄上述半导体晶片，可以在上述减薄了的半导体晶片的上述第1面上层叠上述多个半导体芯片。再者，可以在上述半导体晶片上层叠上述多个半导体芯片之前，在上述第1面上形成再布线层。
在上述树脂模塑工序之后，最好除去上述增强用基体材料，并在上述半导体晶片的上述第2面上形成安装用的外部端子。或者，在粘接上述增强用基体材料之前，预先在上述半导体晶片的上述第2面上形成安装用外部端子。
按照本发明，由于在半导体晶片状态的介入片上层叠多个半导体芯片，并且在树脂模塑后进行切割，故提高了各工序中的操作和作业性。以前必须处理薄且小的介入片，操作是非常困难的。
通过在树脂模塑工序后(切割之前)减薄半导体晶片，提高了研磨工序中的操作性。
另一方面，通过在半导体晶片上粘接增强用基体材料，提高了机械的强度，进而提高了操作性。此外，通过减薄粘接在增强用基体材料上的半导体晶片，可在介入片的表面背面的两面上形成布线层。
通过在半导体晶片的与增强用基体材料粘接的一侧的面上预先形成安装用外部端子，外部端子的形成变得容易。即，可避免由于残存的粘接剂等的原因使外部端子的形成变得困难的事态。
附图说明
图1是表示可应用于与本发明有关的半导体封装的半导体芯片(A)及其层叠体(B)的结构的概略剖面图。
图2是表示可应用于与本发明有关的半导体封装的介入片用的硅晶片的概略平面图。
图3是表示与本发明第1实施例有关的半导体封装的制造工序(1-1，1-2)的剖面图，与图2的A-A方向的剖面相对应。
图4是表示与本发明的第1实施例有关的半导体封装的制造工序(1-3，1-4)的剖面图，与图2的A-A方向的剖面相对应。
图5是表示与第1实施例有关的半导体封装的制造工序(1-5，1-6)的剖面图，与图2的A-A方向的剖面相对应。
图6是表示与本发明的第2实施例有关的半导体封装的制造工序(2-1～2-3)的剖面图，与图2的A-A方向的剖面相对应。
图7是表示与第2实施例有关的半导体封装的制造工序(2-4，2-5)的剖面图，与图2的A-A方向的剖面相对应。
图8是表示与第2实施例有关的半导体封装的制造工序(2-6，2-7)的剖面图，与图2的A-A方向的剖面相对应。
图9是表示与第2实施例有关的半导体封装的制造工序(2-8，2-9)的剖面图，与图2的A-A方向的剖面相对应。
图10是表示与本发明的第3实施例有关的半导体封装的制造工序(3-1～3-3)的剖面图，与图2的A-A方向的剖面相对应。
图11是表示与第3实施例有关的半导体封装的制造工序(3-4，3-5)的剖面图，与图2的A-A方向的剖面相对应。
图12是表示与第3实施例有关的半导体封装的制造工序(3-6，3-7)的剖面图，与图2的A-A方向的剖面相对应。
图13是表示与第3实施例有关的半导体封装的制造工序(3-8)的剖面图，与图2的A-A方向的剖面相对应。
具体实施方式
以下，使用实施例详细地说明用于实施本发明的最佳方式。图1是表示可应用于与本发明有关的半导体封装的半导体芯片(A)及其层叠体(B)的结构的概略剖面图。图2是表示可应用于与本发明有关的半导体封装的介入片用的硅晶片的概略平面图。半导体芯片100成为在设置了贯通电极104的半导体衬底102的表面背面的两面上形成了凸点106的结构。再有，也可以是只在半导体衬底102的单侧形成凸点106的结构。希望半导体衬底102的厚度从贯通电极的深度算起是20-100μm。为了说明的方便起见，假定将如(B)图那样层叠了半导体芯片100的结构称为芯片层叠体120。将芯片层叠体120层叠在介入片上。在本发明中，采用了在晶片W状态的介入片上层叠半导体芯片100的方法。
图3～图5是表示与本发明第1实施例有关的半导体封装的制造工序的剖面图，与图2的A-A方向的剖面相对应。以下说明与本发明第1实施例有关的制造工序。首先，如图3(1-1)中所示，在介入片形成用的硅晶片112(W)的内部形成多个贯通电极114。硅晶片112的厚度约为500-1000μm。贯通电极114的上端在硅晶片112的表面上露出。在硅晶片112的表面上形成了布线层(再布线)118。在贯通电极114的上端形成了凸点116。虽然未图示，但在布线层118上和贯通电极114以外的部分的表面上形成了绝缘膜。贯通电极的深度可定为20-100μm。
作为凸点106、116的材质，可使用能熔融连接的SnAg、SnPb、Cu+SnAg、Au+SnAg等。作为贯通电极104、114的材质，可使用Cu、Al、W、Au、Ag、多晶硅等。此外，作为绝缘膜，可使用SiO2、SiN、聚酰亚胺等。
其次，如图3(1-2)中所示，利用众所周知的方法在硅晶片112的规定的位置上层叠半导体芯片100，对芯片层叠体120进行成形。在芯片层叠体120中，电连接了各半导体芯片100。
其次，如图4(1-3)中所示，从芯片层叠体120的侧面注入填充树脂122，通过加热使其固化。或者，也可采用在层叠半导体芯片100之前在安装半导体芯片100的中央附近预先供给填充树脂、在半导体芯片100的层叠时使其暂时固化、一层一层地层叠半导体芯片100并进行树脂密封的方法。作为填充树脂122，可使用由环氧材料和氧化硅(填充剂)构成的热固化性树脂。再有，为了密封窄的间隙，也可使用不混入氧化硅的树脂。
其次，如图4(1-4)中所示，用模塑树脂124一并地对硅晶片112的整个表面进行过模塑。关于过模塑，可利用使用了规定的尺寸的模具的传递模塑方式来成形。作为模塑树脂的材料，可使用环氧树脂。
其次，如图5(1-5)中所示，研磨硅晶片112的背面直到贯通电极114的下端露出。接着，如图5(1-6)中所示，在硅晶片112的背面的规定的位置上形成外部端子126。作为外部端子126的材料，可使用SnPb、SnAg等。其后，通过沿切割线进行切断，完成分成了各个小片的多个半导体封装(BGA)。在母板(安装布线基板)上安装已完成的半导体封装。
如上所述，按照本发明的第1实施例，由于可在晶片标准厚度的状态下进行半导体芯片的层叠和过模塑，故各工序间的操作变得容易。此外，由于在过模塑后研磨了硅晶片，故可抑制因强度不足引起的缺陷的发生，容易进行减薄。
图6～图9是表示与本发明第2实施例有关的半导体封装的制造工序的剖面图，与图2的A-A方向的剖面相对应。以下说明与本发明第2实施例有关的制造工序。再有，在本实施例中，对于与上述的第1实施例为同一或对应的构成要素，附以同一参照符号，省略重复的说明。
首先，如图6(2-1)中所示，在介入片形成用的硅晶片212(W)的内部形成多个贯通电极214。硅晶片212的厚度约为500-1000μm。贯通电极214的上端在硅晶片212的表面上露出。在硅晶片212的表面上形成了布线层(再布线)218。在贯通电极214上形成了凸点焊盘。虽然未图示，但在布线层218上和贯通电极214上形成了绝缘膜。贯通电极的深度可定为20-100μm。
作为贯通电极214的材质，可使用Cu、Al、W、Au、Ag、多晶硅等。此外，作为绝缘膜，可使用SiO2、SiN、聚酰亚胺等。
其次，如图6(2-2)中所示，经粘接剂215将玻璃板232粘贴到硅晶片212的布线层一侧的表面上。玻璃板232的外径比硅晶片212的外径约大500-2000μm或与硅晶片212的外径相同，使用厚度为500-1000μm且平面精度良好的板材。此外，作为粘接剂215的厚度，最好约为10-100μm。
其次，如图6(2-3)中所示，研磨硅晶片212的表面直到贯通电极214露出。其后，根据需要，如图7(2-4)中所示，在规定的位置上形成再布线217和凸点216。再者，在贯通电极214以外的部分的表面和再布线上形成绝缘层。此时，硅晶片212的的厚度为20-100μm。
其次，如图7(2-5)中所示，利用众所周知的方法在硅晶片212的规定的位置上层叠半导体芯片100，对芯片层叠体120进行成形。在芯片层叠体120中，电连接了各半导体芯片100。
其次，如图8(2-6)中所示，从芯片层叠体120的侧面注入填充树脂222，通过加热使其固化。或者，也可采用在层叠半导体芯片100之前在安装半导体芯片100的中央附近预先供给填充树脂、在半导体芯片100的层叠时使其暂时固化、一层一层地层叠半导体芯片100并进行树脂密封的方法。作为填充树脂222，可使用由环氧材料和氧化硅(填充剂)构成的热固化性树脂。再有，为了密封窄的间隙，也可使用不混入氧化硅的树脂。
其次，如图8(2-7)中所示，用模塑树脂224一并地对硅晶片212的整个表面进行过模塑。关于过模塑，可利用使用了规定的尺寸的模具的传递模塑方式来成形。作为模塑树脂的材料，可使用环氧树脂。
其次，如图9(2-8)中所示，从硅晶片212剥离玻璃板232和粘接剂215。接着，如图9(2-9)中所示，在硅晶片212的背面的规定的位置上设置外部端子226。作为外部端子226的材料，可使用SnPb、SnAg等。其后，通过沿切割线进行切断，完成分成了各个小片的多个半导体封装(BGA)。在母板(安装布线基板)上安装已完成的半导体封装。
如上所述，按照本发明的第2实施例，除了上述的第1实施例的效果外，由于可在硅晶片的表面背面的两面上形成再布线，故可与多品种相对应。此外，由于用玻璃板支撑了硅晶片，故到过模塑工序为止具有可抑制硅晶片的翘曲的效果。再有，作为粘接到硅晶片上的增强用基体材料，也可使用玻璃以外的材质的材料。
图10～图13是表示与本发明第3实施例有关的半导体封装的制造工序的剖面图，与图2的A-A方向的剖面相对应。以下说明与本发明第3实施例有关的制造工序。再有，在本实施例中，对于与上述的第1和第2实施例为同一或对应的构成要素，附以同一参照符号，省略重复的说明。
首先，如图10(3-1)中所示，在介入片形成用的硅晶片312(W)的内部形成多个贯通电极314。硅晶片312的厚度约为500-1000μm。贯通电极314的上端在硅晶片312的表面上露出。在硅晶片312的表面上形成了布线层(再布线)318、凸点焊盘316和外部端子319。此外，虽然未图示，但在布线层318上和贯通电极314以外的部分的表面上形成了绝缘膜。贯通电极的深度可定为20-100μm。
作为贯通电极314的材质，可使用Cu、Al、W、Au、Ag、多晶硅等。此外，作为绝缘膜，可使用SiO2、SiN、聚酰亚胺等。
其次，如图10(3-2)中所示，经粘接剂330将玻璃板332粘贴到硅晶片312的外部端子319一侧的表面上。玻璃板332的外径比硅晶片312的外径约大500-2000μm或与硅晶片312的外径相同，使用厚度为500-1000μm且平面精度良好的板材。此外，作为粘接剂315的厚度，最好约为10-100μm。
其次，如图10(3-3)中所示，研磨硅晶片312的表面直到贯通电极314露出。其后，根据需要，如图11(3-4)中所示，在规定的位置上形成再布线322和凸点324。再者，在贯通电极314以外的部分的表面和再布线322上形成绝缘层。此时，硅晶片312的的厚度为20-100μm。
其次，如图11(3-5)中所示，利用众所周知的方法在硅晶片312的规定的位置上层叠半导体芯片100，对芯片层叠体120进行成形。在芯片层叠体120中，电连接了各半导体芯片100。
其次，如图12(3-6)中所示，从芯片层叠体120的侧面注入填充树脂323，通过加热使其固化。或者，也可采用在层叠半导体芯片100之前在安装半导体芯片100的中央附近预先供给填充树脂、在半导体芯片100的层叠时使其暂时固化、一层一层地层叠半导体芯片100并进行树脂密封的方法。作为填充树脂323，可使用由环氧材料和氧化硅(填充剂)构成的热固化性树脂。再有，为了密封窄的间隙，也可使用不混入氧化硅的树脂。
其次，如图12(3-7)中所示，用模塑树脂325一并地对硅晶片312的整个表面进行过模塑。关于过模塑，可利用使用了规定的尺寸的模具的传递模塑方式来成形。作为模塑树脂的材料，可使用环氧树脂。
其次，如图13(3-8)中所示，从硅晶片312剥离玻璃板332和粘接剂330。接着，其后，通过沿切割线进行切断，完成分成了各个小片的多个半导体封装(BGA)。在母板(安装布线基板)上安装已完成的半导体封装。
如上所述，按照本发明的第3实施例，除了上述的第1和第2实施例的效果外，由于在由粘接剂污染焊盘之前预先设置了外部端子319，故提高了介入片与外部端子319的连接的可靠性。
以上，用实施例说明了本发明，但本发明不由实施例的范围来限定，在各项权利要求中记载了的技术的思想的范围内，当然可适当地变更设计。

Claims (9)

1.一种在具有贯通电极的介入片上层叠多个半导体芯片而构成的半导体封装的制造方法，其特征在于：
在介入片用的半导体晶片的第1面上层叠上述多个半导体芯片，
形成模塑树脂，以覆盖上述半导体芯片的整体，
其后，通过切割上述半导体晶片，对分成了各个小片的多个半导体封装进行成形。
2.如权利要求1中所述的半导体封装的制造方法，其特征在于：
在上述树脂模塑工序之后，从上述半导体晶片的与上述第1面相反的第2面一侧研磨上述半导体晶片。
3.如权利要求1中所述的半导体封装的制造方法，其特征在于：
在上述半导体晶片上层叠上述多个半导体芯片之前，在上述半导体晶片的与上述第1面相反的第2面上粘接增强用基体材料。
4.如权利要求3中所述的半导体封装的制造方法，其特征在于：
上述增强用基体材料是玻璃板。
5.如权利要求3或4中所述的半导体封装的制造方法，其特征在于：
在上述树脂模塑工序之后，除去上述增强用基体材料，在上述半导体晶片的上述第2面上形成外部端子。
6.如权利要求3或4中所述的半导体封装的制造方法，其特征在于：
在粘接上述增强用基体材料之前，预先在上述半导体晶片的上述第2面上形成安装用外部端子。
7.如权利要求3、4、5或6中所述的半导体封装的制造方法，其特征在于：
在上述半导体晶片的上述第2面上粘接了上述增强用基体材料后，研磨上述半导体晶片的上述第1面，
在上述半导体晶片的被研磨了的上述第1面上层叠上述多个半导体芯片。
8.如权利要求3、4、5、6或7中所述的半导体封装的制造方法，其特征在于：
在上述半导体晶片上层叠上述多个半导体芯片之前，在上述第1面上形成再布线层。
9.如权利要求2中所述的半导体封装的制造方法，其特征在于：
在研磨上述半导体晶片的工序之后，在上述半导体晶片的上述第2面上形成外部端子。
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JP3690407B2 (ja) * 2003-07-31 2005-08-31 セイコーエプソン株式会社 半導体装置の製造方法
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
JP2005236245A (ja) 2004-01-23 2005-09-02 Seiko Epson Corp 半導体装置およびその製造方法、半導体チップおよびその製造方法、並びに電子機器

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CN101499464B (zh) * 2008-02-01 2013-01-02 海力士半导体有限公司 使用穿通电极制备堆叠封装的方法
CN102024713A (zh) * 2009-09-14 2011-04-20 台湾积体电路制造股份有限公司 半导体封装体工艺
CN102024713B (zh) * 2009-09-14 2013-08-21 台湾积体电路制造股份有限公司 半导体封装体工艺
US9997440B2 (en) 2009-09-14 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for adhesive material at wafer edge
CN104321866A (zh) * 2012-09-14 2015-01-28 瑞萨电子株式会社 半导体器件的制造方法
CN104321866B (zh) * 2012-09-14 2018-03-02 瑞萨电子株式会社 半导体器件的制造方法
CN112970108A (zh) * 2018-10-23 2021-06-15 株式会社大赛璐 半导体装置制造方法

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CN101017786B (zh) 2011-11-16
KR101347633B1 (ko) 2014-01-09
KR20070080811A (ko) 2007-08-13

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