CN101330068B - 模制重配置晶片、使用其的叠置封装及该封装的制造方法 - Google Patents

模制重配置晶片、使用其的叠置封装及该封装的制造方法 Download PDF

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CN101330068B
CN101330068B CN2007101437824A CN200710143782A CN101330068B CN 101330068 B CN101330068 B CN 101330068B CN 2007101437824 A CN2007101437824 A CN 2007101437824A CN 200710143782 A CN200710143782 A CN 200710143782A CN 101330068 B CN101330068 B CN 101330068B
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stack package
semiconductor chip
molded
electrode
substrate
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CN101330068A (zh
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金钟薰
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种模制的重配置晶片、使用其的叠置封装以及该叠置封装的制造方法。该叠置封装包括至少两个叠置封装单元。每一封装单元包括：在其上表面上具有接合焊垫的半导体芯片；形成以包围半导体芯片侧面的模制部；形成于模制部中的贯通电极；及形成以互连贯通电极与邻近的接合焊垫的重分布线。本发明可以简化制造工艺而降低制造成本。

Description

模制重配置晶片、使用其的叠置封装及该封装的制造方法
技术领域
本发明涉及一种叠置封装，更详细而言，涉及一种模制的重配置晶片、使用该晶片的叠置封装，以及制造该叠置封装的方法，该晶片可以简化工艺并减少制造成本。
背景技术
半导体集成装置的封装技术的持续发展导致装置的小型化与高容量化。近年来各种能够满足小型化，高容量化及高效率安装的叠置封装技术已被开发了。
术语″叠置″用在半导体工业意思为垂直叠置至少两片半导体芯片或封装。利用叠置技术，在存储器装置的情形，可以实现一种具有可经半导体集成工艺获得的较大存储容量、以及安装面积的使用上增加效率的产品。
取决于制造技术，叠置封装可分为：第一型，其中个别的半导体芯片叠置且叠置后的半导体芯片被一次封装；第二型，其中个别分开封装的半导体芯片被叠置。叠置封装使用金属线或贯通硅通孔(through-silicon via)来将半导体芯片相互电连接。
图1为使用金属线的传统叠置封装的剖面图。
参照图1，使用金属线的叠置封装100中，至少有两个半导体芯片110通过粘接剂114叠置于基板120上。各芯片110及基板120通过金属线116相互电连接。
图1中，未经说明的参考标号112指接合焊垫，122为连接焊垫，124为球形焊接点，126为电路导线，170为外部连接端子，及190为密封剂。
然而在使用金属线的传统叠置封装中，由于电信号经金属线传输，因此信号交换速率不高，且由于使用许多金属线，个别芯片的电特性易于劣化。此外，基板中须有额外的区域来形成金属线，因此增加了封装的尺寸，更因须有间隙以供将金属线键合于接合焊垫，因此整个封装高度增加。
因此，为了克服使用金属线的叠置封装造成的问题，避免叠置封装电特性的劣化，并且能够使得叠置封装的小型化，在本领域中曾推荐使用贯通硅通孔的方式。
图2为说明使用贯通硅通孔的传统叠置封装的剖面图。
参照图2，使用贯通硅通孔的叠置封装200中，其中形成有贯通硅通孔230的半导体芯片210叠置于基板220上，如此则可互连相对应的贯通硅通孔230。
在图2中，未经说明的参考标号212指接合焊垫，222为连接焊垫，224为球形焊接点，226为电路导线，而270为外部连接端子。
在使用贯通硅通孔的叠置封装中，由于通过贯通硅通孔形成电连接，因此避免了半导体芯片电特性的降低，而增加了半导体芯片的操作速率，使得能够小型化。
然而在使用贯通硅通孔的传统叠置封装中，必须形成贯通硅通孔以贯穿半导体芯片，且在形成有贯通硅通孔的半导体芯片部分中不能形成电路。因此工艺的复杂性增加了制造成本，且因须要通过设计顾虑贯通硅通孔的半导体芯片来制备晶片，不能使用包括广泛应用的半导体芯片的晶片。
发明内容
本发明的一实施例涉及模制的重配置晶片，使用其的叠置封装，及制造该叠置封装的方法，该晶片可简化工艺。
本发明的另一实施例涉及模制的重配置晶片，使用其的叠置封装，及制造该叠置封装的方法，该晶片可降低制造成本。
在一方面中，模制的重配置晶片包括：模制部，形成以包围半导体芯片侧面与下表面，各半导体芯片具有在其上表面上的多个接合焊垫；贯通电极，贯穿模制部的上面和模制部的相对上面的下面，邻近于各该半导体芯片的接合焊垫；及重分布线，形成于以互连贯通电极与邻近接合焊垫。
各贯通电极形成以具有比各半导体芯片的下表面更深的深度。
贯通电极与重分布线形成以相互集成。
另一方面中，叠置封装包括至少两个叠置封装单元，每一封装单元包括：在其上表面上具有接合焊垫的半导体芯片；包围半导体芯片侧面的模制部；形成于模制部中的贯通电极；及形成以相互连接贯通电极与邻近接合焊垫的重分布线。
各贯通电极的下表面从封装单元的下表面突出。
贯通电极与重分布线的形成以相互集成。
各叠置封装单元具有互不相同尺寸的半导体芯片。
具有不同尺寸的半导体芯片的各叠置封装单元具有相同的整体尺寸。
叠置封装还包括：基板，其上装设叠置封装；和外连接端子，装设到基板的下表面。
叠置封装还包括介于叠置封装单元间及最下层叠置封装单元与基板之间的填充材料。
叠置封装还包括形成于最上层封装单元的上表面上的盖层。
叠置封装还包括密封剂，形成于填充于叠置单元间及最下层封装单元与基板之间，以覆盖包括最上层封装单元的上表面的基板上表面。
叠置封装单元以面向下方式叠置于基板上。
叠置封装还包括叠置于最上层封装单元上的半导体芯片，而并未具有贯通电极与重分布线。
未具有贯通电极与重分布线的半导体芯片的接合焊垫再对准以对应于最上层封装单元的贯通电极。
再另一方面中，制造叠置封装的方法包括的步骤有：在多个模制的重配置晶片的各个的模制部的一部分中界定沟槽，该部分邻近于多个半导体芯片的接合焊垫，各模制的重配置晶片具有其上表面上设有接合焊垫的多个半导体芯片，及形成以包围半导体芯片的侧面和下表面的模制部；形成贯通电极于沟槽中，并形成互连邻近的贯通电极与接合焊垫的重分布线；移除模制的重配置晶片的下表面以暴露贯通电极的下表面，因而构成多个封装单元；叠置封装单元使各对应的贯通电极相互连接；及在芯片级切割在晶片级叠置的封装单元。
每一沟槽被界定以具有比各半导体芯片的下表面更深的深度。
形成贯通电极及重分布线的步骤包括：形成金属种子层于包括沟槽的模制的重配置晶片的上表面上；形成金属层于金属种子层上以填充沟槽；及将金属层与金属种子层图案化。
在形成金属种子层的步骤后与图案化金属层与金属种子层的步骤前，该方法还包括的步骤有：回蚀刻金属层以减小金属层的厚度。
模制的重配置晶片下表面的移除利用研磨与蚀刻工艺中的至少一种来进行，使得模制部在模制的重配置晶片的下表面上被移除。
在叠置封装单元的步骤后，该方法还包括有步骤：将填充材料夹于封装单元间并形成盖层于最上封装单元上。
叠置封装单元各自具有尺寸不同的半导体芯片。
在芯片级切割封装单元的步骤之后，该方法还包括的步骤为：将形成有贯通电极的叠置封装单元装设于基板。
制造方法还包括的步骤为：将填充材料夹于装设于基板的最下层封装单元与基板间。
在将叠置封装单元装设于基板的步骤后，该方法还包括的步骤为：形成密封剂以填充于叠置封装间及最下层封装单元与基板之间，并且覆盖包括最上层封装单元的上表面的基板的上表面。
在将叠置封装单元装设于基板后，该方法还包括的步骤为：将外部连接端子装设于基板的下表面。
附图说明
图1为示出使用金属线的传统叠置封装的剖面图。
图2为示出使用贯通硅通孔的传统叠置封装的剖面图。
图3A及3B为说明传统的模制的重配置晶片的视图与相片。
图4为根据本发明第一实施例的模制的重配置晶片的剖面图。
图5为根据本发明第二实施例的叠置封装的剖面图。
图6A至6F为示出根据本发明第二实施例的叠置封装制造方法工艺的剖面图。
图7为示出根据本发明第三实施例的叠置封装的剖面图。
图8为示出根据本发明第四实施例的叠置封装的剖面图。
图9为示出根据本发明第五实施例的叠置封装的剖面图。
具体实施方式
在本发明中，模制的重配置晶片的制造方式为模制部形成以包围在其上设有接合焊垫的半导体芯片的侧面与下表面，贯通电极则形成于模制部的侧面模制部分，且重分布线将贯通电极与接合焊垫相互连接。叠置封装利用模制的重配置晶片而实现。
详细的说，模制的重配置晶片包括：通常具有良好品质的半导体芯片，其以规则间隔配置，而且具有在其上设置的接合焊垫；形成以包围各半导体芯片侧面与下表面的模制部；形成于模制部侧面模制部分的贯通电极；及相互连接贯通电极与半导体芯片的接合焊垫的重分布线。在本发明中，至少两个模制的重配置晶片利用贯通电极相互叠置，然后在芯片级分割，由是形成叠置封装。
结果，本发明中，具有贯通电极形成于其模制部的模制的重配置晶片被叠置而使各晶片的贯通电极电连接。因此，无需通过设计一种顾虑到贯通电极的半导体芯片来制备晶片以形成叠置封装，而广泛使用的半导体芯片就可以足以采用。因此，可以简化制造工艺而降低制造成本。
此外，在本实施例中，由于叠置封装利用模制的重配置晶片形成，而该晶片只利用良好品质的半导体芯片，可以消除因有一个不良半导体芯片而否定整个叠置封装的可能性，因此可避免成品率的降低。
下文中将详细说明关于本发明各实施例的模制的重配置晶片，使用其的叠置封装，以及制造该叠置封装的方法。
图3A及3B为说明传统模制的重配置晶片的视图与相片，图4为根据本发明第一实施例的模制的重配置晶片的剖面图。
参照图3A及3B，传统模制的重配置晶片350a形成的方式为使多个良好品质半导体芯片310位于载体390的希望位置，其上表面贴有双面胶带392，模制部340形成于双面胶带392上以包围半导体芯片310，且然后移除载体390及双面胶带392。
换言之，模制的重配置晶片利用一种技术制造，其中良好品质的半导体芯片从晶片分离，该芯片经芯片制造工艺置于载体上，然后新晶片经进行模制工艺而制造。制造模制的重配置晶片的方法曾揭示于M.Brunnbauer等的″An Embedded Device Technology Based on a Molded Reconfigured Wafer″，ECTC，2006，PP547～551中。
本发明被构建以在传统的模制重配置晶片中通过形成贯通电极合重分布线来实现叠置封装。
参照图4，在根据本发明的模制的重配置晶片450a中，贯通电极430形成于邻近接合焊垫412的模制部440中，该接合焊垫412设于传统模制的重配置晶片的各半导体芯片410上，使得贯通电极430具有比半导体芯片410的下表面更深的深度，但不穿透模制部440。此外，重分布线432形成以相互电连接接合焊垫412与邻近的贯通电极430。
贯通电极430与重分布线432优选地通过沉积金属层于金属种子层434上而且将它们图案化来相互一体形成。贯通电极430，重分布线432，及金属种子层434由Sn、Ni、Cu、Au及Al的或其组合的至少一种制成。
下文中说明根据本发明利用模制的重配置晶片的叠置封装。
图5为根据本发明的第二实施例的叠置封装的剖面图。
参照图5，根据本发明的叠置封装400形成的方式为，至少两个封装单元450相互叠置，所述封装单元450利用模制的重配置晶片450a形成，该模制的重配置晶片450a具有贯通电极430及重分布线432，。
各封装单元450包括：半导体芯片410，在其上表面的两侧设有接合焊垫412；模制部440，形成以包围半导体芯片410的侧面；贯通电极430，形成于邻近接合焊垫412的模制部440中；及重分布线432，相互电连接接合焊垫412与邻近贯通电极430。
为了保证叠置封装400的容易形成，贯通电极430从封装单元450的下表面突出，而叠置封装单元450的对应的贯通电极430相互连接。
为了电连接叠置封装单元450与外界，叠置封装单元450安装于基板420上。基板420具有多个在其上表面上的连接衬垫422、连接外部连接端子470的在其下表面上的球形焊接点424、和其内部的电路导线426。最下层封装单元450的贯通电极430与基板420的连接焊垫422电连接。
第一填充材料460，第二填充材料462及盖层464分别形成于叠置封装单元450间，最下层封装单元450与基板420之间，及最上层封装单元450的上表面上，以确保半导体芯片410的电绝缘与保护。
如上所述，依照本发明利用模制的重配置晶片形成叠置封装，该模制的重配置晶片在其模制部中形成有贯通电极，当在晶片级形成叠置封装时，由于其可能防止多个良好品质的半导体芯片因存在有劣化芯片而变成无用，提高了制造的成品率。同样，由于叠置封装可以利用广泛使用的半导体芯片来实现，简化了制造工艺且降低了制造成本。
图6A至6F为示出根据本发明第二实施例的叠置封装制造方法的剖面图。
参照图6A，准备模制的重配置晶片450a，其包括：在其上表面上设有多个接合焊垫412半导体芯片410，及包围半导体芯片410的侧面与下表面的模制部440。然后在模制的重配置晶片450a的模制部的一部分中界定沟槽T，沟槽T邻近于各接合焊垫412，使得沟槽T具有比半导体芯片410更深的深度，但不穿透模制部440。
参照图6B，在金属种子层434形成于包括沟槽T的表面的模制的重配置晶片450a上，通过对所形成的模制的重配置晶片450a实施镀覆工艺，形成金属层432a于金属种子层434上，以填充沟槽T。金属种子层434及金属层432a由Sn、Ni、Cu、Au及Al或其组合的至少一种制成。金属种子层432a可经回蚀刻工艺蚀刻一预定厚度，以便减小所得叠置封装的整体高度。
参照图6C，通过将形成于模制的重配置晶片450a上的金属层432a及金属种子层434图案化，贯通电极430及用以电互连半导体芯片410的接合焊垫412与邻近贯通电极430的重分布线432形成于模制的重配置晶片450a中。金属层432a以湿蚀刻工艺蚀刻。
参照图6D，通过实施研磨工艺与蚀刻工艺的至少一中，移除叠置封装450a的下部，贯通电极430的下部即暴露于外。因此形成了包括多个封装单元450的模制的重配置晶片450b。优选地，模制的重配置晶片450a下部的移除方式可使贯通电极430的下部从模制的重配置晶片450b的模制部440突出，以便在形成叠置封装时确保稳定的电连接。
参照图6E，包括多个封装单元450的至少两个模制的重配置晶片450b被叠置，使得形成于各模制的重配置晶片450b的封装单元450中的相对应的贯通电极430相互连接。其次，第一填充材料460及盖层464分别形成于叠置模制的重配置晶片450b间及最上层的模制的重配置晶片450b上，而得以保证半导体芯片410的电绝缘及保护。
参照图6F，由此在芯片级切割在晶片级叠置的模制的重配置晶片450b，即可获得封装单元450相互上下叠置的结构。由此，叠置封装单元450安装于基板420上，其具有在其上表面上的多个连接衬垫422、在其下表面上的球形焊接点424、及在其内部的电路导线426。然后外部连接端子470装设于球形焊接点424。此时叠置封装单元450的最下层封装单元450的贯通电极430则与基板420的连接衬垫422相应地装设。第二填充材料462夹于最下层封装单元450与基板420间，由此改善结合点的可靠性。
图7为示出根据本发明第三实施例的叠置封装的剖面图。
参照图7，根据本发明的叠置封装400中，封装单元450以与图5同样方式叠置，取代第一填充材料460、第二填充材料462、及盖层464，密封剂480夹于至少两个叠置封装单元450间及最低层封装单元450与基板420间，并覆盖包括最上层封装单元450的上表面的基板420的上表面。
在此叠置封装中，叠置封装单元450以与图6A至6E同样方式叠置，直到形成第一填充材料460及盖层464之前，且然后在叠置封装单元450装设于基板420后，为了保证电绝缘与增进结合点的可靠性，密封剂480形成以填充于至少两个叠置封装单元450间及最低层封装单元450与基板420之间，并且覆盖包括最上层封装单元450的上表面的基板420的上表面。
同时，参照图8，根据本发明第四实施例的叠置封装500被配置，使得具有不同尺寸的半导体芯片510的封装单元550相互叠置。封装单元550形成以具有相同尺寸。详细的说，当构成封装单元550的半导体芯片510的尺寸相对较小时，通过增大模制部540，即可使叠置封装单元550具有同样尺寸。
用以互连设于各封装单元550的接合焊垫412与贯通电极530的重分布线532形成具有相同长度。这是为了要保证即使利用不同尺寸的半导体芯片510形成封装单元550，重分布线532可简单的利用相同光掩模图案以图案化工艺来形成。重分布线532的长度决定于最小尺寸的半导体芯片510。
不含重分布线532及半导体芯片510的叠置封装500的其余结构与如图5所示相同，而其制造方法则与如图6A至6F所示相同。
另外，参照图9，在根据本发明第五实施例的叠置封装600中，具有与如图5所示相同结构的封装单元650被叠置于基板620上，封装单元650叠置成封装单元650的上表面面对着基板620，而形成封装单元650上表面上的重分布线632则装设于基板620。另外，贯通电极630及重分布线632并非形成于最上层封装单元650，而是具有取代贯通电极的重布线接合焊垫612a的通用结构的半导体芯片610a位于最上层。
构成叠置封装600的封装单元650的结构与如图5所示相同，而封装单元650的制造方法与如图6A至6F所示相同。
此外，虽然未示于图中，在本发明中，叠置封装可构成的方式为：虽然封装单元被叠置以具有与上述叠置结构相同的结构，但不使用基板来形成电连接，再布置层形成于最下层叠置封装单元的下表面上，而外部连接端子则装设于再布置层。
从以上的说明可以明了，本发明的优点在于，由于利用各具有包围半导体芯片的模制部且其中形成有贯通电极的模制的重配置晶片来实现叠置封装，所以并不须通过设计顾虑贯通电极的半导体芯片来制备晶片形成叠置封装，而广泛被使用的半导体芯片就可以足以被采用，由此简化制造工艺，减少制造成本。此外，在本发明重，因叠置封装利用只采用良好品质的半导体芯片的模制的重配置晶片形成，消除了由于一个劣化的半导体芯片而否决整体叠置封装的可能性，亦可避免降低制造成品率。
虽然为了说明的目的，描述了本发明的特定的施例，但是本领域的技术人员将理解在不脱离由所附权利要求中所披露的本发明的范围和精神的情况下，各种修改、附加和替换是可能的。
本申请要求于2007年6月18日提出的韩国专利申请第10-2007-0059315号的优先权，其整体在此引入作为参考。

Claims (24)

1.一种模制的重配置晶片，包括：
模制部，形成以包围半导体芯片的侧面与下表面，各该半导体芯片具有在其上表面上的多个接合焊垫，从而该半导体芯片和该接合焊垫的上表面全部被暴露；
多个贯通电极，贯穿模制部的上面和模制部的相对上面的下面，邻近于该半导体芯片的接合焊垫；及
多条重分布线，形成以互连各该贯通电极与暴露的邻近的接合焊垫，该重分布线直接设置于该模制部的上表面和该半导体芯片的上表面，
其中所述模制部中的各该贯通电极形成以具有比模制部中的各该半导体芯片的下表面更深的底部深度。
2.如权利要求1的模制的重配置晶片，其中所述贯通电极与重分布线一体成形。
3.一种包括至少两个叠置封装单元的叠置封装体，每一封装单元包括：
半导体芯片，各具有上和下表面，使接合焊垫形成于各该半导体芯片的上表面，从而该半导体芯片和该接合焊垫的上表面全部被暴露；
模制部，形成以包围各该半导体芯片的侧面；
多个贯通电极，贯穿模制部的上面和模制部的相对上面的下面，邻近于各该半导体芯片的接合焊垫；及
重分布线，形成以相互连接所述贯通电极与邻近的接合焊垫，该重分布线直接设置于该模制部的上表面和该半导体芯片的上表面，
其中该模制部的上表面和该半导体芯片的上表面设置在相同的高度，使得该模制部的上表面和该半导体芯片的上表面彼此连接。
4.如权利要求3的叠置封装体，其中所述模制部中的各该贯通电极下表面从该封装单元的下表面突出。
5.如权利要求3的叠置封装体，其中所述贯通电极与重分布线一体成形。
6.如权利要求3的叠置封装体，其中所述半导体芯片至少一个尺寸不同。
7.如权利要求6的叠置封装体，其中无论在其中封装的半导体芯片尺寸不同，至少两个叠置封装单元尺寸相同。
8.一种叠置封装体，包括：
基板；
至少两个叠置封装单元，装设在所述基板的上表面；
形成于最上层封装单元的上表面上的盖层，及
外部连接端子，装设于该基板的下表面，
每一封装单元包括：
半导体芯片，各具有上和下表面，使接合焊垫形成于各该半导体芯片的上表面，从而该半导体芯片和该接合焊垫的上表面全部被暴露；
模制部，形成以包围各该半导体芯片的侧面；
多个贯通电极，贯穿模制部的上面和模制部的相对上面的下面，邻近于各该半导体芯片的接合焊垫；及
重分布线，形成以相互连接所述贯通电极与邻近的接合焊垫，该重分布线直接设置于该模制部的上表面和该半导体芯片的上表面，
其中该模制部的上表面和该半导体芯片的上表面设置在相同的高度，使得该模制部的上表面和该半导体芯片的上表面彼此连接。
9.如权利要求8的叠置封装体，还包括：
夹于这些叠置封装间及最下层封装单元与该基板之间的填充材料。
10.如权利要求8的叠置封装体，还包括：
密封剂，用以填充于这些叠置封装单元间及最下层封装单元与该基板间而覆盖包括最上层封装单元的上表面的该基板的上表面。
11.如权利要求8的叠置封装体，其中所述叠置封装单元以面朝下的方式叠置于该基板上。
12.如权利要求11的叠置封装体，还包括：
半导体芯片，叠置于该最上层的封装单元，而该叠置的半导体芯片不具有贯通电极与重分布线。
13.如权利要求12的叠置封装体，其中所述不具贯通电极及重分布线的该半导体芯片的接合焊垫被再对准以相对应于该最上层封装单元的贯通电极。
14.一种制造叠置封装的方法，包括的步骤有：
提供具有并排排列多个半导体芯片的模制的重配置晶片，各该晶片具有多个在其上表面上的接合焊垫，及包围各该半导体芯片的侧面与下表面的模制部；
在邻近各半导体芯片的接合焊垫的该模制部内界定沟槽；
在这些沟槽内形成贯通电极，并且形成相互连接这些贯通电极与这些邻近的接合焊垫的重分布线；
移除该叠置封装下表面的一部分，以暴露这些贯通电极的下表面，从而在该模制的重配置晶片中形成多个封装单元；
叠置至少两个模制的重配置晶片，其中来自各叠置晶片的封装单元叠置成相对应的贯通电极相互连接；及
将这些叠置的模制的重配置晶片的叠置封装单元切割为芯片级。
15.如权利要求14的方法，其中所述各沟槽被界定以具有比各半导体芯片的下表面更深的深度。
16.如权利要求14的方法，其中所述形成贯通电极及重分布线的步骤还包括下列步骤：
形成金属种子层于包括这些沟槽的该模制的重配置晶片的上表面上；
形成一金属层于该金属种子层上以填充这些沟槽；及
将该金属层与该金属种子层图案化。
17.如权利要求14的方法，在形成金属层的步骤后及图案化该金属层与该金属种子层的步骤前，该方法包括的步骤有：
回蚀刻该金属层以减小该金属层的厚度。
18.如权利要求14的方法，其中所述模制重配置晶片的下表面的移除利用研磨工艺及蚀刻工艺中的至少一中来实施，使得模制部在所述模制重配置晶片的下表面上被移除。
19.如权利要求14的方法，在叠置这些封装单元的步骤后，该方法还包括的步骤有：
将填充材料填入于这些叠置封装单元间，并形成盖层于最上层封装单元上。
20.如权利要求14的方法，其中所述叠置封装单元具有其各自的半导体芯片，所述半导体芯片尺寸互不相同。
21.如权利要求14的方法，其中在切割所述封装单元成为芯片级的步骤后，该方法还包括的步骤有：
将形成有这些贯通电极的这些叠置封装单元装设于基板。
22.如权利要求21的方法，还包括的步骤有：
将填充材料填入于装设于该基板的最下层封装单元与该基板之间。
23.如权利要求21的方法，在装设这些叠置封装单元于该基板的步骤后，该方法还包括的步骤有：
形成密封剂以填充于这些叠置封装单元间及最下层封装单元与该基板之间，并覆盖包括最上层封装单元的上表面的该基板的上表面。
24.如权利要求21的方法，在将这些叠置封装单元装设于该基板的步骤后，该方法还包括的步骤有：
将外部连接端子装设于该基板的下表面。
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