CN111276457A - 双晶片存储器封装 - Google Patents

双晶片存储器封装 Download PDF

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Publication number
CN111276457A
CN111276457A CN201910140540.2A CN201910140540A CN111276457A CN 111276457 A CN111276457 A CN 111276457A CN 201910140540 A CN201910140540 A CN 201910140540A CN 111276457 A CN111276457 A CN 111276457A
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Prior art keywords
conductive
die
chip
pad
redistribution layer
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CN201910140540.2A
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Inventor
黄信贸
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种双晶片存储器封装，其包含封装基板、第一晶片、第二晶片、接合引线以及导电柱。第一晶片设置于封装基板上，并且包含第一导电接垫以及第一接合垫。第一导电接垫以及第一接合垫设置于第一晶片背向封装基板的表面。第二晶片设置于第一晶片远离封装基板的一侧。第二晶片包含第二导电接垫，其设置于第二晶片面向第一晶片的表面。第一接合垫通过接合引线电性连接封装基板。第一导电接垫通过导电柱电性连接第二导电接垫。上述结构配置使得三维晶片堆叠能在不需要硅穿孔下实现。

Description

双晶片存储器封装
技术领域
本发明是关于一种双晶片存储器封装，特别是关于一种不需要硅穿孔的双晶片存储器封装。
背景技术
近年来，三维晶片堆叠技术被广泛采用以生产体积小巧的高容量存储器封装。三维堆叠的存储器封装通常包含多个垂直堆叠并通过硅穿孔(through-silicon via，TSV)以及微凸块(microbump)互连的半导体晶片，然而，对此等基于硅穿孔的存储器装置而言，硅穿孔的使用可能会在制造上带来额外的复杂性，从而增加生产成本。
发明内容
有鉴于此，本发明的一目的在于提出一种不需要硅穿孔的三维堆叠存储器封装。
为实现上述目的，依据本发明的一些实施方式，一种双晶片存储器封装包含封装基板、第一晶片、第二晶片、接合引线以及导电柱。第一晶片设置于封装基板上，并且包含第一导电接垫以及第一接合垫。第一导电接垫以及第一接合垫设置于第一晶片背向封装基板的表面。第二晶片设置于第一晶片远离封装基板的一侧。第二晶片包含第二导电接垫，其设置于第二晶片面向第一晶片的表面。第一接合垫通过接合引线电性连接封装基板。第一导电接垫通过导电柱电性连接第二导电接垫。
在本发明的一或多个实施方式中，第一导电接垫以及第二导电接垫于垂直于第一晶片的所述表面的方向上对齐。导电柱位于第一导电接垫以及第二导电接垫之间，并且接触第一导电接垫以及第二导电接垫。
在本发明的一或多个实施方式中，第二导电接垫在第一晶片的所述表面上的垂直投影与第一导电接垫完全重叠。
在本发明的一或多个实施方式中，第一导电接垫以及第二导电接垫在垂直于第一晶片的所述表面的方向上不对齐。
在本发明的一或多个实施方式中，第二导电接垫在第一晶片的所述表面上的垂直投影至少部分与第一导电接垫不重叠。
在本发明的一或多个实施方式中，第一晶片进一步包含重分布层，其设置于第一晶片的所述表面，并且电性连接第一导电接垫。导电柱位于重分布层以及第二导电接垫之间，并且接触重分布层以及第二导电接垫。
在本发明的一或多个实施方式中，第二晶片进一步包含重分布层，其设置于第二晶片的所述表面，并且电性连接第二导电接垫。导电柱位于重分布层以及第一导电接垫之间，并且接触重分布层以及第一导电接垫。
在本发明的一或多个实施方式中，第一晶片进一步包含第一重分布层，其设置于第一晶片的所述表面，并且电性连接第一导电接垫。第二晶片进一步包含第二重分布层，其设置于第二晶片的所述表面，并且电性连接第二导电接垫。导电柱位于第一重分布层以及第二重分布层之间，并且接触第一重分布层以及第二重分布层。
在本发明的一或多个实施方式中，第一重分布层远离第一导电接垫的一端对齐第二重分布层远离第二导电接垫的一端。
在本发明的一或多个实施方式中，导电柱接触第一重分布层远离第一导电接垫的一端以及第二重分布层远离第二导电接垫的一端。
在本发明的一或多个实施方式中，接合引线的两端分别接触第一接合垫以及封装基板。
在本发明的一或多个实施方式中，第一晶片进一步包含重分布层，其设置于第一晶片的所述表面，并且电性连接第一接合垫。接合引线的两端分别接触重分布层以及封装基板。
在本发明的一或多个实施方式中，重分布层远离第一接合垫的一端延伸至第一晶片的边缘。
在本发明的一或多个实施方式中，接合引线的两端分别接触封装基板以及重分布层远离第一接合垫的一端。
在本发明的一或多个实施方式中，接合引线部分延伸至形成于第一晶片以及第二晶片之间的间隙内。
在本发明的一或多个实施方式中，第一晶片于封装基板上的垂直投影与接合引线接触封装基板的一端彼此分离。
在本发明的一或多个实施方式中，第一导电接垫对应第二导电接垫，且第一晶片以及第二晶片具有相同的结构。
综上所述，本发明的双晶片存储器封装包含堆叠于基板上的两晶片(即上述的第一晶片与第二晶片)。两晶片的导电接垫彼此面对而使两晶片呈面对面的配置，并且两导电接垫通过设置于其间的导电柱彼此电性耦接。位于下方的第一晶片进一步包含接合垫，其通过接合引线电性耦接封装基板，借此促成晶片与封装间的沟通。上述结构配置使得三维晶片堆叠能在不需要硅穿孔下实现。
附图说明
参照以下附图阅读下文中详述的实施方式，可更透彻地理解本发明。
图1依据本发明的一些实施方式绘示双晶片存储器封装的剖视示意图。
图2依据本发明的另一些实施方式绘示双晶片存储器封装的剖视示意图。
图3依据本发明的另一些实施方式绘示双晶片存储器封装的剖视示意图。
图4依据本发明的另一些实施方式绘示双晶片存储器封装的剖视示意图。
图5依据本发明的另一些实施方式绘示双晶片存储器封装的剖视示意图。
具体实施方式
以下详细介绍本发明的实施方式，并且在附图中绘示示例性的实施方式。附图与说明书中尽可能使用相同的元件符号来代表相同或相似的元件。
请参照图1，其依据本发明的一些实施方式绘示双晶片存储器封装100(dual-diememory package)的剖视示意图。双晶片存储器封装100包含封装基板190、第一晶片110、第二晶片120、接合引线130以及导电柱140。第一晶片110设置于封装基板190上，而第二晶片120设置于第一晶片110远离封装基板190的一侧，换言之，第一晶片110与第二晶片120是以第一晶片110在下、第二晶片120在上的方式堆叠于封装基板190上。在一些实施方式中，双晶片存储器封装100为三维堆叠双层第四代双倍资料率同步动态随机存取存储器(3D-stack 2-height double data rate fourth-generation synchronous dynamic random-access memory，3DS 2H DDR4SDRAM)封装。
如图1所示，第二晶片120包含第二导电接垫121，其设置于第二晶片120面向第一晶片110的下表面123上(亦即，第二晶片120面向下方)。第一晶片110包含第一导电接垫111以及第一接合垫112，第一导电接垫111以及第一接合垫112设置于第一晶片110背向封装基板190的上表面113(亦即，第一晶片110面向上方，使得第一晶片110与第二晶片120呈面对面配置)。第一导电接垫111通过导电柱140电性耦接第二晶片120的第二导电接垫121，借此促成晶片间的沟通(die-to-die communication)。第一接合垫112通过接合引线130电性耦接封装基板190，借此促成晶片与封装间的沟通(die-to-package communication)。
在一些实施方式中，导电柱140为铜柱，且铜柱的宽度与高度实质上介于30微米与70微米之间。在一些实施方式中，接合引线130的材料包含金、银、铜、其他合适的导电材料或上述材料的组合。
在一些实施方式中，如图1所示，双晶片存储器封装100进一步包含晶片粘着层150(die attach film)，其设置于第一晶片110与封装基板190之间。晶片粘着层150包含粘着剂，其用以将第一晶片110附接至封装基板190的顶面。
在一些实施方式中，如图1所示，双晶片存储器封装100进一步包含成型模料160(molding compound)，其包覆第一晶片110、第二晶片120、接合引线130以及导电柱140。具体而言，成型模料160覆盖于封装基板190与第二晶片120上，并且填入形成于第一晶片110与第二晶片120之间的间隙G。成型模料160是用以保护其内的元件。
在一些实施方式中，如图1所示，双晶片存储器封装100进一步包含多个焊球170，其设置于封装基板190远离第一晶片110的一侧。焊球170是作为外部连接介面，并配置以电性耦接电路板或其他电子元件(图未示)。
在一些实施方式中，如图1所示，第一晶片110与第二晶片120具有相同的结构。第一晶片110的第一导电接垫111对应第二晶片120的第二导电接垫121，且第二晶片120进一步包含对应第一晶片110的第一接合垫112的第二接合垫122。在第一晶片110与第二晶片120具有相同的结构下，可降低双晶片存储器封装100的制造复杂程度。
在一些实施方式中，第一晶片110作为主晶片(master die)，而第二晶片120作为仆晶片(slave die)。第一晶片110的第一接合垫112为唯一的晶片与封装间通讯界面，换言之，进出堆叠的两晶片的所有传输流量皆通过第一接合垫112，而第二接合垫122不具任何功能。本发明不限于上述主仆配置，在另一些实施方式中，第二接合垫122可通过另一接合引线(图未示)电性耦接封装基板190。
在一些实施方式中，如图1所示，在垂直于第一晶片110的上表面113的方向D上，第一导电接垫111与第二导电接垫121彼此对齐。具体而言，第二导电接垫121于第一晶片110的上表面113上的垂直投影(亦即，沿方向D的投影)与第一导电接垫111完全重叠。在此等实施方式中，导电柱140位于第一导电接垫111与第二导电接垫121之间，且导电柱140的两端分别接触第一导电接垫111与第二导电接垫121。
在一些实施方式中，如图1所示，接合引线130部分延伸至第一晶片110与第二晶片120之间的间隙G内。接合引线130具有相反的两端，包含接触第一接合垫112的第一端130a以及接触封装基板190的第二端130b。第一晶片110在封装基板190上的垂直投影与接合引线130的第二端130b彼此分离，换言之，接合引线130的第二端130b是连接至封装基板190未受到第一晶片110覆盖的部分。
尽管前文中描述第一晶片110具有单一个导电接垫(即第一导电接垫111)以及单一个接合垫(即第一接合垫112)，其仅是为了描述上的方便。第一晶片110可能包含设置于上表面113的多个第一导电接垫111与多个第一接合垫112，举例而言，多个第一导电接垫111与多个第一接合垫112可能沿着垂直于图1所示的剖面的方向排列。同样地，第二晶片120可能包含对应至第一导电接垫111的多个第二导电接垫121。双晶片存储器封装100可能包含多个导电柱140，每一导电柱140将对应的第一导电接垫111电性耦接至对应的第二导电接垫121。双晶片存储器封装100可能包含多个接合引线130，每一导电柱140将对应的第一接合垫112电性耦接至封装基板190。
请参照图2，其依据本发明的另一些实施方式绘示双晶片存储器封装200的剖视示意图。双晶片存储器封装200包含封装基板190、第一晶片210、第二晶片120、接合引线230以及导电柱140，其中相同的元件符号是代表实质上等同于前文中参照图1所描述的元件，为了内容的简洁，在此不重复关于这些元件的描述。
如图2所示，在一些实施方式中，接合引线230不直接接触第一接合垫112。双晶片存储器封装200的第一晶片210进一步包含重分布层214(redistribution layer，RDL)，接合引线230是通过重分布层214电性耦接第一接合垫112。重分布层214设置于第一晶片210的上表面113。重分布层214具有相反的两端，包含电性连接第一接合垫112的第一端214a以及延伸至第一晶片210的边缘的第二端214b。接合引线230的两端分别接触重分布层214的第二端214b以及封装基板190。重分布层214的设置使得在引线接合过程中能形成较短的接合引线230(相较于双晶片存储器封装100的接合引线130)。
请参照图3，其依据本发明的另一些实施方式绘示双晶片存储器封装300的剖视示意图。双晶片存储器封装300包含封装基板190、第一晶片310、第二晶片120、接合引线130以及导电柱140，其中相同的元件符号是代表实质上等同于前文中参照图1所描述的元件，为了内容的简洁，在此不重复关于这些元件的描述。
如图3所示，在一些实施方式中，在方向D上，第一晶片110的第一导电接垫111与第二晶片120的第二导电接垫121彼此不对齐。具体而言，第一导电接垫111与第二导电接垫121不对齐是代表第二导电接垫121在第一晶片310的上表面113上的垂直投影至少部分与第一导电接垫111不重叠。在图3所示的实施方式中，第一导电接垫111相对于第二导电接垫121向左偏移。
如图3所示，为了应对第一导电接垫111与第二导电接垫121不对齐，第一晶片310进一步包含电性连接第一导电接垫111的重分布层314。重分布层314设置于第一晶片310的上表面113，并且延伸至第二导电接垫121的下方。导电柱140位于重分布层314与第二导电接垫121之间，且导电柱140的两端分别接触重分布层314以及第二导电接垫121。
请参照图4，其依据本发明的另一些实施方式绘示双晶片存储器封装400的剖视示意图。双晶片存储器封装400包含封装基板190、第一晶片110、第二晶片420、接合引线130以及导电柱140，其中相同的元件符号是代表实质上等同于前文中参照图1所描述的元件，为了内容的简洁，在此不重复关于这些元件的描述。
如图4所示，第一导电接垫111与第二导电接垫121以与图3所示的实施方式类似的方式不对齐。第二晶片420进一步包含电性连接第二导电接垫121的重分布层424。重分布层424设置于第二晶片420的下表面123，并且延伸至第一导电接垫111的上方。导电柱140位于重分布层424与第一导电接垫111之间，且导电柱140的两端分别接触重分布层424以及第一导电接垫111。
请参照图5，其依据本发明的另一些实施方式绘示双晶片存储器封装500的剖视示意图。双晶片存储器封装500包含封装基板190、第一晶片510、第二晶片520、接合引线130以及导电柱140，其中相同的元件符号是代表实质上等同于前文中参照图1所描述的元件，为了内容的简洁，在此不重复关于这些元件的描述。
如图5所示，在一些实施方式中，在方向D上，第一导电接垫111与第二导电接垫121不对齐。然而，第二导电接垫121在第一晶片510的上表面113上的垂直投影部分与第一导电接垫111重叠。第一晶片510进一步包含第一重分布层514，其设置于第一晶片510的上表面113，并且电性连接第一导电接垫111。第二晶片520进一步包含第二重分布层524，其设置于第二晶片520的下表面123，并且电性连接第二导电接垫121。第一重分布层514与第二重分布层524均向右延伸，且第一重分布层514远离第一导电接垫111的一端514a对齐第二重分布层524远离第二导电接垫121的一端524a。导电柱140位于第一重分布层514与第二重分布层524之间，且导电柱140的两端分别接触第一重分布层514的该端514a以及第二重分布层524的该端524a。
综上所述，本发明的双晶片存储器封装包含堆叠于基板上的两晶片(即上述的第一晶片与第二晶片)。两晶片的导电接垫彼此面对而使两晶片呈面对面的配置，并且两导电接垫通过设置于其间的导电柱彼此电性耦接。位于下方的第一晶片进一步包含接合垫，其通过接合引线电性耦接封装基板，借此促成晶片与封装间的沟通。上述结构配置使得三维晶片堆叠能在不需要硅穿孔下实现。
尽管已以特定实施方式详细地描述本发明，但其他实施方式亦是可能的。因此，权利要求的精神与范围不应限定于本文中所描述的实施方式。
对于所属技术领域中的技术人员而言，显然可在不脱离本发明的范围或精神下对本发明的结构进行各种修改与更动。有鉴于此，本发明旨在涵盖落入以下权利要求内的修改与更动。

Claims (17)

1.一种双晶片存储器封装，其特征在于，包含：
封装基板；
第一晶片，设置于所述封装基板上，并且包含：
第一导电接垫，设置于所述第一晶片背向所述封装基板的表面；以及
第一接合垫，设置于所述第一晶片的所述表面；
第二晶片，设置于所述第一晶片远离所述封装基板的一侧，并且包含第二导电接垫，其中所述第二导电接垫设置于所述第二晶片面向所述第一晶片的表面；
接合引线，其中所述第一接合垫通过所述接合引线电性连接所述封装基板；以及
导电柱，其中所述第一导电接垫通过所述导电柱电性连接所述第二导电接垫。
2.如权利要求1所述的双晶片存储器封装，其特征在于，所述第一导电接垫以及所述第二导电接垫在一个方向上对齐，所述方向垂直于所述第一晶片的所述表面，所述导电柱位于所述第一导电接垫以及所述第二导电接垫之间，并且接触所述第一导电接垫以及所述第二导电接垫。
3.如权利要求2所述的双晶片存储器封装，其特征在于，所述第二导电接垫在所述第一晶片的所述表面上的垂直投影与所述第一导电接垫完全重叠。
4.如权利要求1所述的双晶片存储器封装，其特征在于，所述第一导电接垫以及所述第二导电接垫在一个方向上不对齐，所述方向垂直于所述第一晶片的所述表面。
5.如权利要求4所述的双晶片存储器封装，其特征在于，所述第二导电接垫在所述第一晶片的所述表面上的垂直投影至少部分与所述第一导电接垫不重叠。
6.如权利要求4所述的双晶片存储器封装，其特征在于，所述第一晶片进一步包含重分布层，所述重分布层设置于所述第一晶片的所述表面，并且电性连接所述第一导电接垫，所述导电柱位于所述重分布层以及所述第二导电接垫之间，并且接触所述重分布层以及所述第二导电接垫。
7.如权利要求4所述的双晶片存储器封装，其特征在于，所述第二晶片进一步包含重分布层，所述重分布层设置于所述第二晶片的所述表面，并且电性连接所述第二导电接垫，所述导电柱位于所述重分布层以及所述第一导电接垫之间，并且接触所述重分布层以及所述第一导电接垫。
8.如权利要求4所述的双晶片存储器封装，其特征在于，所述第一晶片进一步包含第一重分布层，所述第一重分布层设置于所述第一晶片的所述表面，并且电性连接所述第一导电接垫，所述第二晶片进一步包含第二重分布层，所述第二重分布层设置于所述第二晶片的所述表面，并且电性连接所述第二导电接垫，所述导电柱位于所述第一重分布层以及所述第二重分布层之间，并且接触所述第一重分布层以及所述第二重分布层。
9.如权利要求8所述的双晶片存储器封装，其特征在于，所述第一重分布层远离所述第一导电接垫的一端对齐所述第二重分布层远离所述第二导电接垫的一端。
10.如权利要求8所述的双晶片存储器封装，其特征在于，所述导电柱接触所述第一重分布层远离所述第一导电接垫的一端以及所述第二重分布层远离所述第二导电接垫的一端。
11.如权利要求1所述的双晶片存储器封装，其特征在于，所述接合引线的两端分别接触所述第一接合垫以及所述封装基板。
12.如权利要求1所述的双晶片存储器封装，其特征在于，所述第一晶片进一步包含重分布层，所述重分布层设置于所述第一晶片的所述表面，并且电性连接所述第一接合垫，所述接合引线的两端分别接触所述重分布层以及所述封装基板。
13.如权利要求12所述的双晶片存储器封装，其特征在于，所述重分布层远离所述第一接合垫的一端延伸至所述第一晶片的一边缘。
14.如权利要求12所述的双晶片存储器封装，其特征在于，所述接合引线的两端分别接触所述封装基板以及所述重分布层远离所述第一接合垫的一端。
15.如权利要求1所述的双晶片存储器封装，其特征在于，所述接合引线部分延伸至形成于所述第一晶片以及所述第二晶片之间的间隙内。
16.如权利要求1所述的双晶片存储器封装，其特征在于，所述第一晶片在所述封装基板上的垂直投影与所述接合引线接触所述封装基板的一端彼此分离。
17.如权利要求1所述的双晶片存储器封装，其特征在于，所述第一导电接垫对应所述第二导电接垫，且所述第一晶片以及所述第二晶片具有相同的结构。
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