JP5215244B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5215244B2 JP5215244B2 JP2009145430A JP2009145430A JP5215244B2 JP 5215244 B2 JP5215244 B2 JP 5215244B2 JP 2009145430 A JP2009145430 A JP 2009145430A JP 2009145430 A JP2009145430 A JP 2009145430A JP 5215244 B2 JP5215244 B2 JP 5215244B2
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- semiconductor chip
- semiconductor chips
- semiconductor
- conductive
- stacked body
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2924/20751—Diameter ranges larger or equal to 10 microns less than 20 microns
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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Description
図2は、本発明の第1の実施の形態に係る半導体チップ積層体を例示する断面図である。図2を参照するに、半導体チップ積層体20Aは、配線基板51と、配線基板51上に載置されたチップ積層体52Cとを有する。チップ積層体52Cは、パッド33を含む複数の半導体チップ32と、それぞれのパッド33に接続されたボンディングワイヤ34aと、導電性部材47と、封止樹脂48とを有する。
例えば、外径が6インチ、8インチまたは12インチの半導体ウエハを準備し、バックグラインド等による薄型化を施し、さらに個々の半導体チップにダイシング(個片化)する。ダイシングを終えた半導体チップは、ダイシングテープ上に置かれている。
工程a.において、S100で準備した個々の半導体チップを、ダイシングテープからピックアップして、仮接着フィルム上に載置する。仮接着フィルムの材質としては、例えば、ポリエステルフィルムを使用することができる。
個々の半導体チップ32を前出の図5又は図7で示した仮接着フィルム31上から剥離し、ボンディングワイヤ34aを有する半導体チップ32の背面41bに絶縁樹脂42を塗布する。絶縁樹脂42の塗布は、周知のスクリーン印刷法、スピンコート法またはフィルム状シートの貼り付け等により行うことができる。
図8は、ボンディングワイヤ34a及び絶縁樹脂42を有する半導体チップ32が、配線基板51上に載置され、全体としてチップ積層体52Aが形成された状態を示している。個々の半導体チップをピックアップして、チップ積層を行うが、チップ積層体52Aの形成のためには、ダイマウント装置またはフリップチップマウンタ装置を使用し、半導体チップのアライメントと固定を行う。チップ積層体の配線基板への搭載における絶縁樹脂による固定は、例えば、150℃の温度で30分の温度条件により行う。
図9は、半導体チップ32の有するボンディングワイヤ34aの端部が、導電性部材47により配線基板51上の接続端子61と導電接続され、全体としてチップ積層体52Bが形成された状態を示している。前出の図8において積層された半導体チップ32の側面から突出する各ボンディングワイヤ34aの端部は、導電性部材47により配線基板51の接続端子61と導電接続されている。導電性部材47としては、例えば、高粘度でチクソ性を有する銀ペーストやはんだ等を使用することができる。
図9に示す積層体・基板接続工程の後に、チップ積層体、接続端子と接続された導電性連結材及び配線基板について、その全体または一部を封止樹脂48により封止することにより、図2に示す半導体チップ積層体20Aが完成する。
各々の半導体チップに接続されたボンディングワイヤを、導電性部材により配線基板の接続端子と導電接続する際に、各々の半導体チップの側面と導電性部材との間に所定の間隔を空けるようにする。その結果、各々の半導体チップの側面に絶縁膜を形成する工程が不要となり、半導体チップ積層体の形成工程を簡素化して、生産性の向上を図ることができる。
図10は、本発明の第2の実施の形態に係る半導体チップ積層体を例示する断面図である。同図中、図2と同一の構成部分については同一符号を付し、その説明を省略する場合がある。
第1の実施の形態と同様の効果を奏するが、更に以下の効果を奏する。すなわち、半導体チップ積層体に搭載できる半導体チップの種類を増やすことができる。
図11は、本発明の第3の実施の形態に係る半導体チップ積層体を例示する断面図である。同図中、図2と同一の構成部分については同一符号を付し、その説明を省略する場合がある。
第1の実施の形態と同様の効果を奏するが、更に以下の効果を奏する。すなわち、半導体チップ積層体において、ボンディングワイヤの長さを調整することにより、チップサイズが異なる半導体チップを積層することができる。
図12は、本発明の第4の実施の形態に係る半導体チップ積層体を例示する断面図である。同図中、図2と同一の構成部分については同一符号を付し、その説明を省略する場合がある。
第1の実施の形態と同様の効果を奏するが、更に以下の効果を奏する。すなわち、図4又は図6に示す工程と同一工程において、各々の半導体チップの集積回路面側に絶縁樹脂を塗布することができるため、半導体チップ積層体の形成工程を簡素化して、生産性の向上を図ることができる。
図13は、本発明の第5の実施の形態に係る半導体チップ積層体を例示する断面図である。同図中、図2と同一の構成部分については同一符号を付し、その説明を省略する場合がある。
第1の実施の形態と同様の効果を奏するが、更に以下の効果を奏する。すなわち、例えば、KGD(Known Good Die)としてのメモリとロジックの複合した半導体チップの積層体等を構成することができるので、半導体パッケージの設計において、半導体チップ積層体の形態を利用できる半導体チップの範囲を拡大することができる。そして、半導体チップの積層体をコンパクトな形態にすることができるので、さらに性能の向上を図ることができる。
以上、本発明の好ましい実施の形態について詳説したが、本発明は、上述した実施の形態に制限されることはなく、本発明の範囲を逸脱することなく、上述した実施の形態に種々の変形及び置換を加えることができる。
31 仮接着フィルム
32、32A、32B、32C、32D 半導体チップ
33 パッド
34、34a、34b、34c ボンディングワイヤ
35 間隙
36 導電性連結材
37 切断箇所
41a 集積回路面
41b 背面
42、46 絶縁樹脂
47 導電性部材
48 封止樹脂
49 シリンジ
51 配線基板
52A、52B、52C、52D、52E、52F、52G チップ積層体
61 接続端子
70 ボンディングツール
71 底面部
72、73 溝
74 孔部
81 パッド
82 バンプ
83 接続端子
84 絶縁樹脂
h1、h2 深さ
θ1,θ2 開口角度
W1 間隔
Claims (5)
- 接続端子を有する配線基板と、
前記配線基板上に積層された、パッドを有する複数の半導体チップと、
一方の端部が前記複数の半導体チップの前記パッドと接続され、他方の端部が前記複数の半導体チップの側面から突出する導電性連結材と、
前記複数の半導体チップにおける前記導電性連結材の前記他方の端部と前記配線基板の前記接続端子とを接続する導電性部材と、を有し、
前記複数の半導体チップの側面には前記複数の半導体チップの各々を構成する導電性材料が露出しており、前記複数の半導体チップの側面と前記導電性部材との間には間隙が設けられ、
前記導電性部材は、導電性ペースト、又は、はんだの何れか一の材料であり、
前記複数の半導体チップ、前記導電性連結材、前記導電性部材、及び前記間隙は、同一の封止樹脂により覆われている半導体チップ積層体。 - 前記配線基板上に積層された前記複数の半導体チップのうち、隣接する半導体チップにおいて、前記導電性連結材の前記他方の端部が異なる方向に突出している請求項1記載の半導体チップ積層体。
- 前記配線基板上に積層された前記複数の半導体チップのうち、少なくとも1つの半導体チップは、他の半導体チップと大きさが異なる請求項1又は2記載の半導体チップ積層体。
- 前記配線基板上に積層された前記複数の半導体チップのうち、前記配線基板に対向する半導体チップは、前記配線基板とフリップチップ接続されている請求項1乃至3の何れか一項記載の半導体チップ積層体。
- 前記導電性部材は、チクソ性を有する材料である請求項1乃至4の何れか一項記載の半導体チップ積層体。
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JP2009145430A JP5215244B2 (ja) | 2009-06-18 | 2009-06-18 | 半導体装置 |
US12/768,938 US8058717B2 (en) | 2009-06-18 | 2010-04-28 | Laminated body of semiconductor chips including pads mutually connected to conductive member |
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