CN112530880B - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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CN112530880B
CN112530880B CN202010047872.9A CN202010047872A CN112530880B CN 112530880 B CN112530880 B CN 112530880B CN 202010047872 A CN202010047872 A CN 202010047872A CN 112530880 B CN112530880 B CN 112530880B
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CN112530880A (zh
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三浦正幸
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Kioxia Corp
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Kioxia Corp
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Abstract

本实施方式涉及一种半导体装置及半导体装置的制造方法。根据一实施方式，于半导体装置中，基板具有主面。控制芯片具有第1正面及第1背面。控制芯片在第1正面与主面对面的状态下介隔多个凸块电极安装在主面。第1间隔片具有第2正面及第2背面。第1间隔片的第2背面安装在主面。第1间隔片的第2正面距主面的高度为第1背面距主面的高度的上限与下限之间的范围内。第2间隔片具有第3正面及第3背面。第2间隔片的第3背面安装在主面。第2间隔片的第3正面距主面的高度为第1背面距主面的高度的上限与下限之间的范围内。

Description

半导体装置及半导体装置的制造方法
相关申请案的引用
本申请案基于2019年09月17日提出申请的现有的日本专利申请案第2019-168746号的优先权的利益，且谋求其利益，其整体内容通过引用而包含在此。
技术领域
本实施方式涉及一种半导体装置及半导体装置的制造方法。
背景技术
于半导体装置中，在基板的主面安装半导体芯片及间隔片，在间隔片之上安装其它多个半导体芯片，构成间隔片构造的安装形态。此时，较理想为适当地构成间隔片构造的安装形态。
发明内容
一实施方式的目的在于提供一种能够适当地构成间隔片构造的安装形态的半导体装置及半导体装置的制造方法。
根据一实施方式，提供一种具有基板、控制芯片、第1间隔片及第2间隔片的半导体装置。基板具有主面。控制芯片具有第1正面及第1背面。控制芯片在第1正面与主面对面的状态下介隔多个凸块电极安装在主面。第1间隔片具有第2正面及第2背面。第1间隔片的第2背面安装在主面。第1间隔片的第2正面距主面的高度为第1背面距主面的高度的上限与下限之间的范围内。第2间隔片具有第3正面及第3背面。第2间隔片的第3背面安装在主面。第2间隔片的第3正面距主面的高度为第1背面距主面的高度的上限与下限之间的范围内。
附图说明
图1是表示第1实施方式的半导体装置的构成的截面图。
图2是表示第1实施方式的间隔片及控制芯片的高度的放大截面图。
图3是表示第1实施方式的间隔片及控制芯片的高度的放大截面图。
图4是表示第1实施方式的第1变化例中的间隔片及控制芯片的布局构成的俯视图。
图5是表示第1实施方式的第1变化例中的间隔片、控制芯片及存储芯片的积层构成的截面图。
图6是表示第1实施方式的第2变化例中的间隔片及控制芯片的布局构成的俯视图。
图7是表示第1实施方式的第3变化例中的间隔片及控制芯片的布局构成的俯视图。
图8是表示第1实施方式的第3变化例中的间隔片、控制芯片及存储芯片的积层构成的截面图。
图9是表示第1实施方式的第4变化例中的间隔片、控制芯片及存储芯片的积层构成的截面图。
图10(a)～(d)是表示第2实施方式的半导体装置的制造方法的步骤截面图。
图11是表示第2实施方式的变化例中的间隔片及控制芯片的高度的放大截面图。
图12是表示第2实施方式的变化例中的间隔片及控制芯片的高度的放大截面图。
具体实施方式
以下，参照附图详细地对实施方式的半导体装置进行说明。此外，本发明并不受这些实施方式限定。
(第1实施方式)第1实施方式的半导体装置为了满足SIP(System In Package，系统级封装)的要求，存在采用混载有控制芯片及多个存储芯片的多芯片模块构成的情况。于多芯片模块构成中，控制芯片根据高速化、低耗电化的要求而将芯片面积抑制得较小，相对于此，存储芯片根据大容量化的要求而倾向于增大芯片面积。于半导体装置中，根据小型安装化的要求，可采用如下间隔片构造，即，以间隔片填埋控制芯片及存储芯片间的面积差，并且将多个芯片上下重叠而积层配置。
例如，在基板的面积最大的面(主面)以引线接合方式面朝上安装控制芯片，并且在其周边安装多个间隔片，多个存储芯片经由粘接膜积层在控制芯片及间隔片之上，并以引线接合方式面朝上安装在基板。将该间隔片构造称为面朝上安装+面朝上安装的间隔片构造。
在面朝上安装+面朝上安装的间隔片构造中，需要在控制芯片与最下的存储芯片之间确保用于控制芯片的接合线的间隙空间。因此，从用来安装规定片数的存储芯片的基板到最上的存储芯片的安装高度容易变高。
或者，在基板的主面以倒装芯片方式面朝下安装控制芯片，并且在其周边安装多个间隔片，多个存储芯片经由粘接膜积层在控制芯片及间隔片之上，并以引线接合方式面朝上安装在基板。将该间隔片构造称为面朝下安装+面朝上安装的间隔片构造。
在面朝下安装+面朝上安装的间隔片构造中，在控制芯片与最下的存储芯片之间不需要用于控制芯片的接合线的间隙空间。因此，面朝下安装+面朝上安装的间隔片构造与面朝上安装+面朝上安装的间隔片构造相比，能够降低从用来安装规定片数的存储芯片的基板到最上的存储芯片的安装高度。
在面朝下安装+面朝上安装的间隔片构造的半导体装置中，如果根据进一步小型安装化的要求而将控制芯片薄型化，那么存在控制芯片受安装时的热变形等影响而弯曲的情况。此时，如果基板上的控制芯片的背面与间隔片的正面的高度差较大，那么为了吸收该高度差而应积层在其之上的粘接膜大幅变厚，从基板到最上的存储芯片的安装高度有变高的可能性。
于此，本实施方式中，于面朝下安装+面朝上安装的间隔片构造的半导体装置中，通过将各间隔片距基板的主面的高度构成为控制芯片的高度的上限与下限之间的范围内，而实现粘接膜的薄膜化及由此带来的安装高度的降低。
具体而言，半导体装置1可如图1所示一样构成。图1是表示半导体装置1的构成的图。
半导体装置1具有基板10、控制芯片20、多个存储芯片40-1～40-8、密封树脂50、外部电极60、多个间隔片70-1～70-2、及多个粘接膜30-1～30-10。以下，将垂直于基板10的面积最大的面中的一个(正面10a、第1主面)的方向设为Z方向，将在垂直于Z方向的平面内相互正交的2个方向设为X方向及Y方向。
在半导体装置1中，在基板10之上依次积层控制芯片20及多个存储芯片40-1～40-8，在多个存储芯片40-1～40-8中的最下的存储芯片40-1与基板10之间的控制芯片20的侧方配置多个间隔片70-1～70-2。控制芯片20以面朝下状态倒装芯片安装在基板10，多个存储芯片40-1～40-8以面朝上状态引线接合安装在基板10。由此，构成面朝下安装+面朝上安装的间隔片构造。
基板10在+Z侧具有正面(主面)10a，在-Z侧具有背面10b。在基板10的正面10a分别安装有控制芯片20、多个间隔片70-1～70-2、多个存储芯片40-1～40-8、及多个粘接膜30-1～30-10，在基板10的背面10b安装有外部电极60。安装在基板10的正面10a侧的控制芯片20、多个间隔片70-1～70-2、多个存储芯片40-1～40-8、及多个粘接膜30-1～30-10利用密封树脂50密封。密封树脂50由以绝缘物为主成分的材料形成，例如可由以具有绝缘性、热塑性的第1树脂为主成分的材料形成。安装在基板10的背面10b侧的外部电极60可由以导电物为主成分的材料形成，并且其表面露出，可从外部电连接。
基板10具有阻焊剂层11、预浸料层12、核心层13、导电层14、及通孔电极15。阻焊剂层11可由以绝缘物(例如，绝缘性有机系物质)为主成分的材料形成。预浸料层12可由以绝缘物(例如，绝缘性树脂)为主成分的材料形成。核心层13可由以绝缘物(例如，绝缘性树脂)为主成分的材料形成。导电层14可由以导电物(例如，铜)为主成分的材料形成。通孔电极15可由以导电物(例如，铜)为主成分的材料形成。
控制芯片20在-Z侧具有正面20a，在+Z侧具有背面20b。控制芯片20能够以倒装芯片方式安装在基板10。控制芯片20的正面20a与基板10的正面10a对面。控制芯片20介隔多个凸块电极21以面朝下方式(倒装芯片方式)安装在基板10的正面10a。即，控制芯片20在正面20a与基板10的正面10a对面的状态下介隔多个凸块电极21安装在基板10的正面10a。隔于控制芯片20及基板10间的空间中的多个凸块电极21之间的间隙由粘接树脂(底部填充胶)22填满。
控制芯片20主要由以半导体(例如，硅)为主成分的材料形成。凸块电极21由以金属(例如，铜)为主成分的材料形成。粘接树脂22由以绝缘物为主成分的材料形成，例如可由以具有绝缘性、粘接性的第2树脂为主成分的材料(例如，以环氧树脂为主成分的材料)形成。
例如，如图2、图3所示，控制芯片20的背面20b由于安装时的热变形等影响而以向+Z侧凸出的方式弯曲。图2、图3是表示间隔片70及控制芯片20的高度的放大截面图。关于控制芯片20的背面20b距基板10的正面10a的高度，具有上限高度H20b_max及下限高度H20b_min。背面20b在Y方向的中央附近的部位具有上限高度H20b_max，在+Y侧的端部及-Y侧的端部具有下限高度H20b_min。
此外，于图2、图3中，例示基板10平坦的情况，但在基板10自身因安装时的热变形等影响而弯曲的情况下，距基板10的正面10a的高度的基准可采用正面10a的安装控制芯片20的部位的Z位置。
图1所示的粘接膜30-1覆盖基板10的正面10a，供积层间隔片70-1。粘接膜30-1配置在控制芯片20的周边，例如配置在控制芯片20的-Y侧。粘接膜30-1作为将间隔片70-1粘接在基板10的正面10a的媒介。粘接膜30-1也称为DAF(Die Attach Film，芯片粘接膜)或DBF(Die Bonding Film，芯片接合膜)。
间隔片70-1具有正面70a及背面70b。间隔片70-1的背面70b经由粘接膜30-1安装在基板10的正面10a，经由粘接膜30-3在正面70a积层存储芯片40-1。间隔片70-1可由具有足以经由粘接膜30-3将存储芯片40-1支撑在基板10的+Z侧的强度的材料形成。间隔片70-1可由以半导体(例如，硅)为主成分的材料形成，也可由以树脂(例如，聚酰亚胺树脂)为主成分的材料形成。
例如，如图2所示，间隔片70-1的正面70a距基板10的正面10a的高度H70a1为上限高度H20b_max与下限高度H20b_min之间的范围内。由此，间隔片70-1的高度可视作与控制芯片20的高度大致一致。
图1所示的粘接膜30-2覆盖基板10的正面10a，供积层间隔片70-2。粘接膜30-2配置在控制芯片20的周边，例如配置在控制芯片20的+Y侧。粘接膜30-2作为将间隔片70-2粘接在基板10的正面10a的媒介。粘接膜30-2也称为DAF(Die Attach Film)或DBF(DieBonding Film)。
间隔片70-2具有正面70a及背面70b。间隔片70-2的背面70b经由粘接膜30-2安装在基板10的正面10a，经由粘接膜30-2在正面70a积层存储芯片40-1。间隔片70-2可由具有足以经由粘接膜30-3将存储芯片40-1支撑在基板10的+Z侧的强度的材料形成。间隔片70-2可由以半导体(例如，硅)为主成分的材料形成，也可由以树脂(例如，聚酰亚胺树脂)为主成分的材料形成。
例如，如图3所示，间隔片70-2的正面70a距基板10的正面10a的高度H70a2为上限高度H20b_max与下限高度H20b_min之间的范围内。由此，间隔片70-2的高度可视作与控制芯片20的高度大致一致。间隔片70-2的高度也可与间隔片70-1的高度均等。
图1所示的粘接膜30-3覆盖控制芯片20的背面20b，覆盖间隔片70-1的正面70a，覆盖间隔片70-2的正面70a，供积层存储芯片40-1。粘接膜30-3配置在控制芯片20及多个间隔片70-1、70-2与存储芯片40-1之间。粘接膜30-3将存储芯片40-1粘接在控制芯片20及多个间隔片70-1、70-2，也称为DAF(Die Attach Film)或DBF(Die Bonding Film)。
例如，如图2、图3所示，间隔片70-1的高度可视作与控制芯片20的高度大致一致，间隔片70-2的高度可视作与控制芯片20的高度大致一致，因此，可容易地使粘接膜30-3的厚度变薄。例如，粘接膜30-3的厚度也可为控制芯片20的上限高度H20b_max与下限高度H20b_min的差(ΔH20b＝H20b_max－H20b_min)加上特定的厚度裕度而得的尺寸。
多个存储芯片40-1～40-8积层在控制芯片20及多个间隔片70-1、70-2的+Z侧。存储芯片40-1～40-8跨及控制芯片20及至少1个间隔片70而配置。于图1中，例示存储芯片40-1～40-8跨及控制芯片20及2个间隔片70而配置的构成。于多个存储芯片40-1～40-8之间介置粘接膜30-4～30-10，经由粘接膜30-4～30-10相互粘接。
各存储芯片40-1～40-8具有正面及背面。各存储芯片40-1～40-8中，背面粘接在粘接膜30，在正面配置有电极垫。各存储芯片40-1～40-8主要由以半导体(例如，硅)为主成分的材料形成。
多个存储芯片40-1～40-8可分别以引线接合方式安装在基板10。此时，基板10中的导电层14在正面(+Z侧的主面)10a上具有多个电极图案，各存储芯片40-1～40-8的电极垫可经由接合线41电连接于基板10的正面上的电极图案。由此，多个存储芯片40-1～40-8可通过引线接合方式以间隔片构造安装在基板10。
于半导体装置1中，比较各粘接膜30-1～30-10的厚度，如图1所示，粘接膜30-3的厚度与粘接膜30-1及粘接膜30-2的厚度相同或较其稍厚。粘接膜30-3的厚度与粘接膜30-4～30-10的厚度相同或较其稍厚。即，如果能够将粘接膜30-3的厚度薄膜化至与多个存储芯片40-1～40-8间的各粘接膜30-4～30-10的厚度相同的程度，那么能够容易地降低半导体装置1的安装高度。
此外，各粘接膜30-1～30-10由以绝缘物为主成分的材料形成，例如可由以具有绝缘性、粘接性的第3树脂为主成分的材料(例如，包含丙烯酸聚合物及环氧树脂的材料)形成。
如上所述，第1实施方式中，于面朝下安装+面朝上安装的间隔片构造的半导体装置1中，将各间隔片70-1、70-2距基板10的正面10a的高度构成为控制芯片20的高度的上限与下限之间的范围内。由此，能够容易地将粘接膜30-3薄膜化，因此，能够容易地降低半导体装置1的安装高度。
此外，控制芯片20也可以向-Z侧凸出的方式弯曲。即便在此情况下，通过将各间隔片70-1、70-2距基板10的正面10a的高度构成为控制芯片20的高度的上限与下限之间的范围内，能够实现与实施方式相同的效果。
或者，于半导体装置1i中，多个间隔片70i-1、70i-2也可如图4所示一样布局。图4是表示第1实施方式的第1变化例中的间隔片70i-1、70i-2及控制芯片20i的布局构成的俯视图。
控制芯片20i在XY俯视下配置在包含基板10的正面10a的中心的区域。间隔片70i-1、70i-2的面积相互均等。间隔片70i-1配置在控制芯片20i的-X侧。间隔片70i-2配置在控制芯片20i的+X侧。
此时，如图5所示，多个存储芯片40i-1、40i-2也可经由粘接膜30i-3、30i-4积层在间隔片70i-1及控制芯片20i的+Z侧。多个存储芯片40i-3、40i-4也可经由粘接膜30i-5、30i-6积层在间隔片70i-2及控制芯片20i的+Z侧。图5是表示第1实施方式的第1变化例中的间隔片70i-1、70i-2、控制芯片20i及存储芯片40i-1～40i-4的积层构成的截面图，表示相当于沿着图4的A-A线切割的情况的截面。图5中，为了简略化，省略接合线的图示。
间隔片70i-1可由具有足以经由粘接膜30i-3支撑存储芯片40i-1的强度的材料形成。间隔片70i-1可由以半导体(例如，硅)为主成分的材料形成，也可由以树脂(例如，聚酰亚胺树脂)为主成分的材料形成。间隔片70i-2可由具有足以经由粘接膜30i-5支撑存储芯片40i-3的强度的材料形成。间隔片70i-2可由以半导体(例如，硅)为主成分的材料形成，也可由以树脂(例如，聚酰亚胺树脂)为主成分的材料形成。
各存储芯片40i-1～40i-4经由接合线电连接于图4所示的基板10的正面10a上的多个电极图案101-1～101-2k(k为任意的2以上的整数)。于XY俯视下，间隔片70i-1配置在多个电极图案101-1～101-k与控制芯片20i之间。间隔片70i-2配置在多个电极图案101-(k+1)～101-2k与控制芯片20i之间。
控制芯片20i例如具有矩形的外形，具有4边20i1～20i4。边20i1在Y方向上延伸，相对于边20i2在X方向上隔开并且相向，在±Y方向的两端与边20i3、20i4交叉。边20i2在Y方向上延伸，相对于边20i1在X方向上隔开并且相向，在±Y方向的两端与边20i3、20i4交叉。边20i3在X方向上延伸，相对于边20i4在Y方向上隔开并且相向，在±X方向的两端与边20i2、20i1交叉。边20i4在X方向上延伸，相对于边20i3在Y方向上隔开并且相向，在±X方向的两端与边20i2、20i1交叉。
间隔片70i-1以与边20i1并排的方式配置。间隔片70i-1具有以沿着Y方向的方向为长边方向的矩形的外形，沿着边20i1延伸。间隔片70i-2以与边20i2并排的方式配置。间隔片70i-2具有以沿着Y方向的方向为长边方向的矩形的外形，沿着边20i2延伸。间隔片70i-1及间隔片70i-2的外形尺寸也可相互均等。可将间隔片70i-1及间隔片70i-2的面积设为相互均等。
这样，于半导体装置1i中，由于能够将间隔片70i-1及间隔片70i-2的面积设为相互均等，因此能够提高间隔片70i-1及间隔片70i-2的材料(例如，硅等半导体)的使用效率。
另外，通过将间隔片70i-1及间隔片70i-2的外形尺寸设为相互均等，能够减少间隔片70i-1及间隔片70i-2的厚度的不均，就该观点而言，由于能够将粘接膜30i-3、30i-5的厚度薄膜化，因此能够容易地降低半导体装置1i的安装高度。
或者，于半导体装置1j中，多个间隔片70j-1～70j-4也可如图6所示一样布局。图6是表示第1实施方式的第2变化例中的间隔片70j-1～70j-4及控制芯片20i的布局构成的俯视图。
多个间隔片70j-1～70j-4的面积相互均等。多个间隔片70j-1～70j-4的外形尺寸也可相互均等。间隔片70j-1及间隔片70j-3配置在控制芯片20i的-X侧。间隔片70j-2及间隔片70j-4配置在控制芯片20i的+X侧。
间隔片70j-1及间隔片70j-3是将间隔片70i-1(参照图4)的Y方向的中央附近的部分去除而进行2分割所得。由于在Y方向上的间隔片70j-1及间隔片70j-3之间存在间隙的空间，因此，于制造半导体装置1j时，能够容易地经由该间隙将密封树脂50填满间隔片70j-1及间隔片70j-3与控制芯片20i之间的空间。
间隔片70j-2及间隔片70j-4是将间隔片70i-2(参照图4)的Y方向的中央附近的部分去除而进行2分割所得。由于在Y方向的间隔片70j-2及间隔片70j-4之间存在间隙的空间，因此，于制造半导体装置1j时，能够容易地经由该间隙将密封树脂50填满间隔片70j-1及间隔片70j-3与控制芯片20i之间的空间。
此时，间隔片70j-1～70j-4、控制芯片20i及存储芯片40i-1～40i-4的积层构成也可与图5相同。
这样，于半导体装置1j中，由于能够将间隔片70j-1～70j-4的面积设为相互均等，因此能够提高间隔片70j-1～70j-4的材料的使用效率。
另外，通过将间隔片70j-1～70j-4的外形尺寸设为相互均等，能够减少间隔片70j-1～70j-4的厚度的不均，就该观点而言，由于能够将粘接膜30i-3、30i-5的厚度薄膜化，因此能够容易地降低半导体装置1j的安装高度。
或者，于半导体装置1k中，多个间隔片70k-1～70k-5也可如图7所示一样布局。图7是表示第1实施方式的第3变化例中的间隔片70k-1～70k-5及控制芯片20i的布局构成的俯视图。
控制芯片20i在XY俯视下配置在包含基板10的正面10a的中心的区域。间隔片70k-1～70k-5的面积相互均等。间隔片70k-1配置在控制芯片20i的-X侧。间隔片70k-2配置在控制芯片20i的+X侧。间隔片70k-3配置在控制芯片20i的+X侧，并配置在间隔片70k-2的+Y侧。间隔片70k-4配置在控制芯片20i的-Y侧。间隔片70k-5配置在控制芯片20i的+Y侧。
此时，如图8所示，多个存储芯片40k-1～40k-4也可经由粘接膜30k-6～30k-9积层在间隔片70k-1～70k-5及控制芯片20i的+Z侧。此外，各间隔片70k-1～70k-5经由粘接膜30k-1～30k-5配置在基板这一点与实施方式相同。图8是表示第1实施方式的第3变化例中的间隔片70k-1～70k-5、控制芯片20i及存储芯片40k-1～40k-4的积层构成的截面图，表示相当于沿着图7的B-B线切割的情况的截面。图8中，为了简略化，省略接合线的图示。
各间隔片70k-1～70k-5可由具有足以经由粘接膜30k-6支撑存储芯片40k-1的强度的材料形成。各间隔片70k-1～70k-5可由以半导体(例如，硅)为主成分的材料形成，也可由以树脂(例如，聚酰亚胺树脂)为主成分的材料形成。
各存储芯片40k-1～40k-4经由接合线电连接于图7所示的基板10的正面10a上的多个电极图案101-1～101-2k(k为任意的2以上的整数)。于XY俯视下，间隔片70k-1配置在多个电极图案101-1～101-k与控制芯片20i之间。间隔片70k-2、70k-3分别配置在多个电极图案101-(k+1)～101-2k与控制芯片20i之间。间隔片70k-4在控制芯片20i的-Y侧配置在多个电极图案101-1～101-k与多个电极图案101-(k+1)～101-2k之间。间隔片70k-5在控制芯片20i的+Y侧配置在多个电极图案101-1～101-k与多个电极图案101-(k+1)～101-2k之间。
间隔片70k-1以与控制芯片20i的边20i1并排的方式配置。间隔片70k-1具有以沿着Y方向的方向为长边方向的矩形的外形，沿着边20i1延伸。间隔片70k-2、70k-3分别以与边20i2并排的方式配置。间隔片70k-2、70k-3具有以沿着Y方向的方向为长边方向的矩形的外形，沿着边20i2延伸。间隔片70k-4以与边20i4并排的方式配置。间隔片70k-4具有以沿着X方向的方向为长边方向的矩形的外形，沿着边20i4延伸。间隔片70k-5以与边20i3并排的方式配置。间隔片70k-5具有以沿着X方向的方向为长边方向的矩形的外形，沿着边20i3延伸。
间隔片70k-1～70k-5的外形尺寸也可相互均等。可将间隔片70k-1～70k-5的面积设为相互均等。
这样，在半导体装置1k中，由于能够将间隔片70k-1～70k-5的面积设为相互均等，因此能够提高间隔片70k-1～70k-5的材料(例如，硅等半导体)的使用效率。
另外，通过将间隔片70k-1～70k-5的外形尺寸设为相互均等，能够减少间隔片70k-1～70k-5的厚度的不均，就该观点而言，由于能够将粘接膜30k-6的厚度薄膜化，因此能够容易地降低半导体装置1k的安装高度。
或者，在半导体装置1n中，如图9所示，也可在控制芯片20n的背面20bn配置间隔片90n。图9是表示第1实施方式的第4变化例中的间隔片70i-1、70i-2、90n、控制芯片20n及存储芯片40i-1～40i-4的积层构成的截面图，表示相当于沿着图4的A-A线切割的情况的截面。图9中，为了简略化，省略接合线的图示。间隔片90n由能够减小控制芯片20n的背面20bn与密封树脂50的热膨胀率差的材料(例如，具有半导体与第1树脂的中间热膨胀率的材料、或能够减小因热膨胀率差而产生的应力的材料)形成，例如可由以聚酰亚胺树脂为主成分的材料形成。间隔片90n与控制芯片20n的背面20bn通过未图示的粘接膜而粘接。多个存储芯片40i-1、40i-2经由粘接膜30i-3、30i-4积层在间隔片70i-1及间隔片90n的+Z侧。
于半导体装置1n的制造步骤中，间隔片90n贴附在包含单片化前的控制芯片20n的晶片，其后，间隔片90n及控制芯片20n作为一体进行单片化，其后，间隔片90n及控制芯片20n作为一体安装在基板10。因此，作为图2、图3所示的下限高度H20b_min、上限高度H20b_max，可设为间隔片90n及控制芯片20n成为一体的构件的+Z侧的面(即，间隔片90n的+Z侧的面)的高度。
在图5的构成中，控制芯片20i的背面20bi与密封树脂50的密接力较小，存在密封后密封树脂50从背面20bi剥离的可能性。
相对于此，在图9的构成中，能够经由间隔片90n提高控制芯片20n的背面20bn与密封树脂50的密接性，能够抑制密封后密封树脂50从背面20bi侧(间隔片90n的+Z侧的面)剥离。
(第2实施方式)对第2实施方式的半导体装置进行说明。以下，以与第1实施方式不同的部分为中心进行说明。
于第1实施方式中，半导体装置1的制造方法无特别限定。
例如，于制造半导体装置1时，介隔多个凸块电极将控制芯片20安装(mount)在基板10，并且在将底部填充胶填充到多个凸块电极的间隙后安装(mount)间隔片70。
在安装控制芯片20时，在填充粘接树脂22后，粘接树脂22的熔融片(Bleed)有时在控制芯片20的周围流出。其后，如果在熔融片(Bleed)上安装间隔片70，那么有间隔片70向基板10的密接性劣化而剥离的担忧。当间隔片70剥离时，由此会导致对其它芯片施加应力等，因而存在如下可能性，即，存储芯片的电极垫与基板上的电极图案之间的接合线的电连接路径中的任一者因断线及/或剥离等被阻断等，产生电连接不良。
另外，根据熔融片(Bleed)的厚度，高度方向的不均可能增大。即，基板10上的控制芯片20的上表面与间隔片70的上表面的高度差变大，为了吸收该高度差而应积层在其上的粘接膜30大幅变厚，从基板10到最上的存储芯片40的安装高度有变高的可能性。
于此，于第2实施方式中，如图10所示，在半导体装置1的制造方法中，通过在基板10上安装间隔片70后安装控制芯片20，抑制粘接树脂22的熔融片(Bleed)介置于间隔片70与基板10之间。图10是表示第2实施方式的半导体装置1的制造方法的步骤截面图。
在图10(a)的步骤中，在基板10的正面10a的应安装间隔片70-1、70-2的区域配置粘接膜30-1、30-2。然后，在粘接膜30-1、30-2的+Z侧配置间隔片70-1、70-2。由此，间隔片70-1、70-2经由粘接膜30-1、30-2粘接安装(mount)在基板10的正面10a。
于图10(b)的步骤中，在基板10的正面10a的间隔片70-1、70-2之间的区域，介隔多个凸块电极21配置控制芯片20。此时，在控制芯片20的正面20a与基板10的正面10a对向的状态下，在基板10的正面10a配置控制芯片20。然后，在基板10的正面10a与控制芯片20的正面20a之间的多个凸块电极21的间隙填充粘接树脂22。其后，多个凸块电极21经由基板10被加热至第1温度并在某种程度上熔融。
此时，虽然存在流出粘接树脂22的熔融片(Bleed)22a的可能性，但由于间隔片70已经经由粘接膜30安装在基板10的正面10a，因此，间隔片70与基板10之间未介置粘接树脂22的熔融片(Bleed)。
于图10(c)的步骤中，接合头210对控制芯片20的背面20b加压，多个凸块电极21压抵于基板10的正面10a上的电极。与此同时，多个凸块电极21经由基板10被加热至高于第1温度的第2温度而与正面10a上的电极接合。
此时，第2温度也可设为高于粘接树脂22的玻璃转移点的温度。如果将粘接树脂22加热至低于玻璃转移点的温度，那么存在粘接树脂22热缩而使基板10弯曲的可能性。另一方面，如果将粘接树脂22加热至高于玻璃转移点的温度，那么粘接树脂22成为非晶状态而能够释放热缩的应力，因此能够将基板10恢复至平坦。
在图10(d)的步骤中，在控制芯片20及间隔片70-1、70-2的+Z侧配置粘接膜30-3。然后，在粘接膜30-3的+Z侧配置存储芯片40-1。由此，存储芯片40-1经由粘接膜30-3粘接安装(mount)在控制芯片20及间隔片70-1、70-2的+Z侧。
其后，存储芯片40-2～40-8经由粘接膜30-4～30-10粘接安装(mount)在更+Z侧。由此，能够获得图1所示的半导体装置1。
如上所述，于第2实施方式中，将间隔片70安装在基板10的正面10a，其后，将控制芯片20安装在基板10的正面10a。由此，能够抑制粘接树脂22的熔融片(Bleed)介置于间隔片70与基板10之间，因此能够抑制电连接不良，能够容易地降低半导体装置1的安装高度。
此外，在图10(a)、图10(b)的步骤中，将各间隔片70距基板10的主面10a的高度构成为控制芯片20的高度的上限与下限之间的范围内。因此，在图10(c)的步骤中，存在接合头210无法对控制芯片20的背面20b的低于间隔片70的正面70a的部分加压的可能性，从而存在凸块电极21与基板10的正面10a上的电极的接合不充分的可能性。
考虑到这一点，在半导体装置中，也可将各间隔片距基板的主面的高度构成为低于控制芯片的高度的下限。
例如，也可如图11、图12所示一样构成间隔片70p-1、70p-2。图11是表示第2实施方式的变化例中的间隔片70p-1及控制芯片20的高度的放大截面图。图12是表示第2实施方式的变化例中的间隔片70p-2及控制芯片20的高度的放大截面图。间隔片70p-1的正面70ap距基板10的正面10a的高度H70ap1低于控制芯片20的背面20b的下限高度H20b_min。间隔片70p-2的正面70ap距基板10的正面10a的高度H70ap2低于控制芯片20的背面20b的下限高度H20b_min。由此，在图10(c)的步骤中，接合头210能够容易地对控制芯片20的背面20b加压。
此时，下限高度H20b_min及高度H70ap2的差也可小于上限高度H20b_max及下限高度H20b_min的差。即，以下数式1也可成立。H20b_min－H70ap2＜H20b_max－H20b_min…数式1
由此，在图10(c)的步骤中，接合头210能够容易地对控制芯片20的背面20b加压，并且能够抑制控制芯片20的背面与间隔片的正面的高度差。
对本发明的若干实施方式进行了说明，但这些实施方式只是作为例子提出，并不意图限定发明的范围。这些新颖的实施方式能够以其它各种方式实施，且能够在不脱离发明的主旨的范围内进行各种省略、替换、变更。这些实施方式及其变化包含在发明的范围及主旨中，并且包含在权利要求书中记载的发明及其均等的范围内。

Claims (7)

1.一种半导体装置，具备：
基板，在主面设置有第1端子；
第1半导体芯片，在第1正面设置有与所述第1端子连接的凸块电极，具有与所述第1正面为相反侧的第1背面，所述第1正面与所述主面对面；
第1间隔片，具有第2正面及与所述主面对面的第2背面，所述第2正面距所述主面的高度比所述第1背面距所述主面的高度的上限低，且比下限高；及
第2间隔片，具有第3正面及与所述主面对面的第3背面，所述第3正面距所述主面的高度比所述第1背面距所述主面的高度的上限低，且比下限高。
2.根据权利要求1所述的半导体装置，其中所述第1间隔片的面积与所述第2间隔片的面积在俯视下相互大致均等，
所述第1半导体芯片的外缘具有第1边及与所述第1边相向的第2边，
所述第1间隔片在俯视下与所述第1边并排，
所述第2间隔片在俯视下与所述第2边并排。
3.根据权利要求1所述的半导体装置，其中所述第1间隔片的面积与所述第2间隔片的面积在俯视下相互大致均等，
所述第1半导体芯片的外缘具有第1边及与所述第1边交叉的第2边，
所述第1间隔片在俯视下与所述第1边并排，
所述第2间隔片在俯视下与所述第2边并排。
4.根据权利要求1至3中任一项所述的半导体装置，其中在所述主面还设置有第2端子，且还具备：
第1膜，设置在所述主面与所述第1间隔片之间；
第2膜，设置在所述主面与所述第2间隔片之间；
第3膜，至少覆盖所述第1背面及所述第2正面；
第2半导体芯片，具有设置有第1焊垫电极的第4正面及面向所述第3膜的第4背面；及
第1接合线，将所述第2端子与所述第1焊垫电极连接；且
所述第3膜的厚度与所述第1膜的厚度大致均等，或大于所述第1膜的厚度，所述第3膜的厚度与所述第2膜的厚度大致均等，或大于所述第2膜的厚度。
5.根据权利要求4所述的半导体装置，其还具备：
第4膜，覆盖所述第4正面；
第3半导体芯片，具有设置有第2焊垫电极的第5正面及面向所述第4膜的第5背面；及
第2接合线，将所述第2端子与所述第2焊垫电极连接；且
所述第3膜的厚度与所述第4膜的厚度大致均等，或大于所述第4膜的厚度。
6.一种半导体装置，具备：
基板，在主面设置有第1端子；
第1半导体芯片，在第1正面设置有与所述第1端子连接的凸块电极，具有与所述第1正面为相反侧的第1背面，所述第1正面与所述主面对面；
第1间隔片，具有第2正面及与所述主面对面的第2背面，所述第2正面距所述主面的高度低于所述第1背面距所述主面的高度的下限；及
第2间隔片，具有第3正面及与所述主面对面的第3背面，所述第3正面距所述主面的高度低于所述第1背面距所述主面的高度的下限。
7.根据权利要求6所述的半导体装置，其中在所述主面设置有第2端子，且还具备：
膜，至少覆盖所述第1背面及所述第2正面或所述第3正面；
第2半导体芯片，具有设置有焊垫电极的第4正面及面向所述膜的第4背面；及
接合线，将所述第2端子与所述焊垫电极连接。
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