TWI768552B - 堆疊式半導體封裝結構及其製法 - Google Patents

堆疊式半導體封裝結構及其製法 Download PDF

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TWI768552B
TWI768552B TW109140719A TW109140719A TWI768552B TW I768552 B TWI768552 B TW I768552B TW 109140719 A TW109140719 A TW 109140719A TW 109140719 A TW109140719 A TW 109140719A TW I768552 B TWI768552 B TW I768552B
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chip
substrate
semiconductor package
stacked semiconductor
support
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TW109140719A
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TW202221872A (zh
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龔盈瑝
林佳鴻
姚富淵
劉俊吾
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力成科技股份有限公司
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Priority to TW109140719A priority Critical patent/TWI768552B/zh
Priority to CN202110012671.XA priority patent/CN114530422A/zh
Priority to US17/210,452 priority patent/US11670622B2/en
Publication of TW202221872A publication Critical patent/TW202221872A/zh
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Abstract

本發明係一種堆疊式半導體封裝結構及其製法，其中該堆疊式半導體封裝結構係包含一基板、一第一晶片、至少一支撐墊片、一第二晶片以及一封膠體；該第一晶片以及該第二晶片係交錯堆疊並設置於該基板上；該至少一支撐墊片係設置於該基板上，以支撐該第二晶片；該封膠體係形成於該基板上，並包覆上述元件，其中該封膠體的材質與該至少一支撐墊片的材質相同；因此，本發明之堆疊式半導體封裝結構係藉由該至少一支撐墊片材質與該封膠體材質相同的特性，加強該支撐墊片與該封膠體之間的接合力，避免於後續的可靠度測試中產生脫層現象，提升產品可靠度。

Description

堆疊式半導體封裝結構及其製法
本發明係關於一種堆疊式半導體封裝結構，尤指一種具有支撐墊片的堆疊式半導體封裝結構及其製法。
在半導體封裝技術中，一種堆疊式半導體封裝結構被提出來達到縮小封裝體積、降低功耗、提升可靠度以及安全性等多種功效。
請參閱圖5所示，係現有技術之堆疊式半導體封裝結構60，其包含有一基板61、一第一晶片62、一第二晶片63、一矽凸塊64以及一封膠體65；其中該第一晶片62以及該矽凸塊64係設置於該基板61上；該第二晶片63係堆疊於該第一晶片62上，但為不覆蓋該第一晶片62的接點621，故該第二晶片63的一側邊630係凸出該第一晶片62相對應的側邊620，使該第一晶片62的接點621外露；又為加強該第二晶片63設置在該第一晶片62的穩定性，其凸出的側邊630係堆疊於該矽凸塊64上；該封膠體65係形成於該基板61上，並包覆該第一晶片62、該第二晶片63以及該矽凸塊64。
上述之堆疊式半導體封裝結構60經可靠度測試(reliability test)後發現，該矽凸塊64與該封膠體65之間產生了脫層現象，導致產品失效，究其原 因為該矽凸塊64與該封膠體65之間接合力較弱，使產品的可靠度降低；因此，有必要進一步改良現有技術之堆疊式半導體封裝結構60。
有鑑於上述堆疊式半導體封裝結構的缺陷，本發明的主要目的係提供一種堆疊式半導體封裝結構及其製法，以解決因為脫層現象導致的可靠度下降以及產品失效等問題。
欲達上述發明之目的所使用的主要技術手段係令該堆疊式半導體封裝結構包含：一基板；一第一晶片，係設置於該基板上；至少一支撐墊片，係設置於該基板上，並位在該第一晶片的至少一側邊，以與該第一晶片的對應側邊保持一間隔；一第二晶片，係設置於該第一晶片及該至少一支撐墊片上；以及一封膠體，係形成於該基板上，並包覆該第一晶片、該至少一支撐墊片及該第二晶片，且填充該第一晶片與該至少一支撐墊片之間的間隔；其中該封膠體的材質與該至少一支撐墊片的材質相同。
本發明的優點在於，藉由該至少一支撐墊片支撐堆疊在該第一晶片上方的該第二晶片，加強該堆疊結構的穩固性，同時利用該至少一支撐墊片材質與該封膠體材質相同的特性，加強該支撐墊片與該封膠體之間的接合力，避免於可靠度測試時產生脫層現象，提升產品可靠度。
欲達上述發明之目的所使用的主要技術手段係令該堆疊式半導體封裝結構的製法包含：a.提供一基板、一第一晶片及至少一支撐墊片；b.將該第一晶片以及該至少一支撐墊片以黏膠固定於該基板上且彼此保持一間隔；c.將一第二晶片以黏膠固定於該第一晶片上及該至少一支撐墊片上；d.將該第一晶片與該第二晶片與該基板形成電連接；以及e.於該基板上形成一封膠體，以包覆該第一晶片、該至少一支撐墊片、該第二晶片及該第一晶片，並填充該第一晶片與該至少一支撐墊片之間的間隔；其中該封膠體的材質與該至少一支撐墊片的材質相同。
本發明的優點在於，預先準備至少一支撐墊片，並藉由該至少一支撐墊片材質與該封膠體材質相同的特性，加強該至少一支撐墊片與該封膠體之間的接合力，以及該至少一支撐墊片與該第二晶片的黏膠之間的接合力，避免於後續的可靠度測試中產生脫層現象，提升產品可靠度。
1a、1b:堆疊式半導體封裝結構
10:基板
11:第一接墊
12:外接墊
13:錫球
20:第一晶片
21:第一黏膠層
22:側邊
23:第一晶片接墊
24:第一導線
25:短邊
30:支撐墊片
300、300’:膠體
31:第二黏膠層
310:黏膠層
311:脫膜層
32:載板
33:頂針
34:真空吸嘴
40:第二晶片
41:短邊
42:第三黏膠層
43:第二晶片接墊
44:第二導線
45:短邊
50:封膠體
60:堆疊式半導體封裝結構
61:基板
62:第一晶片
620:側邊
621:接點
63:第二晶片
630:側邊
631:接點
64:矽凸塊
65:封膠體
圖1A：本發明之堆疊式半導體封裝結構之第一實施例的立體圖。
圖1B：本發明之堆疊式半導體封裝結構之第一實施例的剖面圖。
圖1C：本發明之堆疊式半導體封裝結構之第一實施例的俯視平面圖。
圖2A：本發明之堆疊式半導體封裝結構之第二實施例的剖面圖。
圖2B：本發明之堆疊式半導體封裝結構之第二實施例的俯視平面圖。
圖3A至圖3D：本發明之堆疊式半導體封裝結構的製法中不同步驟的剖面圖。
圖4A至圖4G：本發明之支撐墊片的製法中不同流程步驟的立體圖。
圖5：現有技術之堆疊式半導體封裝結構的剖面圖。
本發明係針對堆疊式半導體封裝結構及其製法進行改良，以下謹以多個實施例配合圖式詳細說明本發明的技術。
首先請參閱圖1A、圖1B及圖1C所示，係本發明堆疊式半導體封裝結構1a的第一實施例，該堆疊式半導體封裝結構1a包含有一基板10、一第一晶片20、二支撐墊片30、一第二晶片40以及一封膠體50，於本實施例中，該第一晶片20與該第二晶片40係交叉堆疊於該基板10上方。
上述基板10於表面形成多個第一接墊11，於底面形成多個外接墊12，該些外接墊12與對應的該些第一接墊11形成電連接，並進一步於該些外接墊12分別形成有多個錫球13或金屬凸塊。於本實施例中，該些第一接墊11係分別位在該基板10之表面上的四周邊。
上述第一晶片20係由一第一黏膠層21固定於該基板10上，並進一步於表面形成多個第一晶片接墊23，該些第一晶片接墊23經由多個第一導線24分別電連接至該基板10上對應的該些第一接墊11；於本實施例中，該第一晶片20係呈方形，該些第一晶片接墊23係分別形成於該第一晶片20表面上的二相對周邊，故分別與該基板10表面之對應二相對周邊上的該些第一接墊11打線連接；較佳地，該第一黏膠層21係一黏晶薄膜(Die Attach Film；DAF)。
上述二支撐墊片30係分別設置於該第一晶片20的二相對側邊22，並與該第一晶片20的二相對側邊22分別保持一間隔d1，該些支撐墊片30係 分別由一第二黏膠層31固定於該基板10上；於本實施例中，該些支撐墊片30係呈長方形並與該第一晶片20厚度相同；較佳地，該第二黏膠層31係一黏晶薄膜。
上述第二晶片40係交叉堆疊於該第一晶片20上，即以一第三黏膠層42固定於該第一晶片20以及該些支撐墊片30上，並進一步於表面形成多個第二晶片接墊43，其經由多個第二導線44分別電連接至該基板10上對應的該些第一接墊11；於本實施例中，該第二晶片40係呈長方形，該些第二晶片接墊43分別形成於該第二晶片40的二短邊41周邊，故分別與該基板10表面之對應二相對周邊上的該些第一接墊11打線連接，且為了使該第一晶片20的該些第一晶片接墊23露出，該第二晶片40的二短邊41係設置於該些支撐墊片30上，且該第二晶片40的二短邊41寬度與該些支撐墊片30長度相同；較佳地，該第三黏膠層42係一黏晶薄膜。
上述封膠體50係形成於該基板10上，並包覆該第一晶片20、該些支撐墊片30、該第二晶片40以及該第一晶片20與該些支撐墊片30之間的間隔d1；於本實施例中，該封膠體50材質與該些支撐墊片30材質相同。
請參閱圖2A及圖2B所示，係本發明堆疊式半導體封裝結構1b的第二實施例，本實施例之堆疊式半導體封裝結構1b與第一實施例之堆疊式半導體封裝結構1a大致相同，惟該第一晶片20與該第二晶片40大小相同且交錯堆疊，即該第二晶片40一短邊疊設在該第一晶片20的一短邊25上，不蓋合該第一晶片20另一相對短邊上的第一晶片接墊23，故該第二晶片40另一相對短邊45即疊設在該支撐墊片30上；於本實施例中，該支撐墊片30係設置於該第一晶片20 的一短邊25，並與該第一晶片20保持一間隔d2；該第二晶片40的該些第二晶片接墊43係形成於該短邊45周邊。
由上述的說明可知，本發明堆疊式半導體封裝結構之二實施例的封膠體50材質與該支撐墊片30材質相同，加強該封膠體50與該支撐墊片30間的接合力，使該堆疊式半導體封裝結構1a及1b於可靠度測試時不會產生脫層現象，提升產品的可靠度，且該支撐墊片30材質的表面較現有技術之矽凸塊64表面粗糙，與該第三黏膠層42的結合力佳，第三黏膠層42能夠更穩固的將該第二晶片40固定於該支撐墊片30上，其間不脫層；此外，該第二晶片40的相對應的短邊41或短邊45係凸出該第一晶片20的相對應的側邊22或相對應的短邊25，使該第一晶片20的該些第一晶片接墊23能夠露出，並且電連接至該基板10上對應的該些第一接墊11；該支撐墊片30的厚度與該第一晶片20厚度相同，該第二晶片40設置於該支撐墊片30上相對應的側邊寬度與該支撐墊片30長度相同，使該第二晶片40能夠穩固的被該支撐墊片30所支撐，避免晶片碎裂(Die crack)發生。
以上為本發明之堆疊式半導體封裝結構的結構說明，以下進一步說明完成該半導體封裝結構的詳細製法。
首先請參閱圖3A至3D所示，係本發明堆疊式半導體封裝結構製法的一實施例，其包含以下步驟(a)至步驟(e)。
於步驟(a)中，首先提供一基板10、一第一晶片20以及二支撐墊片30，其中該基板10於上表面四周形成多個第一接墊11，於底面形成多個外接墊12，該些外接墊12與對應的該些第一接墊11形成電連接，並進一步分別形成有多個錫球13或金屬凸塊；該第一晶片20於上表面形成多個第一晶片接墊23。
如圖3A所示的步驟(b)，將該第一晶片20由一第一黏膠層21固定該第一晶片20的下表面於該基板10上，使該第一晶片接墊23朝上露出，該些支撐墊片30係分別且間隔d1設置於該第一晶片20的兩相對應的側邊22，由一第二黏膠層31固定於該基板10上。
如圖3B所示的步驟(c)，將一第二晶片40橫跨於該第一晶片20上，並由一第三黏膠層42固定該第二晶片40的下表面於該些支撐墊片30以及該第一晶片20上，使該第一晶片20的該些第一晶片接墊23露出，其中該第二晶片40於上表面形成多個第二晶片接墊43。
如圖3C所示的步驟(d)，將該第一晶片20的該些第一晶片接墊23分別電連接至該基板10上對應的二相對周圍的該些第一接墊11，該第二晶片40的該些第二晶片接墊43分別電連接至該基板10上對應的二相對周圍的該些第一接墊11；於本實施例中，該第一晶片20以及該第二晶片40係以打線接合的方式與該基板10形成電連接。
如圖3D所示的步驟(e)，於該基板10上形成一封膠體50，並包覆該第一晶片20、該些支撐墊片30、該第二晶片40，並填充該第一晶片20以及該些支撐墊片30之間的間隔d1，完成本實施例之堆疊式半導體封裝結構，其中該封膠體50材質與該二支撐墊片30相同。
以上為本發明之堆疊式半導體封裝結構的製法說明，以下進一步說明各該支撐墊片30的詳細製法。
請參閱圖4A至圖4G所示，係本發明各該支撐墊片30製法的一實施例，其包含以下步驟(a1)至步驟(a5)。
如圖4A所示的步驟(a1)中，提供一載板32。
如圖4B所示的步驟(a2)中，於該載板32上形成一膠體300。
如圖4C所示的步驟(a3)中，於該膠體300上表面依序形成一黏膠層310及一脫膜層311。
如圖4D以及4E所示的步驟(a4)中，將該膠體300與該載板32分離，使該膠體300的下表面外露並翻轉使下表面朝上，於本實施例中，該膠體300的下表面可進一步被研磨，直到該膠體300厚度與該第一晶片20厚度相同。
如圖4F以及4G所示的步驟(a5)中，自該膠體300的下表面切割該膠體300及該黏膠層310，分離出本發明之多個支撐墊片30，於本實施例中，將切割後的該膠體300’連同該黏膠層310及脫膜層311設置於一拾取裝置上，該拾取裝置的頂針(pin)33會向上頂撐該脫膜層311，使待拾取的支撐墊片30被頂升，再由上方的真空吸嘴34吸取該待拾取的支撐墊片30，以進行前揭說明的本發明堆疊式半導體封裝結構製法，即如圖2A所示，該些支撐墊片30可使用黏晶(die bond)製程設置於基板10上。
綜上所述，本發明之堆疊式半導體封裝結構係藉由該至少一支撐墊片支撐堆疊在該第一晶片上方的該第二晶片，加強該堆疊結構的穩固性，同時利用該至少一支撐墊片材質與該封膠體材質相同的特性，加強該至少一支撐墊片與該封膠體之間的接合力，以及該至少一支撐墊片與該第二晶片的黏膠之間的接合力，避免於可靠度測試時產生脫層現象，提升產品可靠度；此外，該支撐墊片的材質成本較現有技術之矽凸塊成本低，於量產時也可達到節省成本的效果。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何 所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。
1a:堆疊式半導體封裝結構 10:基板 11:第一接墊 20:第一晶片 21:第一黏膠層 22:側邊 23:第一晶片接墊 24:第一導線 30:支撐墊片 31:第二黏膠層 40:第二晶片 41:短邊 42:第三黏膠層 43:第二晶片接墊 44:第二導線 50:封膠體

Claims (10)

  1. 一種堆疊式半導體封裝結構，包括： 一基板； 一第一晶片，係設置於該基板上； 至少一支撐墊片，係設置於該基板上，並位在該第一晶片的至少一側邊，以與該第一晶片的對應側邊保持一間隔； 一第二晶片，係設置於該第一晶片及該至少一支撐墊片上；以及 一封膠體，係形成於該基板上，並包覆該第一晶片、該至少一支撐墊片及該第二晶片，且填充該第一晶片與該至少一支撐墊片之間的間隔；其中該封膠體的材質與該至少一支撐墊片的材質相同。
  2. 如請求項1所述之堆疊式半導體封裝結構，其中： 該第一晶片係由一第一黏膠層固定於該基板上； 該至少一支撐墊片係由一第二黏膠層固定於該基板上；以及 該第二晶片係由一第三黏膠層固定於該第一晶片以及該至少一支撐墊片上。
  3. 如請求項1所述之堆疊式半導體封裝結構，其中該至少一支撐墊片的長度與設置於該至少一支撐墊片上之該第二晶片之部分的寬度相同。
  4. 如請求項1所述之堆疊式半導體封裝結構，其中該至少一支撐墊片的厚度與該第一晶片的厚度相同。
  5. 如請求項1至4中任一項所述之堆疊式半導體封裝結構，其中該基板上設置有二支撐墊片，該二支撐墊片分別位在該第一晶片的二相對側邊，以與該第一晶片的二相對側邊分別保持一間隔；其中該第二晶片係設置在該第一晶片及該二支撐墊片上。
  6. 一種堆疊式半導體封裝結構的製法，包括以下步驟： a. 提供一基板、一第一晶片及至少一支撐墊片； b. 將該第一晶片以及該至少一支撐墊片以黏膠固定於該基板上且彼此保持一間隔； c. 將一第二晶片以黏膠固定於該第一晶片上及該至少一支撐墊片上； d. 將該第一晶片及該第二晶片與該基板形成電連接；以及 e.於該基板上形成一封膠體，以包覆該第一晶片、該至少一支撐墊片、該第二晶片及該第一晶片，並填充該第一晶片與該至少一支撐墊片之間的間隔；其中該封膠體的材質與該至少一支撐墊片的材質相同。
  7. 如請求項6所述之堆疊式半導體封裝結構的製法，其中： 於上述步驟a中，提供二支撐墊片； 於上述步驟b中，將該二支撐墊片分別設置於該第一晶片的二相對應的側邊，並黏著固定於該基板上；以及 於上述步驟c中，將該第二晶片以黏膠固定於該第一晶片以及該二支撐墊片上。
  8. 如請求項6或7所述之堆疊式半導體封裝結構的製法，其中各該支撐墊片係由以下步驟製成： a1. 提供一載板； a2. 於該載板上形成一膠體； a3. 於該膠體的上表面依序形成一黏膠層及一脫膜層； a4. 將該膠體與該載板分離，使該膠體的下表面外露；以及 a5. 自該膠體的下表面切割該膠體及該黏膠層，以分離出多個支撐墊片。
  9. 如請求項8所述之堆疊式半導體封裝結構的製法，其中於上述步驟a4中，研磨該膠體的下表面，直到該膠體之厚度與該第一晶片厚度相同為止。
  10. 如請求項6或7所述之堆疊式半導體封裝結構的製法，其中於上述步驟c中，該至少一支撐墊片長度與設置於該至少一支撐墊片上之該第二晶片部分的寬度相同。
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