TWI390704B - 晶片堆疊封裝結構 - Google Patents

晶片堆疊封裝結構 Download PDF

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TWI390704B
TWI390704B TW099100336A TW99100336A TWI390704B TW I390704 B TWI390704 B TW I390704B TW 099100336 A TW099100336 A TW 099100336A TW 99100336 A TW99100336 A TW 99100336A TW I390704 B TWI390704 B TW I390704B
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substrate
wafer
flip chip
package structure
disposed
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TW201125103A (en
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Henry Chen
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

晶片堆疊封裝結構
本發明係有關一種晶片堆疊封裝結構，特別是一種可降低成本及簡化製程之晶片堆疊封裝結構。
立體式封裝目前大致有兩種方式，分別是封裝上封裝(Package on Package，PoP)以及封裝內封裝(Package in Package，PiP)。其中PoP封裝是一種很典型的立體式封裝，是藉由將獨立的兩個封裝體經封裝與測試後再以表面黏著方式疊合。
然而，製作現行PoP封裝結構須先將個別的封裝體完成後，再進行植球與堆疊組合，費時費工。且疊合後的封裝結構厚度大，實無法符合現今對於電子產品輕薄短小的需求。
為了解決上述問題，本發明目的之一係在提供一種晶片堆疊封裝結構，利用在基板上形成凹槽結構以容置一覆晶晶片，再於其上堆疊設置其他晶片，可有效降低封裝體厚度並降低基板與導電球之使用成本。
為了達到上述目的，本發明之一實施例提供一種晶片堆疊封裝結構包括：一基板含有一凹槽於其上表面。一覆晶晶片設置於基板之凹槽內並與基板電性連接，其中覆晶晶片的頂面不凸出基板的上表面。一第一晶片設置於基板之上表面並位於覆晶晶片上，其中第一晶片之主動面以一第一電接元件直接與基板之上表面電性連接。一間隔構件設置於覆晶晶片與第一晶片之間以固化並絕緣第一晶片於覆晶晶片上方， 且間隔構件係覆蓋部分基板的上表面。
為了達到上述目的，本發明之一實施例提供一種晶片堆疊封裝結構包括：一基板含有一凹槽於基板之上表面。一覆晶晶片設置於基板之凹槽內，並與基板電性連接，其中覆晶晶片的頂面不凸出基板的上表面。一第一晶片設置於基板之上表面並位於覆晶晶片上方，並以複數導電凸塊與基板電性連接。一第二晶片設置於第一晶片上，並以複數引線與基板電性連接。以及，一間隔構件設置於覆晶晶片與第一晶片之間以固化並絕緣第一晶片於覆晶晶片上方，且間隔構件係覆蓋部分基板的上表面與第一晶片上的複數導電凸塊。
其詳細說明如下，所述較佳實施例僅做一說明非用以限定本發明。
請先參考圖1A，圖1A為本發明一實施例之晶片堆疊封裝結構之剖視圖。如圖所示，一基板10以適當方法形成一凹槽12於基板10的上表面11。一覆晶晶片20設置於基板10之凹槽12內並與基板10電性連接，其中覆晶晶片20的頂面不凸出基板10的上表面11。一第一晶片30堆疊設置於基板10之上表面11並位於覆晶晶片20上，，其中第一晶片30之主動面以一第一電接元件40直接與基板10的上表面11電性連接。於一實施例中，第一電接元件40可為複數引線(如圖1C所示)或是導電凸塊(如圖1A、1B所示)。
接續上述，如圖1A所示，第一晶片30為一覆晶晶片，且一間隔構件50以適當方法設置於覆晶晶片20與第一晶片30之間，以固化第一晶片30於覆晶晶片20的上方，且間隔構件50係覆蓋部分基板10的上表面11。又一實施例中，如 圖1B所示，若基板10之凹槽12的尺寸大於或遠大於覆晶晶片20之尺寸，間隔構件50有可能會填充至基板10之凹槽12內。於上述實施例中，間隔構件50之材質包括一環氧樹脂、一B階固化膠或其他合適之塗層材料，而間隔構件50不僅可固定第一晶片30於覆晶晶片20或是基板10上，更可電性絕緣第一晶片30與覆晶晶片20。於一實施例中，如圖1C所示，第一晶片30亦可為打線型晶片，利用電接元件40(例如複數條引線)以打線方式與基板10電性連接。
接續請同時參考圖1A、1B及1C，更包括一封裝膠體60(例如由環氧樹脂所構成)包覆第一晶片30、電接元件40及基板10。且複數個導電球70設置於基板10之下表面13，使晶片堆疊封裝結構可電性連接於外界裝置上。
於又一實施例中，更包括一第二晶片設置於第一晶片上方，並以一第二電接元件電性連接基板之上表面。詳細說明請參見圖2A，晶片堆疊封裝結構包括：一基板10含有一凹槽12於基板10之上表面11。一覆晶晶片20設置於基板10之凹槽12內，並與基板10電性連接，且覆晶晶片20的頂面不凸出基板10的上表面11。一第一晶片30設置於基板10之上表面11並位於覆晶晶片20上方，並以複數導電凸塊42與基板10電性連接。一第二晶片32設置於第一晶片30上，並以複數引線44與基板10電性連接。以及，一間隔構件50設置於覆晶晶片20與第一晶片30之間以固化並絕緣第一晶片30於覆晶晶片20上方，且間隔構件50係覆蓋部分基板10的上表面11與第一晶片30上的複數導電凸塊42。
於再一實施例中，如圖2B所示，與圖2A之差異在於，第一晶片30以複數條引線43以打線的方式與基板10電性連接。一間隔構件52設置於第一晶片30與第二晶片32之間以包覆引線43，並使第一晶片30與第二晶片32電性隔絕。且 可以理解的是，第二晶片32之尺寸不限於圖2A與圖2B所示，第二晶片32之尺寸亦可小於第一晶片30之尺寸，甚至，亦可堆疊更多晶片於第二晶片32上，以擴充晶片堆疊結構之功能或容量。
本發明係利用於在基板之上表面形成一凹槽，凹槽上可容置封裝體所需之其他晶片(於此實施例中，為一覆晶晶片，但不為限)，並在其上堆疊其他晶片(打線型晶片與覆晶型晶片皆可)，如此，可有效解決PoP封裝結構總高度過厚之問題。此外，亦可減少當多個封裝體堆疊時，基板與導電球的使用，大大降低生產成本。再者，簡化製程後，亦可改善PoP封裝結構中上層封裝體與下層封裝體導電球對位的問題。
綜合上述，本發明一實施例之一種晶片堆疊封裝結構，利用在基板上形成凹槽結構以容置一覆晶晶片，再於其上堆疊設置其他晶片，可有效降低封裝體厚度並降低基板與導電球之使用成本。
以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。
10‧‧‧基板
11‧‧‧上表面
12‧‧‧凹槽
13‧‧‧下表面
20‧‧‧覆晶晶片
30,32‧‧‧晶片
42‧‧‧導電凸塊
43,44‧‧‧引線
50,52‧‧‧間隔構件
60‧‧‧封裝膠體
70‧‧‧導電球
圖1A、圖1B、圖1C為本發明一實施例之晶片堆疊封裝結構的剖視圖。
圖2A、圖2B為本發明不同實施例之結構剖視圖。
10．．．基板
11．．．上表面
12．．．凹槽
13．．．下表面
20．．．覆晶晶片
30,32．．．晶片
42．．．導電凸塊
44．．．引線
50．．．間隔構件
60．．．封裝膠體
70．．．導電球

Claims (9)

  1. 一種晶片堆疊封裝結構，包含：一基板，含有一凹槽於該基板之一上表面；一覆晶晶片，設置於該基板之該凹槽內，並與該基板之該上表面電性連接，其中該覆晶晶片的頂面不凸出該基板的該上表面；一第一晶片，設置於該基板之該上表面並位於該覆晶晶片上方，其中該第一晶片之主動面以一第一電接元件直接與該基板之該上表面電性連接；以及一間隔構件，設置於該覆晶晶片與該第一晶片之間以固化並絕緣該第一晶片於該覆晶晶片上方，且該間隔構件係覆蓋部分該基板的該上表面。
  2. 如請求項1所述之晶片堆疊封裝結構，更包含一第二晶片設置於該第一晶片上方，並以一第二電接元件電性連接該基板之該上表面。
  3. 如請求項2所述之晶片堆疊封裝結構，其中該第一電接元件與該第二電接元件係為複數條引線或複數個導電凸塊。
  4. 如請求項1所述之晶片堆疊封裝結構，其中該第一晶片為一覆晶晶片。
  5. 如請求項1所述之晶片堆疊封裝結構，其中該間隔構件係填充至該凹槽內。
  6. 如請求項1所述之晶片堆疊封裝結構，更包含一封裝膠體包覆該第二晶片、該第二電接元件與該基板。
  7. 一種晶片堆疊封裝結構，包含：一基板，含有一凹槽於該基板之一上表面；一覆晶晶片，設置於該基板之該凹槽內，並與該基板電性連接，其中該覆晶晶片的頂面不凸出該基板的該上表面；一第一晶片，設置於該基板之該上表面並位於該覆晶晶片上方，並以複數導電凸塊與該基板電性連接；一第二晶片，設置於該第一晶片上，並以複數引線與該基板電性連接；以及 一間隔構件，設置於該覆晶晶片與該第一晶片之間以固化並絕緣該第一晶片於該覆晶晶片上方，且該間隔構件係覆蓋部分該基板的該上表面與該第一晶片上的該複數導電凸塊。
  8. 如請求項7所述之晶片堆疊封裝結構，其中該間隔構件係填充至該凹槽內。
  9. 如請求項7所述之晶片堆疊封裝結構，更包含一封裝膠體包覆該第一晶片、該第一電接元件與該基板。
TW099100336A 2010-01-08 2010-01-08 晶片堆疊封裝結構 TWI390704B (zh)

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