US20230378153A1 - Package-on-Package Structure Including a Thermal Isolation Material - Google Patents

Package-on-Package Structure Including a Thermal Isolation Material Download PDF

Info

Publication number
US20230378153A1
US20230378153A1 US18/361,515 US202318361515A US2023378153A1 US 20230378153 A1 US20230378153 A1 US 20230378153A1 US 202318361515 A US202318361515 A US 202318361515A US 2023378153 A1 US2023378153 A1 US 2023378153A1
Authority
US
United States
Prior art keywords
die
package component
package
seal ring
thermal isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US18/361,515
Inventor
Meng-Tse Chen
Kuei-Wei Huang
Tsai-Tsung Tsai
Ai-Tee Ang
Ming-Da Cheng
Chung-Shi Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US18/361,515 priority Critical patent/US20230378153A1/en
Publication of US20230378153A1 publication Critical patent/US20230378153A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1431Logic devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Definitions

  • POP Package-on-package
  • a conventional package-on-package structure may include a bottom package component and a top package component.
  • the bottom package component may include a bottom die attached to a bottom substrate and the top package component may include a top die attached to a top substrate.
  • the bottom package component is coupled to the top package component typically by a set of conductive elements, such as solder balls.
  • solder balls In operation, both package components generate heat.
  • excessive heat that is generated by the bottom die, especially where the bottom die is a device die may cause damage to the top die.
  • the heat can also cause thermal stress and warpage in the package-on-package structure leading to cracks in the solder balls. Even with the use of molding compounds in the package-on-package structure, the problem of excess heat and warpage still cannot be entirely eliminated.
  • FIG. 1 is a flowchart of a method of fabricating a package-on-package structure according to various embodiments of the present disclosure.
  • FIGS. 2 - 6 are cross-sectional views of a top package and/or a bottom package at various intermediate stages in the manufacture of a package-on-package structure, in accordance with various embodiments of the present disclosure.
  • FIG. 1 is a flowchart of a method 100 for fabricating a package-on-package according to various aspects of the present disclosure.
  • the method includes block 110 , in which a first package component is provided, the first package component having a first die formed on a first substrate.
  • the method 100 includes block 120 , in which a second package component is provided, the second package component having a second die formed on a second substrate.
  • the method 100 includes block 130 , in which a thermal isolation material is attached to the first die. The thermal isolation material substantially thermally insulates the second die from the first die.
  • the method 100 includes block 140 , in which the first package component is coupled to the second package component with a set of conductive elements.
  • FIGS. 2 - 6 are diagrammatic fragmentary cross-sectional side views of a top package and/or a bottom package at various fabrication stages of manufacturing a package-on-package structure according to embodiments of the method 100 of FIG. 1 . It is understood that FIGS. 2 - 6 have been simplified for a better understanding of the inventive concepts of the present disclosure. It should be appreciated that the materials, geometries, dimensions, structures, and process parameters described herein are exemplary only, and are not intended to be, and should not be construed to be, limiting to the invention claimed herein. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure.
  • FIG. 2 illustrates a top package 1 to be employed in the package-on-package structure.
  • Top package 1 which may be formed using a plastic ball grid array (PBGA) package assembly process or the like, includes a plurality of stacked die 2 , which may be wired bonded to top substrate 10 by way of contacts 16 (on respective stacked die 2 ), bond wires 6 , and contacts 12 (on top substrate 10 ).
  • Individual stacked die may comprise a memory chip, a logic chip, a processor chip, or the like.
  • FIG. 2 illustrates three stacked die, this is for illustration only.
  • wire bonding is merely illustrative, and other approaches for electrically connecting the stacked die are within the contemplated scope of the present disclosure.
  • solder bumps, solder balls, copper pillars, conductive bumps, solder caps, conductive pillars, conductive balls, under-bump metallurgies, and/or other connector elements may also be contemplated to connect stacked die 2 to top substrate 10 .
  • an underfill (not shown) is dispensed into the gap between stacked die 2 and top substrate 10 to reinforce the strength of the package-on-package structure.
  • Top substrate 10 may be a laminated circuit board comprised of alternating layers of non-conductive polymers, such as bismaleinide-triazine (BT), and patterned (or non-patterned) conductive layers. As discussed above, top substrate 10 has contacts 12 on a first side (referred to herein sometimes as a top side for convenience) for electrical connection to stacked die 2 . Top substrate 10 further has bottom contacts 24 on a second side (sometimes referred to as a bottom side) for electrical connection to other components as will be detailed further below. Solder balls 36 are attached to bottom contacts 24 to top substrate 10 . Solder balls 36 allow for electrical and/or thermal connection between top package 1 and a bottom package 34 (not shown in FIG. 2 , but illustrated in FIGS. 3 and 4 ).
  • BT bismaleinide-triazine
  • solder balls 36 provide for electrical conduction of signals and power to stacked die 2 .
  • other connection components such as conductive bumps, conductive balls, conductive pillars, and the like, could be employed in lieu of solder balls 36 .
  • a molding compound 35 is applied to top package 1 to provide mechanical stiffness and enhance the mechanical strength of the package-on-package structure. It is believed that this mechanical stiffness prevents, or at least reduces, the severity of warpages resulting from, for example, thermal expansion mismatch between the components of the resulting package. Molding compound 35 may be molded on substrate 10 and surrounds stacked die 2 and bond wires 6 using, for example, compressive molding or transfer molding. A curing step may then be performed to solidify the molding compound 35 .
  • the molding compound 35 may comprise a polymer-based material, an underfill, a molding underfill (MUF), an epoxy, or the like.
  • Top package 1 is attached to a bottom package 34 , as illustrated in FIG. 5 byway of solder balls 36 .
  • the bottom package 34 includes die 37 , which is flip chip attached to a bottom substrate 38 , and which is electrically connected thereto by way of connector elements 39 .
  • Die 37 may comprise a logic chip, a processor chip, a memory chip, or the like.
  • Connector elements 39 may include, for example solder bumps, solder balls, copper pillars, conductive bumps, solder caps, conductive pillars, conductive balls, and under-bump metallurgies.
  • an underfill (not shown) is dispensed into the gap between die 37 and bottom substrate 38 to reinforce the strength of the package-on-package structure.
  • Electrical connection between die 37 and an underlying mother board or other circuitry is provided by through vias (not shown) aligned with connector elements 39 on one side of bottom substrate 38 and connector elements 42 on the other side of bottom substrate 38 .
  • electrical connection between top substrate 10 and an underlying mother board or other circuitry is provided by solder balls 36 , through vias, and connector elements 42 .
  • both the bottom package 34 and the top package 1 that include die 37 and stacked die 2 respectively generate heat.
  • Heat that is generated by die 37 may cause damage to the top die or stacked die 2 .
  • the heat can also cause thermal stress and warpage in the package-on-package structure leading to cracks in the connector elements, such as solder balls.
  • An advantageous feature of the package-on-package structure of the present disclosure is a thermal isolation material 50 of the bottom package 34 , as depicted in FIG. 3 , attached above die 37 and thermally insulates stacked die 2 from the heat generated by die 37 .
  • thermal isolation material 55 provides resistance to warping that might otherwise occur as a result of thermal coefficient of expansion (CTE) mismatch between top package 1 and bottom packager 34 .
  • the thermal isolation material 50 is a material having a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK.
  • the thermal isolation material 50 may comprise a porous film, a wax film, a die attach film (DAF), an aerogel, a tape, a thermal interface material (TIM), or an adhesive.
  • the thermal isolation material 50 is a TIM
  • the TIM may comprise a solder paste, an adhesive, or thermal grease.
  • the thermal isolation material 50 has a thickness ranging from about 10 microns to about 100 microns.
  • FIG. 5 shows the thermal isolation material 50 in the package-on-package structure where the bottom package 34 is attached to the top package 1 .
  • the thermal isolation material 50 is a seal ring 55 having air or vacuum 77 therein, as shown in FIG. 4 and as shown in FIG. 6 .
  • the seal ring 55 is formed in the package-on-package structure where the bottom package 34 is attached to top package 1 . Air or vacuum is an ideal thermal insulator under normal operation conditions.
  • the seal ring 55 provides a thermal conductivity of about 0 W/mK. Seal ring 55 is dispensed on die 37 to provide a vacuum gap during a molding process that will be explained below.
  • a molding compound 35 is applied to bottom package 34 to provide mechanical stiffness and enhance the mechanical strength of the package-on-package structure.
  • Molding compound 35 may be molded on substrate 38 and surround die 37 and connector elements 39 using, for example, compressive molding or transfer molding.
  • a curing step may then be performed to solidify the molding compound 35 .
  • the molding compound 35 may comprise a polymer-based material, an underfill, a molding underfill (MUF), an epoxy, or the like.
  • UMF molding underfill
  • the molding compound 35 is formed around the seal ring 55 , thereby encapsulating the air or vacuum 77 therein.
  • FIGS. 2 - 6 The package-on-package structures shown in FIGS. 2 - 6 are only for illustrative purpose and are not limiting. Additional embodiments can be conceived.
  • the top die in a package-on-package structure having a top package with a top die and a bottom package with a bottom die, the top die is substantially insulated from the heat generated by the bottom die.
  • warpage in a package-on-package structure is better to control because the top package and the bottom package are substantially insulated from heat.
  • a semiconductor device includes a first package component and a second package component.
  • the first package component has a first die formed on a first substrate.
  • the second package component has a second die formed on a second substrate.
  • a first set of conductive elements couples the first package component to the second package component.
  • a thermal isolation material is applied on the first die and interjacent the first package component and the second package component, wherein the thermal isolation material thermally insulates the second die from the first die.
  • the thermal isolation material includes a seal ring and an air gap.
  • a package-on-package includes a bottom package component and a top package component.
  • the bottom package component has at least a bottom die formed on a bottom substrate.
  • the top package component has at least a top die formed on a top substrate.
  • a thermal isolation material is attached to the bottom die, wherein the thermal isolation material thermally insulates the top die from the bottom die.
  • the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK.
  • a first set of conductive elements couples the bottom substrate to the top substrate.
  • the thermal isolation material includes a seal ring and an air gap.
  • a method of forming a package is disclosed.
  • a first package component is provided, and the first package component has a first die formed on a first substrate.
  • a second package component is provided, and the second package component has a second die formed on a second substrate.
  • a thermal isolation material is attached to the first die, wherein the thermal isolation material thermally insulates the second die from the first die.
  • the first package component is coupled to the second package component with a first set of conductive elements.
  • the thermal isolation material includes a seal ring and an air gap.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Description

    PRIORITY CLAIM AND CROSS-REFERENCE
  • This application is a continuation of U.S. patent application Ser. No. 16/580,617, entitled “Package-on-Package Structure Including a Thermal Isolation Material,” filed on Sep. 24, 2019, which is a continuation of U.S. patent application Ser. No. 15/228,098, entitled, “Package-on-Package Structure Including a Thermal Isolation Material and Method of Forming the Same,” filed on Aug. 4, 2016, now U.S. Pat. No. 10,490,539 issued Nov. 26, 2019, which is a continuation of U.S. patent application Ser. No. 13/671,665, entitled “Package-on-Package Structure Including a Thermal Isolation Material and Method of Forming the Same,” filed on Nov. 8, 2012, now U.S. Pat. No. 9,418,971 issued Aug. 16, 2016, which applications are incorporated herein by reference.
  • BACKGROUND
  • Package-on-package (POP) is becoming an increasingly popular integrated circuit packaging technique because it allows for higher density electronics.
  • A conventional package-on-package structure may include a bottom package component and a top package component. The bottom package component may include a bottom die attached to a bottom substrate and the top package component may include a top die attached to a top substrate. The bottom package component is coupled to the top package component typically by a set of conductive elements, such as solder balls. In operation, both package components generate heat. However, excessive heat that is generated by the bottom die, especially where the bottom die is a device die, may cause damage to the top die. The heat can also cause thermal stress and warpage in the package-on-package structure leading to cracks in the solder balls. Even with the use of molding compounds in the package-on-package structure, the problem of excess heat and warpage still cannot be entirely eliminated.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
  • FIG. 1 is a flowchart of a method of fabricating a package-on-package structure according to various embodiments of the present disclosure.
  • FIGS. 2-6 are cross-sectional views of a top package and/or a bottom package at various intermediate stages in the manufacture of a package-on-package structure, in accordance with various embodiments of the present disclosure.
  • DETAILED DESCRIPTION
  • In the following description, specific details are set forth to provide a thorough understanding of embodiments of the present disclosure. However, one having an ordinary skill in the art will recognize that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known structures and processes are not described in detail to avoid unnecessarily obscuring embodiments of the present disclosure.
  • Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are intended for illustration.
  • FIG. 1 is a flowchart of a method 100 for fabricating a package-on-package according to various aspects of the present disclosure. Referring to FIG. 1 , the method includes block 110, in which a first package component is provided, the first package component having a first die formed on a first substrate. The method 100 includes block 120, in which a second package component is provided, the second package component having a second die formed on a second substrate. The method 100 includes block 130, in which a thermal isolation material is attached to the first die. The thermal isolation material substantially thermally insulates the second die from the first die. The method 100 includes block 140, in which the first package component is coupled to the second package component with a set of conductive elements.
  • It is understood that additional processes may be performed before, during, or after the blocks 110-140 shown in FIG. 1 to complete the fabrication of the package-on-package structure, but these additional processes are not discussed herein in detail for the sake of simplicity.
  • FIGS. 2-6 are diagrammatic fragmentary cross-sectional side views of a top package and/or a bottom package at various fabrication stages of manufacturing a package-on-package structure according to embodiments of the method 100 of FIG. 1 . It is understood that FIGS. 2-6 have been simplified for a better understanding of the inventive concepts of the present disclosure. It should be appreciated that the materials, geometries, dimensions, structures, and process parameters described herein are exemplary only, and are not intended to be, and should not be construed to be, limiting to the invention claimed herein. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure.
  • An embodiment package-on-package structure will be discussed with reference to FIGS. 2-6 . FIG. 2 illustrates a top package 1 to be employed in the package-on-package structure. Top package 1, which may be formed using a plastic ball grid array (PBGA) package assembly process or the like, includes a plurality of stacked die 2, which may be wired bonded to top substrate 10 by way of contacts 16 (on respective stacked die 2), bond wires 6, and contacts 12 (on top substrate 10). Individual stacked die may comprise a memory chip, a logic chip, a processor chip, or the like. Although FIG. 2 illustrates three stacked die, this is for illustration only. Likewise, the use of wire bonding is merely illustrative, and other approaches for electrically connecting the stacked die are within the contemplated scope of the present disclosure. For example, solder bumps, solder balls, copper pillars, conductive bumps, solder caps, conductive pillars, conductive balls, under-bump metallurgies, and/or other connector elements may also be contemplated to connect stacked die 2 to top substrate 10. In some embodiments, an underfill (not shown) is dispensed into the gap between stacked die 2 and top substrate 10 to reinforce the strength of the package-on-package structure.
  • Top substrate 10 may be a laminated circuit board comprised of alternating layers of non-conductive polymers, such as bismaleinide-triazine (BT), and patterned (or non-patterned) conductive layers. As discussed above, top substrate 10 has contacts 12 on a first side (referred to herein sometimes as a top side for convenience) for electrical connection to stacked die 2. Top substrate 10 further has bottom contacts 24 on a second side (sometimes referred to as a bottom side) for electrical connection to other components as will be detailed further below. Solder balls 36 are attached to bottom contacts 24 to top substrate 10. Solder balls 36 allow for electrical and/or thermal connection between top package 1 and a bottom package 34 (not shown in FIG. 2 , but illustrated in FIGS. 3 and 4 ). In the illustrated embodiment, solder balls 36 provide for electrical conduction of signals and power to stacked die 2. Again, other connection components, such as conductive bumps, conductive balls, conductive pillars, and the like, could be employed in lieu of solder balls 36.
  • In some embodiments, a molding compound 35 is applied to top package 1 to provide mechanical stiffness and enhance the mechanical strength of the package-on-package structure. It is believed that this mechanical stiffness prevents, or at least reduces, the severity of warpages resulting from, for example, thermal expansion mismatch between the components of the resulting package. Molding compound 35 may be molded on substrate 10 and surrounds stacked die 2 and bond wires 6 using, for example, compressive molding or transfer molding. A curing step may then be performed to solidify the molding compound 35. The molding compound 35 may comprise a polymer-based material, an underfill, a molding underfill (MUF), an epoxy, or the like.
  • Top package 1 is attached to a bottom package 34, as illustrated in FIG. 5 byway of solder balls 36. As depicted in FIG. 3 , the bottom package 34 includes die 37, which is flip chip attached to a bottom substrate 38, and which is electrically connected thereto by way of connector elements 39. Die 37 may comprise a logic chip, a processor chip, a memory chip, or the like. Connector elements 39 may include, for example solder bumps, solder balls, copper pillars, conductive bumps, solder caps, conductive pillars, conductive balls, and under-bump metallurgies. In some embodiments, an underfill (not shown) is dispensed into the gap between die 37 and bottom substrate 38 to reinforce the strength of the package-on-package structure. Electrical connection between die 37 and an underlying mother board or other circuitry (not shown) is provided by through vias (not shown) aligned with connector elements 39 on one side of bottom substrate 38 and connector elements 42 on the other side of bottom substrate 38. Likewise, electrical connection between top substrate 10 and an underlying mother board or other circuitry is provided by solder balls 36, through vias, and connector elements 42.
  • In operation, both the bottom package 34 and the top package 1 that include die 37 and stacked die 2, respectively generate heat. Heat that is generated by die 37, especially where the bottom die is a processor die, may cause damage to the top die or stacked die 2. The heat can also cause thermal stress and warpage in the package-on-package structure leading to cracks in the connector elements, such as solder balls. An advantageous feature of the package-on-package structure of the present disclosure is a thermal isolation material 50 of the bottom package 34, as depicted in FIG. 3 , attached above die 37 and thermally insulates stacked die 2 from the heat generated by die 37. In one embodiment, as an additional benefit because the top package 1 and bottom package 34 are insulated from heat thanks to the thermal isolation material 55, warpage in the package-on-package structure is better controlled. In other words, thermal isolation material 55 provides resistance to warping that might otherwise occur as a result of thermal coefficient of expansion (CTE) mismatch between top package 1 and bottom packager 34.
  • In some embodiments, the thermal isolation material 50 is a material having a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. The thermal isolation material 50 may comprise a porous film, a wax film, a die attach film (DAF), an aerogel, a tape, a thermal interface material (TIM), or an adhesive. Where the thermal isolation material 50 is a TIM, the TIM may comprise a solder paste, an adhesive, or thermal grease. In some embodiments, the thermal isolation material 50 has a thickness ranging from about 10 microns to about 100 microns.
  • FIG. 5 shows the thermal isolation material 50 in the package-on-package structure where the bottom package 34 is attached to the top package 1.
  • In other embodiments, the thermal isolation material 50 is a seal ring 55 having air or vacuum 77 therein, as shown in FIG. 4 and as shown in FIG. 6 . The seal ring 55 is formed in the package-on-package structure where the bottom package 34 is attached to top package 1. Air or vacuum is an ideal thermal insulator under normal operation conditions. In other embodiments, the seal ring 55 provides a thermal conductivity of about 0 W/mK. Seal ring 55 is dispensed on die 37 to provide a vacuum gap during a molding process that will be explained below.
  • After either the thermal isolation material 50 or the seal ring 55 has been applied to die 37, in some embodiments, a molding compound 35 is applied to bottom package 34 to provide mechanical stiffness and enhance the mechanical strength of the package-on-package structure. Molding compound 35 may be molded on substrate 38 and surround die 37 and connector elements 39 using, for example, compressive molding or transfer molding. A curing step may then be performed to solidify the molding compound 35. The molding compound 35 may comprise a polymer-based material, an underfill, a molding underfill (MUF), an epoxy, or the like. Referring back to FIG. 4 , to form the air or vacuum 77, the molding compound 35 is formed around the seal ring 55, thereby encapsulating the air or vacuum 77 therein.
  • The package-on-package structures shown in FIGS. 2-6 are only for illustrative purpose and are not limiting. Additional embodiments can be conceived.
  • Advantages of one or more embodiments of the present disclosure may include one or more of the following.
  • In one or more embodiments, in a package-on-package structure having a top package with a top die and a bottom package with a bottom die, the top die is substantially insulated from the heat generated by the bottom die.
  • In one or more embodiments, warpage in a package-on-package structure is better to control because the top package and the bottom package are substantially insulated from heat.
  • The present disclosure has described various exemplary embodiments. According to one embodiment, a semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. The second package component has a second die formed on a second substrate. A first set of conductive elements couples the first package component to the second package component. A thermal isolation material is applied on the first die and interjacent the first package component and the second package component, wherein the thermal isolation material thermally insulates the second die from the first die. In some embodiments, the thermal isolation material includes a seal ring and an air gap.
  • According to another embodiment, a package-on-package includes a bottom package component and a top package component. The bottom package component has at least a bottom die formed on a bottom substrate. The top package component has at least a top die formed on a top substrate. A thermal isolation material is attached to the bottom die, wherein the thermal isolation material thermally insulates the top die from the bottom die. The thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the bottom substrate to the top substrate. In some embodiments, the thermal isolation material includes a seal ring and an air gap.
  • According to yet another embodiment, a method of forming a package is disclosed. A first package component is provided, and the first package component has a first die formed on a first substrate. A second package component is provided, and the second package component has a second die formed on a second substrate. A thermal isolation material is attached to the first die, wherein the thermal isolation material thermally insulates the second die from the first die. The first package component is coupled to the second package component with a first set of conductive elements. In some embodiments, the thermal isolation material includes a seal ring and an air gap.
  • In the preceding detailed description, specific exemplary embodiments have been described. It will, however, be apparent to a person of ordinary skill in the art that various modifications, structures, processes, and changes may be made thereto without departing from the broader spirit and scope of the present disclosure. The specification and drawings are, accordingly, to be regarded as illustrative and not restrictive. It is understood that embodiments of the present disclosure are capable of using various other combinations and environments and are capable of changes or modifications within the scope of the claims.

Claims (20)

What is claimed is:
1. A method comprising:
disposing a thermal isolation material on a top surface of a die, wherein the die is comprised in a lower package component, and wherein at a time the thermal isolation material is disposed, outer edges of the thermal isolation material are aligned to corresponding edges of the die;
bonding an upper package component to the lower package component, wherein the thermal isolation material is between, and is in contact with, both of the die and the upper package component; and
after the upper package component is bonded to the lower package component, disposing a molding compound between the upper package component and the lower package component.
2. The method of claim 1, wherein the thermal isolation material is a solid plate that continuously extends from a first edge of the die to an opposing second edge of the die.
3. The method of claim 1, wherein the thermal isolation material comprises a porous film.
4. The method of claim 1, wherein the thermal isolation material comprises an aerogel.
5. The method of claim 1, wherein the thermal isolation material has a thermal conductivity value in a range between about 0.024 W/mK and about 0.2 W/mK.
6. The method of claim 1, wherein the molding compound is dispensed in a flowable form, and the method further comprises curing to solidify the molding compound.
7. The method of claim 1, wherein the thermal isolation material is in a form of a seal ring encircling a space therein, and wherein after the upper package component is bonded to the lower package component, an air gap or vacuum is enclosed by the seal ring, the upper package component, and the die.
8. The method of claim 7, wherein the molding compound is in contact with the outer edges of the seal ring, with the outer edges of the seal ring being the outer edges of the thermal isolation material, and wherein inner edges of the seal ring are exposed to air or vacuum.
9. The method of claim 8, wherein the seal ring encircles air therein.
10. The method of claim 7, wherein the seal ring encircles a vacuumed space therein.
11. A method comprising:
forming a lower package comprising a device die;
bonding an upper package over the lower package; and
forming a filling region between the lower package and the upper package, wherein the filling region encircles a space that is between the upper package and the device die, and the space comprises an air space or a vacuumed space.
12. The method of claim 11, wherein the filling region comprises:
attaching a first material in a region directly over the device die; and
dispensing a second material vertically offset from the device die, wherein the second material is different from the first material.
13. The method of claim 12, wherein the first material and the second material have interfaces that are vertically aligned to outer edges of the device die.
14. The method of claim 12, wherein the first material and the second material are attached to the device die through different processes.
15. A method comprising:
forming a lower package component comprising bonding a die to a substrate;
forming a seal ring on a first top surface of the die;
bonding a upper package component to the lower package component, wherein a space is defined by the upper package component, the die, and the seal ring; and
dispensing an encapsulant between, and contacting both of, the upper package component and the lower package component, so that the space and the seal ring are encircled by the encapsulant, wherein the encapsulant and the seal ring form interfaces that extend from a bottom surface to a second top surface of the seal ring, and the interfaces are vertically aligned to corresponding edges of the die.
16. The method of claim 15 further comprising curing the encapsulant.
17. The method of claim 15, wherein at a time after the encapsulant is dispensed, the space is an air gap.
18. The method of claim 15, wherein at a time after the encapsulant is dispensed, the space is a vacuumed space.
19. The method of claim 15, wherein the seal ring comprises inner edges that face the space, and the inner edges are vertical and straight edges.
20. The method of claim 15, wherein the encapsulant is dispensed after the seal ring is formed.
US18/361,515 2012-11-08 2023-07-28 Package-on-Package Structure Including a Thermal Isolation Material Pending US20230378153A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/361,515 US20230378153A1 (en) 2012-11-08 2023-07-28 Package-on-Package Structure Including a Thermal Isolation Material

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13/671,665 US9418971B2 (en) 2012-11-08 2012-11-08 Package-on-package structure including a thermal isolation material and method of forming the same
US15/228,098 US10490539B2 (en) 2012-11-08 2016-08-04 Package on-package structure including a thermal isolation material and method of forming the same
US16/580,617 US11776945B2 (en) 2012-11-08 2019-09-24 Package-on-package structure including a thermal isolation material
US18/361,515 US20230378153A1 (en) 2012-11-08 2023-07-28 Package-on-Package Structure Including a Thermal Isolation Material

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US16/580,617 Continuation US11776945B2 (en) 2012-11-08 2019-09-24 Package-on-package structure including a thermal isolation material

Publications (1)

Publication Number Publication Date
US20230378153A1 true US20230378153A1 (en) 2023-11-23

Family

ID=50621621

Family Applications (4)

Application Number Title Priority Date Filing Date
US13/671,665 Active US9418971B2 (en) 2012-11-08 2012-11-08 Package-on-package structure including a thermal isolation material and method of forming the same
US15/228,098 Active 2033-04-12 US10490539B2 (en) 2012-11-08 2016-08-04 Package on-package structure including a thermal isolation material and method of forming the same
US16/580,617 Active 2035-02-21 US11776945B2 (en) 2012-11-08 2019-09-24 Package-on-package structure including a thermal isolation material
US18/361,515 Pending US20230378153A1 (en) 2012-11-08 2023-07-28 Package-on-Package Structure Including a Thermal Isolation Material

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US13/671,665 Active US9418971B2 (en) 2012-11-08 2012-11-08 Package-on-package structure including a thermal isolation material and method of forming the same
US15/228,098 Active 2033-04-12 US10490539B2 (en) 2012-11-08 2016-08-04 Package on-package structure including a thermal isolation material and method of forming the same
US16/580,617 Active 2035-02-21 US11776945B2 (en) 2012-11-08 2019-09-24 Package-on-package structure including a thermal isolation material

Country Status (3)

Country Link
US (4) US9418971B2 (en)
KR (1) KR101531746B1 (en)
CN (1) CN103811430B (en)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9263377B2 (en) 2012-11-08 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures with dams encircling air gaps and methods for forming the same
CN203026500U (en) * 2012-12-25 2013-06-26 华为终端有限公司 Stack packaging device
US8883563B1 (en) * 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9379097B2 (en) * 2014-07-28 2016-06-28 Apple Inc. Fan-out PoP stacking process
WO2016044179A2 (en) 2014-09-15 2016-03-24 Invensas Corporation Electronic structures strengthened by porous and non-porous layers, and methods of fabrication
KR102307490B1 (en) 2014-10-27 2021-10-05 삼성전자주식회사 Semiconductor package
KR102285332B1 (en) * 2014-11-11 2021-08-04 삼성전자주식회사 Semiconductor package and semiconductor device comprising the same
US9589936B2 (en) * 2014-11-20 2017-03-07 Apple Inc. 3D integration of fanout wafer level packages
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
CN104659005A (en) * 2015-01-23 2015-05-27 三星半导体(中国)研究开发有限公司 Packaging device, package stacking structure comprising packaging device, and manufacturing method of packaging device
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9947642B2 (en) * 2015-10-02 2018-04-17 Qualcomm Incorporated Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10115675B2 (en) * 2016-06-28 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of fabricating a packaged semiconductor device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
WO2018126542A1 (en) * 2017-01-04 2018-07-12 华为技术有限公司 Pop (package on package) structure and terminal
CN110060961B (en) * 2018-01-19 2021-07-09 华为技术有限公司 Wafer packaging device
WO2020166567A1 (en) * 2019-02-15 2020-08-20 株式会社村田製作所 Electronic module and method for manufacturing electronic module
US11854935B2 (en) * 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias
US11069383B1 (en) 2020-04-06 2021-07-20 Seagate Technology Llc Thermal interface materials for immersion cooled data storage devices
US20220051962A1 (en) * 2020-08-12 2022-02-17 Micron Technology, Inc. Semiconductor device assemblies and systems with internal thermal barriers and methods for making the same
US11830821B2 (en) 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
JP4036694B2 (en) 2002-03-28 2008-01-23 シャープ株式会社 Multilayer semiconductor device
WO2005059967A2 (en) 2003-12-17 2005-06-30 Chippac, Inc. Multiple chip package module having inverted package stacked over die
CN1700467A (en) * 2004-05-20 2005-11-23 株式会社东芝 Semiconductor device
US7629695B2 (en) * 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US7492039B2 (en) * 2004-08-19 2009-02-17 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
KR100498708B1 (en) * 2004-11-08 2005-07-01 옵토팩 주식회사 Electronic package for semiconductor device and packaging method thereof
US7456088B2 (en) * 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
KR100809701B1 (en) 2006-09-05 2008-03-06 삼성전자주식회사 Multi chip package having spacer for blocking inter-chip heat transfer
JP2008219704A (en) * 2007-03-07 2008-09-18 Olympus Imaging Corp Semiconductor device
DE102007040117A1 (en) 2007-08-24 2009-02-26 Robert Bosch Gmbh Method and engine control unit for intermittent detection in a partial engine operation
US8283570B2 (en) * 2007-12-26 2012-10-09 Panasonic Corporation Semiconductor assembly and multilayer wiring board
US8231692B2 (en) 2008-11-06 2012-07-31 International Business Machines Corporation Method for manufacturing an electronic device
KR101855294B1 (en) * 2010-06-10 2018-05-08 삼성전자주식회사 Semiconductor package
WO2012058074A2 (en) * 2010-10-28 2012-05-03 Rambus Inc. Thermal isolation in 3d chip stacks using gap structures and contactless communications
KR20120089150A (en) 2011-02-01 2012-08-09 삼성전자주식회사 Pakage On Pakage
US8503498B2 (en) * 2011-03-23 2013-08-06 Rohm Co., Ltd. Multi-beam semiconductor laser apparatus
KR101740483B1 (en) * 2011-05-02 2017-06-08 삼성전자 주식회사 Stack Packages having a Fastening Element and a Halogen-free inter-packages connector
US9728652B2 (en) * 2012-01-25 2017-08-08 Infineon Technologies Ag Sensor device and method

Also Published As

Publication number Publication date
US9418971B2 (en) 2016-08-16
CN103811430A (en) 2014-05-21
US11776945B2 (en) 2023-10-03
US20140124955A1 (en) 2014-05-08
US10490539B2 (en) 2019-11-26
US20200020677A1 (en) 2020-01-16
US20160343698A1 (en) 2016-11-24
CN103811430B (en) 2017-05-03
KR20140059696A (en) 2014-05-16
KR101531746B1 (en) 2015-07-06

Similar Documents

Publication Publication Date Title
US20230378153A1 (en) Package-on-Package Structure Including a Thermal Isolation Material
US10269763B2 (en) Package-on-package structure having polymer-based material for warpage control
US8941225B2 (en) Integrated circuit package and method for manufacturing the same
US9583474B2 (en) Package on packaging structure and methods of making same
TWI482261B (en) Three-dimensional system-in-package package-on-package structure
US7498203B2 (en) Thermally enhanced BGA package with ground ring
US11848318B2 (en) Package structure and manufacturing method thereof
US9418874B2 (en) Method of fabricating semiconductor package
KR101607989B1 (en) Package on package and method for manufacturing the same
US11417581B2 (en) Package structure
KR101101435B1 (en) Semiconductor device and manufacturing method thereof
TWI628756B (en) Package structure and its fabrication method
US10290592B2 (en) Semiconductor package, and a method for forming a semiconductor package
TWI591788B (en) Method for manufacturing electronic package
US20060091567A1 (en) Cavity-down Package and Method for Fabricating the same
KR101573311B1 (en) Semiconductor device and method for manufacturing the same
US20160163629A1 (en) Semiconductor package and method of fabricating the same
TW201822331A (en) Electronic package
JP2024046616A (en) Package structure with adhesive layer and packaging method thereof
TWI381513B (en) Chip stacked package structure and fabrication method thereof

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION