CN107039369A - Encapsulation includes the encapsulation stacking structure and its manufacture method of the encapsulation - Google Patents

Encapsulation includes the encapsulation stacking structure and its manufacture method of the encapsulation Download PDF

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Publication number
CN107039369A
CN107039369A CN201710307289.5A CN201710307289A CN107039369A CN 107039369 A CN107039369 A CN 107039369A CN 201710307289 A CN201710307289 A CN 201710307289A CN 107039369 A CN107039369 A CN 107039369A
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CN
China
Prior art keywords
encapsulation
salient point
pad
substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710307289.5A
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Chinese (zh)
Inventor
杜茂华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
Original Assignee
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Semiconductor China R&D Co Ltd, Samsung Electronics Co Ltd filed Critical Samsung Semiconductor China R&D Co Ltd
Priority to CN201710307289.5A priority Critical patent/CN107039369A/en
Publication of CN107039369A publication Critical patent/CN107039369A/en
Pending legal-status Critical Current

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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

Include the encapsulation stacking structure and the manufacture method of the encapsulation and encapsulation stacking structure of the encapsulation there is provided a kind of encapsulation.The encapsulation includes：Substrate, with first surface and back to the second surface of first surface, and including setting the first pad and the second pad that on the first surface and are separated from each other；Chip, on the first surface of substrate and is electrically connected to the first pad；Salient point, is arranged on the second pad, includes first end and second end opposite with first end of the second pad of contact；And encapsulating component, encapsulate at least a portion of chip and at least a portion of salient point, and the second end of exposure salient point.

Description

Encapsulation includes the encapsulation stacking structure and its manufacture method of the encapsulation
The application be the applying date on January 23rd, 2015, Application No. 201510036267.0, it is entitled " encapsulation including this The divisional application of the patent application of the encapsulation stacking structure and its manufacture method of encapsulation ".
Technical field
The present invention relates to the field of semiconductor packages, more particularly, being related to a kind of encapsulation includes the package stack of the encapsulation The manufacture method of stack structure and the encapsulation and encapsulation stacking structure.
Background technology
It is less and less with the size of electronic installation, by stacking multiple chips or heap in a semiconductor packages Multiple semiconductor packages are folded to realize high integration density.For example, in order to reduce circuit board area occupied, an encapsulation stacking exists Encapsulation stacking structure (package-on-package, also referred to as laminate packaging or stacked package) quilt at present in another encapsulation Widely use.The fine ratio of product and reliability for conducting a research to improve or ensure encapsulation stacking structure.
The content of the invention
It is an object of the present invention to provide the encapsulation stacking structure and the envelope that a kind of semiconductor packages includes the encapsulation The manufacture method of dress and encapsulation stacking structure.
Another object of the present invention is to provide a kind of to be favorably improved or ensure fine ratio of product and/or reliability is partly led Body encapsulation includes the encapsulation stacking structure and the manufacture method of the encapsulation and encapsulation stacking structure of the encapsulation.
There is provided one kind encapsulation, the encapsulation includes：Substrate, with first surface and back to the second surface of first surface, And including setting the first pad and the second pad that on the first surface and are separated from each other；Chip, installed in the first of substrate On surface and it is electrically connected to the first pad；Salient point, is arranged on the second pad, including the second pad of contact first end and with the The second opposite end of one end；And encapsulating component, encapsulate at least a portion of chip and at least a portion of salient point, and exposure Second end of salient point.
Substrate may include multiple second pads being separated from each other, and the encapsulation may include to be separately positioned on multiple second Multiple salient points on pad.
The encapsulation may also include the projection being arranged between chip and the first pad, and chip can be electrically connected by the projection It is connected to the first pad.
The encapsulation may also include the first bonding line that chip is electrically connected to the first pad.It is described encapsulation may also include by Chip is electrically connected to the second bonding line of salient point.
The salient point may include that the direction of first surface along a direction substantially perpendicular is sequentially stacked on many height on the second pad At least uppermost sub- salient point in salient point, the multiple sub- salient point can be exposed to the outside of encapsulating component.
The salient point may include the first son that the direction of first surface along a direction substantially perpendicular is sequentially stacked on the second pad Salient point and the second sub- salient point.
The encapsulation, which may also include, to be electrically connected to the first bonding line of the first pad by chip and is electrically connected to chip Second bonding line at the junction surface between the first sub- salient point and the second sub- salient point.
The salient point can be manufactured using wire bonder by lead key closing process.Every sub- salient point can be profit Manufactured with wire bonder by lead key closing process.
Salient point can have uneven size on the direction for be basically perpendicular to first surface.Every sub- salient point can be basic There is uneven size on the direction of first surface.
The salient point can have its be basically perpendicular to the larger size at middle part on the direction of first surface and first end and The less cylindricality of size at the second end.Every sub- salient point can have the chi at its middle part being basically perpendicular on the direction of first surface It is very little larger and it is basically perpendicular to the less cylindricality of size of the end on the direction of first surface.
The salient point can have the shape of ailhead.Every sub- salient point can have the shape of ailhead.
The salient point can be formed by gold, silver, copper or its alloy.
Second end of salient point can be less than the top surface for encapsulating component.Salient point can have more than the 80% of the height of encapsulating component Height.
Encapsulating component may include accommodate salient point the second end and size be more than salient point the second end size depression.Encapsulating Component may include the end being exposed for accommodating uppermost sub- salient point and size is recessed more than the size of the end being exposed Fall into.
The depth of depression can be no more than the half of the height of uppermost sub- salient point.
The pitch of multiple salient points can be no more than 300 μm.
It is described to encapsulate the external connection terminals that may also include the second surface for being attached to substrate.
A kind of method for manufacturing encapsulation is additionally provided, this method includes：There is provided substrate, substrate have first surface and back to The second surface of first surface and including setting on the first surface and the first pad and the second pad that are separated from each other；In base Chip on the first surface of plate, and chip is electrically connected to the first pad；Salient point is set on the second pad so that convex Point includes contacting the first end of the second pad and second end opposite with first end；With at least one of encapsulating component encapsulating chip Divide and salient point；And the part being arranged on the second end of salient point of encapsulating component is removed, to expose the second end of salient point.
Substrate may include multiple second pads being separated from each other, and being set on the second pad may include difference the step of salient point Multiple salient points are set on multiple second pads.
The step of setting salient point may include：The direction of first surface is in turn set on the second pad along a direction substantially perpendicular Many sub- salient points.
The step of setting many sub- salient points may include that the direction of first surface along a direction substantially perpendicular is set on the second pad First sub- salient point simultaneously sets the second sub- salient point on the first sub- salient point, and this method may also include：First sub- salient point is being set with setting Put between the second sub- salient point, chip is electrically connected to the first sub- salient point with bonding line.
Being set on the second pad the step of salient point may include：Using wire bonder by lead key closing process second Salient point is set on pad.
The part being arranged on the second end of salient point of component can be encapsulated with laser ablation.
A kind of encapsulation stacking structure is additionally provided, the encapsulation stacking structure includes the first encapsulation and is stacked in the first encapsulation Second encapsulation.First encapsulation may include：First substrate, with first surface and back to the second surface of first surface, and is wrapped Include the first pad and the second pad for setting and on the first surface and being separated from each other；First chip, installed in the first of substrate On surface and it is electrically connected to the first pad；Salient point, is arranged on the second pad, including the second pad of contact first end and with the The second opposite end of one end；And first encapsulating component, encapsulate the first chip at least a portion and salient point at least a portion, And the second end of exposure salient point.Second encapsulation may include：Second substrate, the with the 3rd surface and back to the 3rd surface the 4th Surface；Second chip, on the 3rd surface and is electrically connected to second substrate；Second encapsulating component, the second chip of encapsulating At least partially；And external connection member, it is attached to the 4th surface.External connection member is fixed on the salient point so that Second encapsulation is electrically connected to the first encapsulation.
First substrate may include multiple second pads being separated from each other, and the first encapsulation may include to be separately positioned on multiple second Multiple salient points on pad, the second encapsulation may include to be separately fixed at multiple external connection members on multiple salient points.
The salient point may include that the direction of first surface along a direction substantially perpendicular is sequentially stacked on many height on the second pad Salient point, external connection member can be fixed on the uppermost sub- salient point in the multiple sub- salient point.
The salient point can be manufactured using wire bonder by lead key closing process.Every sub- salient point can be profit Manufactured with wire bonder by lead key closing process.
First encapsulating component may include accommodate salient point the second end and size be more than salient point the second end size depression. External connection member may include at least a portion being arranged in the depression.
A kind of method for manufacturing encapsulation stacking structure is additionally provided, this method includes providing the first encapsulation, provides the second envelope It is filled with and by the second encapsulation stacking in the first encapsulation.The step of providing the first encapsulation may include：First substrate, substrate tool are provided Have first surface and back to first surface second surface and including set on the first surface and be separated from each other first weldering Disk and the second pad；First chip is installed on the first surface of first substrate, and the first chip is electrically connected to the first weldering Disk；Salient point is set on the second pad so that salient point includes the first end and opposite with first end second of the second pad of contact End；With at least a portion and salient point of the first encapsulating component encapsulating chip；And remove first and encapsulate component and be arranged on salient point The second end on part, to expose the second end of salient point.The step of providing the second encapsulation may include：There is provided has the 3rd surface With the second substrate on the 4th surface back to the 3rd surface；Second chip is installed on the 3rd surface of second substrate, and will Second chip is electrically connected to second substrate；At least a portion of the second chip is encapsulated with the second encapsulating component；And connect outside Connecting terminal is attached to the 4th surface of second substrate.Step of second encapsulation stacking in the first encapsulation may include：By outside Connection terminal is arranged on the salient point；And backflow is performed to external connection terminals so that external connection terminals, which turn into, to be fixed External connection member on the salient point.
First substrate may include multiple second pads being separated from each other, and set on the second pad may include the step of salient point The step of setting multiple salient points, attachment external connection terminals on multiple second pads respectively may include to adhere to multiple external connections Terminal, step of second encapsulation stacking in the first encapsulation may include multiple external connection terminals being separately positioned on multiple convex Point on.
Being set on the second pad the step of salient point may include the direction of first surface along a direction substantially perpendicular in the second pad On stack gradually many sub- salient points, the step that external connection terminals are arranged on the salient point may include external connection terminals It is arranged on the uppermost sub- salient point in the multiple sub- salient point.
The salient point is manufactured by lead key closing process using wire bonder.Pass through lead using wire bonder Every sub- salient point of bonding technology manufacture.
The step of part being arranged on the second end of salient point for removing the first encapsulating component, may include：Structure is encapsulated first The second end and size that receiving salient point is formed in part are more than the depression of the size at the second end of salient point.External connection member may include It is arranged at least a portion in the depression.
A kind of encapsulation is additionally provided, the encapsulation includes：Substrate；Chip, on substrate and electrically connects substrate；Salient point, On substrate and electrically connect substrate, and positioned at the sidepiece of chip；And encapsulating component, encapsulate at least a portion of chip With at least a portion of salient point, and exposure salient point top.
A kind of encapsulation is additionally provided, the encapsulation includes：Substrate；Chip, on substrate and electrically connects substrate；It is multiple convex Point, on substrate and electrically connects substrate, and around chip；And encapsulating component, at least the one of encapsulating chip At least a portion of each salient point in part and multiple salient points, and the top of each salient point of exposure.
A kind of encapsulation is additionally provided, the encapsulation includes：Substrate；Chip, on substrate and electrically connects substrate；Encapsulate structure Part, encapsulates at least a portion of chip；And salient point, it is arranged on substrate and is embedded in encapsulating component, wherein, encapsulate component Opening with exposure salient point.
Brief description of the drawings
By description below in conjunction with the accompanying drawings to embodiment, above and/or other aspect of the invention and advantage will become Understand and be easier to understand, in the accompanying drawings：
Fig. 1 is a kind of schematic cross sectional views for the encapsulation stacking structure for showing correlation technique；
Fig. 2 is the schematic cross sectional views for showing encapsulation stacking structure according to an exemplary embodiment of the present invention；
Fig. 3 is to show the lower envelope that the encapsulation stacking structure according to an exemplary embodiment of the present invention shown in Fig. 2 includes The schematic plan of the substrate of dress；
Fig. 4 is to show the lower envelope that the encapsulation stacking structure according to an exemplary embodiment of the present invention shown in Fig. 2 includes The partial sectional view of dress；
Fig. 5 is the schematic cross sectional views for showing the encapsulation stacking structure according to another exemplary embodiment of the present invention；
Fig. 6 is the schematic cross sectional views for showing the encapsulation stacking structure according to further example embodiment of the present invention；
Fig. 7 A to Fig. 7 F are to show that (that is, encapsulation stacking structure includes for encapsulation according to an exemplary embodiment of the present invention Lower encapsulation) manufacture method schematic cross sectional views；
Fig. 8 A to Fig. 8 E are the manufacture methods for showing the sub- salient point that encapsulation according to an exemplary embodiment of the present invention includes Schematic cross sectional views；
Fig. 8 F to Fig. 8 H are the sub- salient points for partly showing to be included according to the encapsulation of another exemplary embodiment of the present Manufacture method schematic cross sectional views；
Fig. 9 A to Fig. 9 D are to show the upper encapsulation that encapsulation stacking structure according to an exemplary embodiment of the present invention includes The schematic cross sectional views of manufacture method；
Figure 10 A to Figure 10 C are the systems for showing encapsulation stacking structure according to an exemplary embodiment of the present invention at least in part Make the schematic cross sectional views of method；And
Figure 11 A to Figure 11 F are to show the encapsulation according to another exemplary embodiment of the present invention (that is, in encapsulation stacking structure Including lower encapsulation) manufacture method schematic cross sectional views.
Embodiment
Hereinafter, exemplary embodiment will be explained by reference to accompanying drawing present inventive concept is described in detail.So And, present inventive concept can be embodied in many different forms, and should not be interpreted as being limited to described in this paper each Embodiment；On the contrary, these embodiments are provided so that the disclosure is clear and complete, and will be to the common skill in this area Art personnel fully pass on present inventive concept.In the accompanying drawings, identical reference represents identical element.In addition, each yuan Part and region are schematically shown.Thus, present inventive concept is not limited to relative size or distance shown in figure.
It will be appreciated that, although term first, second, third, etc. can be used herein come describe each element, part, Region, layer and/or part, but these elements, part, region, layer and/or part should not be limited by these terms.These arts Language is used only for distinguishing an element, part, region, layer or part with another element, part, region, layer or part. Therefore, the first element discussed below, first component, first area, first layer or Part I can be referred to as the second element, Second component, second area, the second layer or Part II, without departing from the teaching of present inventive concept.
Term used herein is in order at the purpose of description specific embodiment, and is not intended to limit present inventive concept.Such as this In used in, the " one " of singulative, " one kind ", "the", " described " are also intended to include plural form, unless in context In clearly dictate otherwise.It will be understood that, term " comprising " and/or " including ... " are when used in this specification When, illustrate in the presence of stated feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one Or more other features, entirety, step, operation, element, component and/or their group.
For the ease of description, space relative terms may be used herein to describe an element or the feature shown in figure With other elements or the relation of feature, such as " ... under ", " below ... ", " below ", " in ... top " and " above " etc..It will be appreciated that these spatial terminologies are intended to cover the shown in the figure of the device in use or in operation Different azimuth outside orientation.For example, if the device in accompanying drawing is reversed, be described as other elements or feature " under " Or the element of " lower section " will be positioned in other elements or feature " top ".Therefore, exemplary term " in ... lower section " can To cover " lower section " and " top " two kinds of orientation.Device additionally can be positioned (being rotated by 90 ° or in other orientation), and Correspondingly explain that the space being used herein is relative and describe language.
Described with reference to the sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as exemplary embodiment Exemplary embodiment.In this way, the change of the diagram shape for example caused by manufacturing technology and/or tolerance is expected.Cause Exemplary embodiment, should not be construed as limited to the given shape in region as shown here, but include example by this The deviation of vpg connection such as caused by manufacture.
Unless otherwise defined, the term (including technical term and scientific terminology) otherwise used in this manual have with The implication identical implication that those of ordinary skill in the art are generally understood that.Term defined in universaling dictionary should be explained For with the implication identical implication under background of related, and unless be defined in this manual, otherwise not They should be explained with the meaning that is Utopian or excessively formalizing.
As used herein, term "and/or" includes any and all combinations that one or more correlations are listd.
Fig. 1 is a kind of schematic cross sectional views for the encapsulation stacking structure for showing correlation technique.Reference picture 1, correlation technique Encapsulation stacking structure 10 includes the lower encapsulation 11 being stacked on one another and upper encapsulation 12.Lower encapsulation 11 and upper encapsulation 12 may each be ball bar Array (BGA) semiconductor packages.Each may include in lower encapsulation 11 and upper encapsulation 12：Substrate, with being disposed thereon following table The wire of multiple pads and a plurality of patterning being disposed therein on face；Semiconductor chip, on the upper surface of substrate And the pad on upper surface of base plate is electrically connected to by bonding line；Encapsulate component, encapsulation of semiconductor chip, bonding line and substrate At least a portion of upper surface；And multiple external connection terminals, it is attached to the pad on base lower surface.External connection terminals In can be each soldered ball.
Multiple external connection terminals 13 of upper encapsulation 12 are arranged on the upper surface of the substrate of lower encapsulation 11, not encapsulated On the pad of component encapsulating and these pads are electrically connected to, so as to realize the electrical connection between encapsulation 12 and lower encapsulation 11.With The size for the electronic installation that encapsulation stacking structure 10 is applied to is less and less and function is more and more, encapsulation stacking structure 10 Size become less and less and function is more and more so that the pitch (pitch) of external connection terminals 13 also becomes increasingly It is small.Because the external connection terminals 13 of such as soldered ball can soften in high temperature reflux and be easily deformed or cave in, therefore in outside The pitch of connection terminal 13 becomes hour, easily occurs to be crosslinked between the short circuit between external connection terminals 13, such as soldered ball.Therefore, The fine ratio of product and reliability of encapsulation stacking structure 10 can be reduced.
Encapsulation according to an exemplary embodiment of the present invention and the encapsulation including the encapsulation are hereinafter described with reference to the accompanying drawings Stacked structure.
Fig. 2 is the schematic cross sectional views for showing encapsulation stacking structure according to an exemplary embodiment of the present invention.Fig. 3 is to show The schematic plan of the substrate for the lower encapsulation that encapsulation stacking structure according to an exemplary embodiment of the present invention includes.Fig. 4 is The partial sectional view for the lower encapsulation that encapsulation stacking structure according to an exemplary embodiment of the present invention includes is shown.
Reference picture 2, encapsulation 110 according to an exemplary embodiment of the present invention is included according to an exemplary embodiment of the present Encapsulation stacking structure 100 in.Encapsulation stacking structure 100 according to an exemplary embodiment of the present invention includes the encapsulation being stacked on one another (for the ease of description, hereinafter referred to as " lower to encapsulate ") 110 and upper encapsulation 120.
Reference picture 2 is to Fig. 4, and lower encapsulation 110 includes：Substrate 111；Chip 112, on substrate 111 and is electrically connected to Substrate 111；Salient point 115, is arranged on substrate 111 and is electrically connected to substrate 111；And encapsulating component 114, encapsulate chip 112 At least a portion and salient point 115 in each at least a portion, and exposure salient point 115 in each upper end.
Substrate 111 can have the upper surface 111a that is provided with chip 112 and salient point 115 and back to upper surface 111a Lower surface 111b.Substrate 111, which can have, is provided with the chip region DA of chip 112 and the periphery outside the DA of chip region Area PA, and including the multiple first pad P1 (see Fig. 3) being arranged on the 111a of upper surface and in the DA of chip region and be arranged on Multiple second pad P2 on the 111a of upper surface and in peripherally located area PA (see Fig. 3).Substrate 111, which may also include, is arranged on following table Multiple pad (not shown) on the 111b of face and it is arranged on inside substrate 111 with by the first pad P1 and the second pad P2 connections The inner lead (not shown) of pad on to lower surface 111b.Substrate 111 can be printed circuit board (PCB) (PCB).
Although Fig. 3 shows that external zones PA surrounds chip region DA, the invention is not restricted to this.External zones PA can be set The DA at least side in chip region.Although Fig. 3 shows that multiple second pad P2 surround multiple first pad P1, of the invention Not limited to this.Multiple second pad P2 can be arranged on multiple first pad P1 at least side.
Chip 112 is inverted on substrate 111 and is electrically connected to substrate 111.In this case, chip 112 has and faced The active surface of substrate 111 and the non-active face back to substrate 111.Chip 112 utilizes the active surface and substrate for being arranged on chip 112 Multiple projections 113 between 111 multiple first pad P1 are arranged on multiple first pad P1 of substrate 111.
Salient point 115 is located in the external zones PA of substrate 111, and is arranged on each in multiple second pad P2.Each Salient point 115 includes two sub- salient points stacking gradually, i.e. the first sub- salient point 115a for being arranged on the second pad P2 and be arranged on The second sub- salient point 115b on first sub- salient point 115a.First sub- salient point 115a is encapsulated component 114 and encapsulated completely, and the second son The salient point 115b bottom contacted with the first sub- salient point 115a is encapsulated component 114 and encapsulated, and the second sub- salient point 115b top is not Component 114 is encapsulated to encapsulate and be externally exposed.That is, each salient point 115 is embedded in encapsulating component 114, and have Top (for example, top surface) exposed to the outside of encapsulating component 114.
In one exemplary embodiment, (" it can also referred to as be beaten by wire bonding using wire bonder with low cost Line ") it is each in the first sub- sub- salient point 115b of salient point 115a and second to manufacture.The first sub- sub- salient points of salient point 115a and second Each there can be uneven size (for example, width or diameter) in its height direction in 115b, that is to say, that the first son Each can have at least one full-size and at least one in its height direction in the sub- salient point 115b of salient point 115a and second Individual minimum dimension.The first sub- sub- salient point 115b of salient point 115a and second can have substantially the same height, or different height. It is each with its short transverse in the first sub- sub- salient point 115b of salient point 115a and second in one exemplary embodiment The size at middle part is larger and the less cylindricality of size at two ends in short transverse.In a further exemplary embodiment, the first son Each shape with ailhead in the sub- salient point 115b of salient point 115a and second.However, of the first sub- salient point 115a and second Each shape in salient point 115b is not particularly limited.
Each in the first sub- sub- salient point 115b of salient point 115a and second can be formed by least one of gold, silver and copper, But be not particularly limited for the material for forming the first sub- sub- salient point 115b of salient point 115a and second.
Each at least a portion at least a portion and salient point 115 of the encapsulating chip 112 of component 114 is encapsulated, to protect Protect these components is not influenceed by external environment or external impact.Encapsulating component 114 can also encapsulate multiple projections 113 and substrate 111 upper surface 111a at least a portion.As shown in Fig. 2 the not encapsulated component 114 in the non-active face of chip 112 encapsulate and It is externally exposed；However, the invention is not restricted to this, the non-active face of chip 112 can be encapsulated component 114 and encapsulate.
Encapsulating component 114 also include be used for accommodate each second sub- salient point 115b the end being exposed and size (for example, Width) be more than the second sub- salient point 115b the end being exposed size multiple depression C so that the second sub- salient point 115b has The top that the bottom and not encapsulated component 114 for being encapsulated the encapsulating of component 114 are encapsulated and be externally exposed.That is, second Sub- salient point 115b is externally exposed by the C that is recessed.
Reference picture 4, the first sub- sub- salient point 115b of salient point 115a and second have substantially the same height.It is exemplary at one In embodiment, each height having no more than 100 μm in the first sub- sub- salient point 115b of salient point 115a and second, for example, not Height more than 75 μm, the height no more than 50 μm, height no more than 25 μm, etc..Of first sub- salient point 115a and second Salient point 115b has essentially identical diameter or width.In one exemplary embodiment, of the first sub- salient point 115a and second Each diameter or width having no more than 200 μm in salient point 115b, more specifically, the diameter or width no more than 175 μm, Diameter or width no more than 150 μm, the diameter or width no more than 125 μm, the diameter or width no more than 100 μm does not surpass Cross 75 μm of diameter or width, or the diameter or width no more than 50 μm, etc..
The total height h of salient point 115BLess than the height h of encapsulating component 114ESo that the second sub- salient point 115b top surface is low In the top surface of encapsulating component 114.In one exemplary embodiment, the total height h of salient point 115BIt can be encapsulating component 114 Height hEMore than 80%, more specifically, more than 85%, more than 90% or more than 95%.In one exemplary embodiment, The total height h of salient point 115BHeight h with encapsulating component 114EBetween difference can be no more than 75 μm, for example, no more than 50 μm, no More than 25 μm, no more than 10 μm, etc..
Depression C depth DRThe half of height that can be no more than the second sub- salient point 115b, more specifically, 1/3,1/4；And can No more than the height h of encapsulating component 114E1/3, more specifically, 1/5,1/7,1/9.In one exemplary embodiment, it is recessed C depth DR50 μm, 40 μm, 30 μm, 20 μm, 10 μm, etc. can be no more than.
The pitch (that is, the distance between corresponding points on adjacent salient point 115 in multiple salient points 115) of multiple salient points 115 can be with It is small.In one exemplary embodiment, the pitch of multiple salient points 115 is no more than 300 μm, more specifically, no more than 250 μ M, no more than 200 μm, no more than 175 μm, no more than 150 μm, no more than 125 μm, no more than 100 μm, no more than 75 μm, or not More than 50 μm, etc..
Although Fig. 2 and Fig. 4 show that encapsulating component 114 includes being used to accommodate being exposed for each second sub- salient point 115b Multiple depression C of the size of the end being exposed of end and size (for example, width) more than the second sub- salient point 115b, and the Two sub- salient point 115b top surface is less than the top surface for encapsulating component 114, but the invention is not restricted to this.It is real in another exemplary Apply in example, encapsulating component only includes the end being exposed for accommodating each salient point and size (for example, width) is equal to salient point The end being exposed size through hole so that all parts (such as sidepiece) in its height of salient point and encapsulating component Contact and be encapsulated.In this case, the top surface of salient point can have the top surface identical height with encapsulating component, i.e. The top surface of salient point is flushed with encapsulating the top surface of component.In yet another exemplary embodiment, salient point, which has, protrudes past encapsulating A part for the top surface of component so that top surface of the top surface of salient point higher than encapsulating component.
Although Fig. 3 shows that each salient point 115 includes two sub- salient points, the invention is not restricted to this.Salient point can be only Including a sub- salient point or more than two sub- salient point.Can be by adjusting the size and/or the quantity of sub- salient point of every sub- salient point To adjust the whole height of salient point.
Although Fig. 2 and Fig. 4 show that lower encapsulation 110 includes multiple salient points 115 corresponding to multiple second pad P2, The invention is not restricted to this.Lower encapsulation can only include a salient point for corresponding to a second pad P2.Although Fig. 2 is shown down Encapsulation 110 includes a chip 112, but the invention is not restricted to this.Lower encapsulation can include multiple chips.
Lower encapsulation 110 may also include the outside for the multiple pad (not shown) being attached on the lower surface 111b of substrate 111 Connection terminal 116.In external connection terminals 116 can be each soldered ball.Therefore, chip 112 can be by the first pad P1, interior Multiple pads and external connection terminals 116 on portion's lead, lower surface 111b are electrically connected to external devices.In lower encapsulation 110, The component that external connection terminals 116 are not required.
Upper encapsulation 120 includes：Substrate 121, with upper surface 121a and back to upper surface 121a lower surface 121b；First Chip 122a and the second chip 122b, the first chip 122a are attached to the upper surface of substrate 121 by adhesive die attachment film 127a 121a is simultaneously electrically connected to the pad (not shown) on the upper surface 121a of substrate 121 by bonding line 128, and the second chip 122b leads to Adhesive die attachment film 127b is crossed to be attached to the first chip 122a active surface and be electrically connected to substrate by bonding line 129a and 129b Pad (not shown) on 121 upper surface 121a；Encapsulate component 124, encapsulating the first chip 122a, the second chip 122b and Bonding line 128,129a and 129b；And multiple external connection members 126 ', it is attached to the weldering on the lower surface 121b of substrate 121 Disk.
Substrate 121, which may also include, to be arranged on inside substrate 121 pad on the 121a of upper surface being connected to lower surface The inner lead (not shown) of pad on 121b.Substrate 121 can be printed circuit board (PCB) (PCB).First chip 122a and Two chip 122b can be by the pad and external connection member on the pad on the 121a of upper surface, inner lead, lower surface 121b 126 ' are electrically connected to the external devices of all following encapsulation 110.
Although Fig. 2 shows that encapsulation 120 includes two chips being arranged on by wire bonding on substrate 121, The invention is not restricted to this.Upper encapsulation may include to be inverted on substrate or be arranged at least one core on substrate by wire bonding Piece.
Multiple external connection members 126 ' are arranged on each going up in multiple salient points 115 and are electrically connected to each salient point 115, So as to realize the electrical connection between encapsulation 120 and lower encapsulation 110.First chip 122a and the second chip 122b can be by least External connection member 126 ' and salient point 115 are electrically connected to external connection terminals 116 and/or chip 112.
It is each with least one be arranged in the depression C of encapsulating component 114 in multiple external connection members 126 ' Point.Each in multiple external connection members 126 ' can be manufactured with soldered ball by flowing back, such as hereinafter in description manufacture according to this Illustrated during the method for the encapsulation stacking structure of invention exemplary embodiment.
Because lower encapsulation 110 has the salient point 115 for the outside for being exposed to encapsulating component 114 and the outside of upper encapsulation 120 connects Connection member 126 ' is arranged on salient point 115 and is electrically connected to each salient point 115, thus with the envelope of the correlation technique shown in Fig. 1 Dress stacked structure 10 is compared, and can reduce upper encapsulation 120 will be used for being formed the external connection terminal of external connection member 126 ' The size (such as thickness or width) of sub 126 (see Fig. 9 D) (such as soldered balls).Therefore, even if the external connection terminal of upper encapsulation 120 Son 126 pitch diminish, also can because of external connection terminals the smaller deformation to prevent or suppress external connection terminals of size Or the problem of short circuit between external connection terminals caused by caving in, so as to improve fine ratio of product and reliability.
The pitch of the external connection terminals 126 (see Fig. 9 D) of upper encapsulation 120 can be equal to the pitch of multiple salient points 115. In one exemplary embodiment, the pitch of external connection terminals 126 (see Fig. 9 D) is more than 300 μm, more specifically, no more than 250 μ M, no more than 200 μm, no more than 175 μm, no more than 150 μm, no more than 125 μm, no more than 100 μm, no more than 75 μm, or not More than 50 μm, etc..
Fig. 5 is the schematic cross sectional views for showing the encapsulation stacking structure according to another exemplary embodiment of the present invention.In Fig. 5 The encapsulation stacking structure 200 according to another exemplary embodiment of the present invention shown has the encapsulation described with reference picture 2 to Fig. 4 Substantially the same or similar construction of stacked structure 100, therefore same or analogous reference will be used to represent and encapsulate Element identical element in stacked structure 100, and omit detailed description.Following description will focus on encapsulation stacking In difference between structure 200 and encapsulation stacking structure 100.
Reference picture 5, lower encapsulation 210 includes：Substrate 211, with upper surface 211a and the lower surface back to upper surface 211a 211b；Chip 212, is attached to the upper surface 211a of substrate 211 by adhesive die attachment film 217 and is electrically connected by bonding line 218 Pad (not shown) onto the upper surface 211a of substrate 211；Multiple salient points 215, are arranged on substrate 211 and are electrically connected to base Plate 211；And encapsulating component 214, encapsulate chip 212 at least a portion and salient point 215 in each at least a portion with And each upper end in bonding line 218, and exposure salient point 215.
Fig. 6 is the schematic cross sectional views for showing the encapsulation stacking structure according to further example embodiment of the present invention.In Fig. 6 The encapsulation stacking structure 300 according to further example embodiment of the present invention shown has the encapsulation stacking described with reference picture 5 Substantially the same or similar construction of structure 200, therefore same or analogous reference will be used to represent and encapsulation stacking Element identical element in structure 200, and omit detailed description.Following description will focus on encapsulation stacking structure In difference between 300 and encapsulation stacking structure 200.
Reference picture 6, lower encapsulation 310 includes：Substrate 311, with upper surface 311a and the lower surface back to upper surface 311a 311b；Chip 312, is attached to the upper surface 311a of substrate 311 by adhesive die attachment film 317 and is electrically connected by bonding line 318 Pad (not shown) onto the upper surface 311a of substrate 311；Multiple salient points 315, are arranged on substrate 311 and are electrically connected to base Plate 311；And encapsulating component 314, encapsulate chip 312 at least a portion and salient point 315 in each at least a portion with And each upper end in bonding line 318, and exposure salient point 315.
Lower encapsulation 310 also includes the bonding line 319 that chip 312 is electrically connected to salient point 315.More particularly, lower encapsulation 310 include the bonding line for the connecting portion being electrically connected to chip 312 between the first sub- sub- salient point 315b of salient point 315a and second 319.Therefore, chip 312 can be electrically connected to external connection terminals 316 by least sub- salient point 315a of bonding line 319 and first. That is, it is not necessary that whole pads on the active surface of chip 312 are connected directly on the upper surface 311a of substrate 311 Pad, but at least one pad on the active surface of chip 312 can be connected to salient point 315.It therefore, it can reduce substrate The quantity and wiring density of 311 pad.
Fig. 7 A to Fig. 7 F are to show encapsulation according to an exemplary embodiment of the present invention (for example, being wrapped in encapsulation stacking structure 100 The lower encapsulation 110 included) manufacture method schematic cross sectional views.Hereinafter by reference picture 7A to Fig. 7 F descriptions according to the present invention The manufacture method of the encapsulation of exemplary embodiment.
Chip 112 chip 112 and is electrically connected to substrate by reference picture 7A there is provided substrate 111, and on substrate 111 111.Specifically, substrate 111 has the upper surface 111a and the following table back to upper surface 111a for being provided with chip 112 Face 111b, and with the chip region DA and the external zones PA outside the DA of chip region for being provided with chip 112.Utilize setting Multiple projections 113 between the active surface of chip 112 and multiple first pad P1 (see Fig. 3) of substrate 111 pacify chip 112 On multiple first pad P1 of substrate 111.Projection 113 can be solder projection, Au projections or conducting polymer flexible convex Block.
Reference picture 7B, in being located on the 111a of upper surface and multiple second pad P2 in external zones PA for substrate 111 First sub- salient point 115a is set on (see Fig. 3) and the first sub- salient point 115a is electrically connected to substrate 111.Can be with low cost utilization Wire bonder is each in first sub- salient point 115a to be manufactured on substrate 111 by lead key closing process.
Fig. 8 A to Fig. 8 E are the manufacture methods for showing the sub- salient point that encapsulation according to an exemplary embodiment of the present invention includes Schematic cross sectional views.Described referring to Fig. 8 A to Fig. 8 E with low cost using wire bonder by wire bonding come in base The first sub- salient point 115a illustrative processes are manufactured on plate 111.Reference picture 8A, is split extending beyond with the method for spark discharge The tail end formation ball 31 of the wire 30 of such as gold, silver or copper of the outlet of knife 20.Reference picture 8B so that wire 30 relative to Chopper 20 is moved, to cause ball 31 to come close to or in contact with chopper 20.Reference picture 8C, makes chopper 20 and wire 30 together towards substrate 111 the second pad P2 motions so that ball 31 contacts the second pad P2, then apply heat and by chopper 20 by substrate 111 Apply bonding force, while chopper 20 vibrates under ultrasonication, so as to form solder joint 31 '.Reference picture 8D, chopper 20 is lifted simultaneously And wire clamp (not shown) is stayed open, to send out one section of tailfiber.Reference picture 8E, wire clamp is closed, and chopper 20 is transported upwards It is dynamic, with by stretching constriction effect cut-out wire 30, so as to form the first sub- salient point 115a.The the first sub- salient point so manufactured 115a can have the shape of ailhead.
First sub- salient point 115a of the method manufacture described by referring to Fig. 8 A to Fig. 8 E may have tinsel tail.Can Remove line tail to improve the first sub- salient point 115a quality and reliability by other technique.
Fig. 8 F to Fig. 8 H are the sub- salient points for partly showing to be included according to the encapsulation of another exemplary embodiment of the present Manufacture method schematic cross sectional views.Lead is utilized with low cost referring to Fig. 8 A to Fig. 8 D and Fig. 8 F to Fig. 8 H descriptions Bonder manufactures the first sub- salient point 115a another exemplary technique by wire bonding on substrate 111.Join above It is described in detail according to Fig. 8 A to Fig. 8 D and solder joint 31 ' is formed on the second pad P2 of substrate 111 and then in chopper 20 and solder joint 31 ' Between keep predetermined length tailfiber technique, will not be repeated here.Then, reference picture 8F and Fig. 8 G, chopper 20 is along relative Move and moved towards the side of solder joint 31 ' slightly in the direction of the level of substrate 111 so that chopper 20 comes close to or in contact with solder joint 31 ', and the wire of the top of butt welding point 31 ' heats and applies pressure.Then, reference picture 8G and Fig. 8 H, chopper 20 is moved upwards, And close wire clamp, to cut off wire 30, so as to form the first sub- salient point 115a.The the first sub- salient point 115a so manufactured can Shape with ailhead.By referring to the first sub- salient point 115a of Fig. 8 A to Fig. 8 D and Fig. 8 F to Fig. 8 H method manufactures described There may be tinsel tail.Line tail can be removed by other technique to improve the first sub- salient point 115a quality and reliable Property.
Reference picture 7C, the first sub- salient point 115a it is each on set the second sub- salient point 115b.For setting the second son convex Point 115b technique can be substantially the same with the first sub- salient point 115a described above with reference to Fig. 8 A to Fig. 8 H manufacturing process Or it is similar, therefore it is not repeated that it is described in detail herein.
When using wire bonder by a diameter of 50 μm of wire according to Fig. 8 A to Fig. 8 E in the technique that shows or Fig. 8 A The technique that is shown into Fig. 8 D and Fig. 8 F to Fig. 8 H is manufactured during sub- salient point, can obtain width or it is a diameter of 100 μm -150 μm, Highly it is at most 75 μm of sub- salient point.If salient point includes the two sub- salient points so manufactured, the pitch of the salient point can be 200μm-250μm.In this case, encapsulating component 114 can have 150 μm of height hE。
When using wire bonder by a diameter of 25 μm of wire according to Fig. 8 A to Fig. 8 E in the technique that shows or Fig. 8 A The technique shown into Fig. 8 D and Fig. 8 F to Fig. 8 H is manufactured during sub- salient point, can obtain width or a diameter of 50 μm -70 μm, high Degree is at most 30 μm of sub- salient point.If salient point includes the five sub- salient points so manufactured, the pitch of the salient point can be 100 μm-150μm.In this case, encapsulating component 114 can have 150 μm of height hE。
Therefore, the size of sub- salient point can be adjusted by the diameter of adjustment at least wire, and salient point can be adjusted accordingly Size and pitch.
Although described above is the chip 112 first on substrate 111, then salient point 115 is set, and the present invention is not It is limited to this.That is, the technique of the setting salient point 115 of reference picture 7B and Fig. 7 C descriptions can be first carried out, ginseng is then performed The technique of chip 112 on substrate 111 described according to Fig. 7 A.
Reference picture 7D, with encapsulating component 114 encapsulating chip 112, projection 113 and including the first sub- salient point 115a and second Sub- salient point 115b salient point 115.In one exemplary embodiment, the product shown in Fig. 7 C can be placed on mould In cavity, the encapsulating component precursor of such as epoxy molding plastic (EMC) is then filled in the cavity of mould, encapsulating component is made afterwards Precursor cures, to form encapsulating component 114.Here, each entirety in encapsulating component 114 encapsulating salient point 115.Chip 112 The not encapsulated component 114 in non-active face encapsulate and be externally exposed；However, the invention is not restricted to this, chip 112 it is non-active Face can be encapsulated component 114 and encapsulate.
Reference picture 7E, the part being arranged on each second sub- salient point 115b for removing encapsulating component 114 is multiple to be formed Be recessed C, so that each second sub- salient point 115b of exposure.Therefore, the second sub- salient point 115b, which has, is encapsulated under the encapsulating of component 114 The top that portion and not encapsulated component 114 are encapsulated and be externally exposed.In one exemplary embodiment, using laser ablation Encapsulate the part of component 114.Here, each size in multiple depression C can be more than each second sub- salient point 115b quilt The size of exposed end.
External connection terminals are set on reference picture 7F, multiple pad (not shown) on the lower surface 111b of substrate 111 116, thus complete lower encapsulation 110.In external connection terminals 116 can be each soldered ball.In one exemplary embodiment, Solder is applied on each in multiple pads on the lower surface 111b of substrate 111, then by solder is performed backflow with Form external connection terminals 116.
Fig. 9 A to Fig. 9 D are to show the upper encapsulation that encapsulation stacking structure 100 according to an exemplary embodiment of the present invention includes The schematic cross sectional views of 120 manufacture method.Hereinafter reference picture 9A to Fig. 9 D descriptions are implemented according to the present invention is exemplary The manufacture method for the upper encapsulation 120 that the encapsulation stacking structure 100 of example includes.
Reference picture 9A installs the first chip 122a and the second chip 122b on substrate 121 and incited somebody to action there is provided substrate 121 First chip 122a and the second chip 122b are electrically connected to substrate 121.Specifically, substrate 121 has upper surface 121a and the back of the body To upper surface 121a lower surface 121b.First chip 122a is attached to the upper table of substrate 121 by adhesive die attachment film 127a Face 121a and the active surface that the second chip 122b is attached to the first chip 122a by adhesive die attachment film 127b, then, pass through First chip 122a is electrically connected to pad (not shown) on the upper surface 121a of substrate 121 and by bonding by bonding line 128 Second chip 122b is electrically connected to the pad (not shown) on the upper surface 121a of substrate 121 by line 129a and 129b.
Reference picture 9B, the first chip 122a, the second chip 122b and bonding line 128,129a are encapsulated with encapsulating component 124 And 129b.In one exemplary embodiment, the product shown in Fig. 9 A can be placed in the cavity with mould, Ran Hou The encapsulating component precursor of such as epoxy molding plastic (EMC) is filled in the cavity of mould, encapsulating component precursor cures are made afterwards, with shape Into encapsulating component 124.
The outer of such as soldering paste is set on reference picture 9C, multiple pad (not shown) on the lower surface 121b of substrate 121 Portion connection terminal precursor S.Specifically, the mask M with multiple opening OP is placed on the lower surface 121b of substrate 121, it is many It is each in multiple pads on the lower surface 121b for each corresponding to substrate 121 in individual opening OP.Then, using instrument T External connection terminals precursor S is applied in each opening OP.Then, mask M is removed so that external connection terminals precursor S retains On multiple pads on the lower surface 121b of substrate 121.
Reference picture 9D, to the external connection terminals precursor S being attached on multiple pads on the lower surface 121b of substrate 121 Backflow is performed, to form the external connection terminals 126 of such as soldered ball.Thus, 120 are encapsulated in completion.
Figure 10 A to Figure 10 B are to show encapsulation stacking structure 100 according to an exemplary embodiment of the present invention at least in part The schematic cross sectional views of manufacture method.Reference picture 10A to Figure 10 B is hereinafter described according to an exemplary embodiment of the present invention The manufacture method of encapsulation stacking structure 100.
Reference picture 10A, scaling powder F is attached to each external connection terminals 126 of upper encapsulation 120.Implement exemplary In example, a part for each external connection terminals 126 of upper encapsulation 120 can be immersed in scaling powder, to cause scaling powder F attached Each external connection terminals 126.
Reference picture 10B, each external connection terminals 126 for adhering to fluxing agent F is arranged on every in multiple salient points 115 On individual, to cause between the externally-located connection terminals 126 of scaling powder F and salient point 115.That is, in the outside of upper encapsulation 120 In the state of connection terminal 126 is aligned and connected with the salient point 115 of lower encapsulation 110, upper encapsulation 120 is stacked on lower encapsulation 110 On.
The external connection terminals 126 of such as soldered ball of upper encapsulation 120 are performed backflow so that external connection by reference picture 10C Terminal 126 turns into external connection member 126 ' and arrives salient point 115 to be permanently connected and (such as be welded to), is achieved in encapsulation 120 and it is lower encapsulation 110 between mechanical connection and electrically connect.During backflow is performed to external connection terminals 126, fusing External connection terminals 126 at least a portion enter encapsulating component 114 depression C in.Therefore, depression C side wall can be used Make stop fusing external connection terminals 126 motion block piece, with prevent fusing external connection terminals 126 with it is adjacent The external connection terminals 126 of fusing are contacted and short-circuit.
Thus, complete to include the encapsulation stacking structure 100 of lower encapsulation 110 and upper encapsulation 120.
Because lower encapsulation 110 has the salient point 115 for the outside for being exposed to encapsulating component 114 and the outside of upper encapsulation 120 connects Connection member 126 ' is arranged on salient point 115 and is electrically connected to each salient point 115, thus with the envelope of the correlation technique shown in Fig. 1 Dress stacked structure 10 is compared, and can reduce upper encapsulation 120 will be used for being formed the external connection terminal of external connection member 126 ' The size (such as thickness or width) of sub 126 (such as soldered balls).Therefore, even if the section of the external connection terminals 126 of upper encapsulation 120 Away from diminishing, it can also cause because of the smaller deformation to prevent or suppress external connection terminals of size or cave in of external connection terminals External connection terminals between short circuit the problem of, so as to improve fine ratio of product and reliability.
Furthermore, it is possible to sub- salient point 115 is easily manufactured by lead key closing process using wire bonder with low cost, Therefore encapsulation 110 according to an exemplary embodiment of the present invention and the encapsulation stacking structure 100 including the encapsulation 110 can have low Manufacturing cost.
The difference of encapsulation stacking structure 100 of the encapsulation stacking structure 200 shown in Fig. 5 with being shown in Fig. 2 is essentially consisted in Chip 212 is attached to the upper surface 211a of substrate 211 by adhesive die attachment film 217 and is electrically connected to substrate by bonding line 218 Pad on 211 upper surface 211a.Substrate 211 and the chip 212 on substrate 211 can be provided first.Specifically, Substrate 211 with the upper surface 211a and lower surface 211b back to upper surface 211a is provided first, passes through adhesive die attachment film 217 Chip 212 is attached to the upper surface 211a of substrate 211, chip 212 is then electrically connected to by substrate 211 by bonding line 218 Upper surface 211a on pad.It is then possible to using substantially the same or similar to the technique that reference picture 7B to Figure 10 C is described Technique manufacture encapsulation stacking structure 200.
Figure 11 A to Figure 11 F are to show the encapsulation according to another exemplary embodiment of the present invention (for example, encapsulation stacking structure The 300 lower encapsulation 310 included) manufacture method schematic cross sectional views.Hereinafter reference picture 11A to Figure 11 F is described According to the manufacture method of the encapsulation of another exemplary embodiment of the present invention.
Reference picture 11A is there is provided substrate 311, and the chip 312 on substrate 311.Specifically, substrate 311 has upper The surface 311a and lower surface 311b back to upper surface 311a.Chip 312 is attached to by substrate 311 by adhesive die attachment film 317 Upper surface 311a.
Reference picture 11B, first is set on the multiple second pad (not shown) being located on the 311a of upper surface of substrate 311 Sub- salient point 315a.First son can be manufactured on substrate 311 by lead key closing process using wire bonder with low cost It is each in salient point 315a.Above reference picture 8A to Fig. 8 H describes the first sub- salient point 115a manufacture method, for Substrate 311 sets the first sub- salient point 315a technique can be with the first sub- salient point 115a's described above with reference to Fig. 8 A to Fig. 8 H Manufacturing process is substantially the same or similar, therefore is no longer described in detail in first sub- salient point 315a of the setting of substrate 311 herein Process.Then, pad chip 312 being electrically connected on the upper surface 311a of substrate 311 by bonding line 318 (does not show Go out), and chip 312 is electrically connected to by bonding line 319 first sub- salient point 315a top surface.Selectively, can be first Chip 312 is electrically connected to and in substrate 311 by pad (not shown) on the upper surface 311a of substrate 311 by bonding line 318 Be located at upper surface 311a on multiple second pad (not shown) on set the first sub- salient point 315a, then pass through bonding line 319 are electrically connected to chip 312 first sub- salient point 315a top surface.
Reference picture 11C, the first sub- salient point 315a it is each on set the second sub- salient point 315b.For setting the second son convex Point 315b technique can be substantially the same with the first sub- salient point 115a described above with reference to Fig. 8 A to Fig. 8 H manufacturing process Or it is similar, therefore it is not repeated that it is described in detail herein.Therefore, bonding line 319 is electrically connected to the first sub- salient point 315a and Connecting portion between two sub- salient point 315b.
Reference picture 11D, with encapsulating component 314 encapsulating chip 312, bonding line 318,319 and including the first sub- salient point The sub- salient point 315b of 315a and second salient point 315.The offer bag that the technique of encapsulating component 314 can be described with reference picture 7D is provided The technique for sealing component 114 is substantially the same or similar, therefore no longer describes the work for providing encapsulating component 314 in detail herein Skill.
Reference picture 11E, the part being arranged on each second sub- salient point 315b for removing encapsulating component 314 is multiple to be formed Be recessed C, so that each second sub- salient point 315b of exposure.Therefore, the second sub- salient point 315b, which has, is encapsulated under the encapsulating of component 314 The top that portion and not encapsulated component 314 are encapsulated and be externally exposed.In one exemplary embodiment, using laser ablation Encapsulate the part of component 314.Here, each size in multiple depression C can be more than each second sub- salient point 115b quilt The size of exposed end.
External connection terminals are set on reference picture 11F, multiple pad (not shown) on the lower surface 311b of substrate 311 316, thus complete lower encapsulation 310.In external connection terminals 316 can be each soldered ball.In one exemplary embodiment, Solder is applied on each in multiple pads on the lower surface 311b of substrate 311, then by solder is performed backflow with Form external connection terminals 316.
Substantially the same or similar technique of the technique described to reference picture 10A to Figure 10 C can be utilized to manufacture in Fig. 6 The encapsulation stacking structure 300 shown.
Because encapsulation according to an exemplary embodiment of the present invention has the salient point for the outside for being exposed to its encapsulating component and will The external connection member for stacking another encapsulation on the package may be provided on salient point and be electrically connected to each salient point, so Compared with the encapsulation stacking structure of correlation technique, can reduce another encapsulation will be used for form external connection member The size of external connection terminals (such as soldered ball).Therefore, even if the pitch of the external connection terminals of another encapsulation diminishes, It can connect because of the smaller deformation or the caused outside that caves in prevent or suppress external connection terminals of size of external connection terminals The problem of short circuit between connecting terminal, so as to improve fine ratio of product and reliability.
Furthermore, it is possible to easily be manufactured according to the present invention by lead key closing process using wire bonder with low cost Salient point in the encapsulation of exemplary embodiment, therefore encapsulation according to an exemplary embodiment of the present invention and the encapsulation including the encapsulation Stacked structure can have low manufacturing cost.
Although being specifically illustrated with reference to the exemplary embodiment of the present invention and describing the present invention, those skilled in the art It should be understood that without departing from the spirit and scope of the present invention, the various changes in formal and details can be made.

Claims (9)

1. one kind encapsulation, it is characterised in that the encapsulation includes：
Substrate, with first surface and back to the second surface of first surface, and including setting on the first surface and each other Separated the first pad and the second pad；
Chip, on the first surface of substrate and is electrically connected to the first pad；
Salient point, is arranged on the second pad, includes first end and second end opposite with first end of the second pad of contact, its In, salient point is sequentially stacked on using wire bonder by the direction of lead key closing process first surface along a direction substantially perpendicular Many sub- salient points on second pad；And
Component is encapsulated, at least a portion of chip and at least a portion of salient point, and the second end of exposure salient point is encapsulated.
2. encapsulation according to claim 1, it is characterised in that substrate includes multiple second pads being separated from each other, and The encapsulation includes the multiple salient points being separately positioned on multiple second pads.
3. encapsulation according to claim 1, it is characterised in that at least uppermost sub- salient point in the multiple sub- salient point Exposed to the outside of encapsulating component.
4. encapsulation according to claim 1, it is characterised in that salient point has on the direction for be basically perpendicular to first surface Uneven size.
5. encapsulation according to claim 1, it is characterised in that top surface of the second end of salient point less than encapsulating component.
6. encapsulation according to claim 1, it is characterised in that encapsulating component includes accommodating the second end of salient point and size is big In the depression of the size at the second end of salient point.
7. a kind of method for manufacturing encapsulation, it is characterised in that including：
Substrate is provided, substrate have first surface and back to first surface second surface and including setting on the first surface simultaneously And the first pad and the second pad being separated from each other；
The chip on the first surface of substrate, and chip is electrically connected to the first pad；
Using wire bonder by the direction of lead key closing process first surface along a direction substantially perpendicular on the second pad successively Ground stacks many sub- salient points to set salient point so that salient point includes the first end and opposite with first end the of the second pad of contact Two ends；
With at least a portion and salient point of encapsulating component encapsulating chip；And
The part being arranged on the second end of salient point of encapsulating component is removed, to expose the second end of salient point.
8. a kind of encapsulation stacking structure, it is characterised in that including the first encapsulation and the second encapsulation being stacked in the first encapsulation,
First encapsulation includes：
First substrate, with first surface and back to the second surface of first surface, and including set on the first surface and The first pad and the second pad being separated from each other；
First chip, on the first surface of substrate and is electrically connected to the first pad；
Salient point, is arranged on the second pad, includes first end and second end opposite with first end of the second pad of contact, its In, salient point is sequentially stacked on using wire bonder by the direction of lead key closing process first surface along a direction substantially perpendicular Many sub- salient points on second pad；And
First encapsulating component, encapsulates at least a portion of the first chip and at least a portion of salient point,
And the second end of exposure salient point,
Second encapsulation includes：
Second substrate, with the 3rd surface and the 4th surface back to the 3rd surface；
Second chip, on the 3rd surface and is electrically connected to second substrate；
Second encapsulating component, encapsulates at least a portion of the second chip；And
External connection member, is attached to the 4th surface,
Wherein, external connection member is fixed on the salient point so that the second encapsulation is electrically connected to the first encapsulation.
9. it is a kind of manufacture encapsulation stacking structure method, it is characterised in that including provide first encapsulation, provide second encapsulation and By the second encapsulation stacking in the first encapsulation,
Wherein there is provided include the step of the first encapsulation：
There is provided first substrate, substrate have first surface and back to first surface second surface and including being arranged on first surface The first pad and the second pad upper and be separated from each other；
First chip is installed on the first surface of first substrate, and the first chip is electrically connected to the first pad；
Using wire bonder by the direction of lead key closing process first surface along a direction substantially perpendicular on the second pad successively Ground stacks many sub- salient points to set salient point so that salient point includes the first end and opposite with first end the of the second pad of contact Two ends；
With at least a portion and salient point of the first encapsulating component encapsulating chip；And
The first part being arranged on the second end of salient point for encapsulating component is removed, to expose the second end of salient point,
Wherein there is provided include the step of the second encapsulation：
Second substrate with the 3rd surface and the 4th surface back to the 3rd surface is provided；
Second chip is installed on the 3rd surface of second substrate, and the second chip is electrically connected to second substrate；
At least a portion of the second chip is encapsulated with the second encapsulating component；And
External connection terminals are attached to the 4th surface of second substrate；
Wherein, step of second encapsulation stacking in the first encapsulation is included：
External connection terminals are arranged on the salient point；And
Backflow is performed to external connection terminals so that external connection terminals turn into the external connection structure being fixed on the salient point Part.
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