CN102738094B - Semiconductor packaging structure for stacking and manufacturing method thereof - Google Patents

Semiconductor packaging structure for stacking and manufacturing method thereof Download PDF

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Publication number
CN102738094B
CN102738094B CN201210167921.8A CN201210167921A CN102738094B CN 102738094 B CN102738094 B CN 102738094B CN 201210167921 A CN201210167921 A CN 201210167921A CN 102738094 B CN102738094 B CN 102738094B
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substrate
packaging structure
semiconductor packaging
interposer substrate
chip
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CN102738094A (en
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沈明宗
鄚智仁
张惠珊
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

The invention discloses a semiconductor packaging structure for stacking and a manufacturing method thereof. The semiconductor packaging structure comprises a bottom substrate, a chip, an annular switchover substrate and packaging colloid. The bottom substrate is provided with a plurality of welding pads and a chip bearing area; the chip is fixedly arranged on the chip bearing area of the bottom substrate; a plurality of switchover assemblies and an opening are arranged on the annular switchover substrate; the switchover assemblies surround the opening and are electrically connected with the welding pads of the bottom substrate; the packaging colloid is filled in a gap between the bottom substrate and the annular switchover substrate, and is filled in the opening of the annular switchover substrate; and the packaging colloid in the opening is exposed to one top surface of the chip. With the adoption of the annular switchover substrate, the upper side and the lower side of a packaged body are slightly different in coefficient of thermal expansion, so that the warping rate is relatively lowered.

Description

For stacking semiconductor packaging structure and manufacture method thereof
Technical field
The invention relates to a kind of for stacking semiconductor packaging structure and manufacture method thereof, relate to especially a kind of utilize annular interposer substrate reduce warpage defect for stacking semiconductor packaging structure and manufacture method thereof.
Background technology
Now, semiconductor packaging industry is in order to meet the demand of various high-density packages, develop the package design of various different types gradually, wherein various different system in package (system in package, SIP) design concept is usually used in framework high-density packages product.Generally speaking, system in package can be divided into stacked package body (package in package, PIP) etc. in multi-chip module (multi chip module, MCM), stacked package body (POP) and packaging body.Described multi-chip module (MCM) refers to lays several chip on the same substrate, after chip is set, recycle same packing colloid and embed all chips, and stacked chips (stacked die) encapsulation or chip (side-by-side) encapsulation side by side can be subdivided into again according to chip arrangement.Moreover, described stacked package body (POP), its structure refers to and first completes the first packaging body that has substrate, then again in upper surface another second complete packaging body stacking of the first packaging body, second packaging body is electrically connected on the substrate of the first packaging body through suitable adapter assembly (as tin ball), thus becomes a composite package structure.In comparison, in described packaging body, the structure of stacked package body (PIP) is then utilize another packing colloid to be embedded together by the element of the second packaging body, adapter assembly and the first packaging body etc. to be fixed on the substrate of the first packaging body, thus becomes a composite package structure.
In the structure of existing stacked package body (POP), the substrate of the first packaging body (lower package body) bottom it is generally tellite, and packing colloid is generally the epoxy resin base material doped with solid filling, and be utilize transfer casting (transfer molding) technique to make.In recent years, in order to meet the lightening requirement of electronic product, the thickness of the lower package body of existing stacked package body (POP) encapsulating structure gradually by slimming to 350 micron (μm) below.But, when the thickness of lower package body reduces gradually, the overall construction intensity of lower package body also can be weakened gradually, and more easily because thermal coefficient of expansion (the coefficient of thermal expansion between tellite and packing colloid, CTE) there are differences and have thermal stress effect to pull, thus producing the phenomenon of warpage (warpage).Above-mentioned warping phenomenon normally forms warpage towards tellite at periphery by packing colloid.Simultaneously, the thinning thermal diffusivity of chip that also can make of integral thickness due to lower package body is deteriorated, therefore when the heat energy of chip cannot externally be derived timely and effectively, above-mentioned warping phenomenon can become more obvious, packing colloid or tellite even can be caused time serious to produce slight crack (crack), and then significantly affect the production reliability of lower package body and the useful life of stacked package body (POP).
Therefore, be necessary to provide a kind of for stacking semiconductor packaging structure, to solve the problem existing for prior art.
Summary of the invention
In view of this, the invention provides a kind of for stacking semiconductor packaging structure and manufacture method thereof, to solve warpage existing for existing stacked package body (POP) technology and heat dissipation problem.
Main purpose of the present invention is to provide a kind of for stacking semiconductor packaging structure and manufacture method thereof, it sets up an annular interposer substrate in the lower package body of stacked package body (POP), and packing colloid is filled between substrate and annular interposer substrate, to keep the upper and lower sides of lower package body to have less thermal expansion coefficient difference as far as possible when reducing integral thickness, relatively to reduce the probability producing warpage, and then improve production reliability and the useful life of lower package body.
Secondary objective of the present invention is to provide a kind of for stacking semiconductor packaging structure and manufacture method thereof, wherein the opening part of annular interposer substrate can set up a fin, the end face of the hot contact chip of fin, and described fin also can have several ribs, several corner position is extended to by the opening part of annular interposer substrate, therefore can rapidly the heat energy that chip produces upwards and outwards be derived, and then be conducive to improving the radiating efficiency of lower package body and increasing the structural strength of annular interposer substrate, the probability of warpage is produced relatively to reduce Yin Gaowen.
For reaching aforementioned object of the present invention, one embodiment of the invention provides a kind of for stacking semiconductor packaging structure, and it comprises: a substrate, a chip, an annular interposer substrate and a packing colloid.Described substrate has a upper surface and a lower surface, and described upper surface has several weld pad and a chip bearing district.Described chip is fixedly arranged on the chip bearing district of described substrate.Described annular interposer substrate has several adapter assembly, several connection pad and an opening, described adapter assembly is located at a lower surface of described annular interposer substrate, described connection pad is located at a upper surface of described annular interposer substrate, described opening runs through described annular interposer substrate, and described adapter assembly is centered around the surrounding of described opening and is electrically connected the weld pad of described substrate.Described packing colloid is filled in the gap that formed between described substrate and annular interposer substrate, and be filled in the opening of described annular interposer substrate, and coated described chip and adapter assembly, the packing colloid in wherein said opening exposes an end face of described chip.
Moreover one embodiment of the invention provides a kind of manufacture method for stacking semiconductor packaging structure.First, provide a substrate, described substrate has a upper surface and a lower surface, and described upper surface has several weld pad and a chip bearing district.Then, a chip is fixedly arranged on the chip bearing district of described substrate.Then, one annular interposer substrate is provided, and the weld pad of described substrate is electrically connected by several adapter assemblies of a lower surface of described annular interposer substrate, wherein said annular interposer substrate offers an opening, described adapter assembly is centered around around described opening, and a upper surface of described annular interposer substrate is provided with several connection pad.And, one packing colloid is inserted in the gap formed between described substrate and annular interposer substrate and in the opening of described annular interposer substrate, the coated described chip of described packing colloid and adapter assembly, and the packing colloid in described opening exposes an end face of described chip.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:
Accompanying drawing explanation
Fig. 1 is the cutaway view of the upper and lower packaging body of one embodiment of the invention stacked package body.
Fig. 2 is the cutaway view of the upper and lower packaging body of another embodiment of the present invention stacked package body.
Fig. 3 is the cutaway view of the upper and lower packaging body of further embodiment of this invention stacked package body.
Fig. 3 A is the top view of the lower package body of Fig. 3 of the present invention.
Fig. 4 is the cutaway view of the upper and lower packaging body of yet another embodiment of the invention stacked package body.
Fig. 5 A, 5B and 5C are the schematic flow sheet of Fig. 1 of the present invention for the manufacture method of stacking semiconductor packaging structure (lower package body).
Fig. 6 A and 6B is the schematic flow sheet of Fig. 3 of the present invention for the manufacture method of stacking semiconductor packaging structure (lower package body).
Embodiment
The explanation of following embodiment is graphic with reference to what add, can in order to the specific embodiment implemented in order to illustrate the present invention.Moreover, the direction term that the present invention mentions, such as " on ", D score, "front", "rear", "left", "right", " interior ", " outward " or " side " etc., be only the direction with reference to annexed drawings.Therefore, the direction term of use is in order to illustrate and to understand the present invention, and is not used to limit the present invention.
Please refer to shown in Fig. 1, first embodiment of the invention be mainly used in a lower package body 100 as stacked type packaging body (POP) for stacking semiconductor packaging structure, and in order in conjunction with packaging body 200 on, hereinafter, describedly namely lower package body 100 is directly called for stacking semiconductor packaging structure.In the present embodiment, described lower package body 100 comprises: substrate 10, chip 11, annular interposer substrate 12 and a packing colloid 13.The present invention is by hereafter describing the detail structure of the present embodiment above-mentioned each element, assembled relation and operation principles thereof one by one in detail.
Please refer to shown in Fig. 1, the substrate 10 of one embodiment of the invention can be selected from the tellite without core layer (coreless) of thickness between 50 to 200 μm (micron) or be selected from pliability film substrate (flexible tape substrate), such as to be selected from thickness be the additional layers without core layer (build-up) tellite (comprising 4 layers of circuit layer) of 150 or 180 μm or thickness is the pliability film substrate of 64 μm, but is not limited to this.Described substrate 10 is not had a core layer and will be conducive to relatively reducing its substrate thickness.Described substrate 10 has a upper surface and a lower surface, and the surface circuit of described upper surface is exposed several weld pad 101 and a chip bearing district 102.Described weld pad 101 arranges on the upper surface in matrix (array) shape usually.Described chip bearing district 102 refers to a middle section of described upper surface, in described chip bearing district 102, be usually also distributed with several weld pad 101.The surface circuit of described lower surface is also exposed several weld pad (sign), and has several Metal Ball 103, with the electric terminal as the I/O of described substrate 10 by the weld pad solder bond of these lower surfaces.
Please refer to shown in Fig. 1, the chip 11 of one embodiment of the invention can be various semiconductor chip, such as high frequency chip, CPU (CPU) chip or memory body chip (as DRAM or FLASH) etc., but is not limited.Described chip 11 can be the form of flip-chip (flip chip) or the form of routing chip (wire bonding chip).For flip-chip, the active surface of described chip 11 down, and by several projection 111 solder bond and be fixedly arranged on the weld pad 101 in chip bearing district 102 of described substrate 10.A underfill (underfill) 112 can be filled with between described chip 11 and the upper surface of described substrate 10, but also can be omitted.The thickness of described chip 11 can between 0.1 to 0.04mm, such as, be 0.1,0.08,0.06,0.05 or 0.04 etc.Described projection 111 can be selected from tin projection (bumps), golden projection or copper post projection (Cu pillar bumps) etc., and the height of described projection 111 is about 30 to 50 μm, such as, be 40 μm.
Please refer to shown in Fig. 1, the annular interposer substrate 12 of one embodiment of the invention can be selected from thickness between 100 to 150 μm and the tellite of tool core layer, such as be selected from the tellite without core layer (comprising 2 layers of circuit layer) that thickness is 140 μm, but be not limited to this.Described annular interposer substrate 12 has core layer and under less substrate thickness, guarantees that it has enough structural strengths by being conducive to.The surface circuit of a lower surface of described annular interposer substrate 12 is exposed several weld pad (sign), and have several adapter assembly 121 by the weld pad solder bond of these lower surfaces, described adapter assembly 121 is such as tin projection, golden projection or copper post projection etc., the height of described adapter assembly 121 is about 15 to 25 μm, such as, be 20 μm.
Moreover, described annular interposer substrate 12 offers an opening 122, described opening 122 runs through described annular interposer substrate 12, and correspond to described chip bearing district 102 and chip 11, and the length and width size (such as 11 × 11mm) of described opening 122 is obviously greater than the length and width size (such as 10 × 10mm) of described chip bearing district 102 or described chip 11.Described adapter assembly 121 is centered around the surrounding of described opening 122 and is electrically connected the weld pad 101 of described substrate 10.The surface circuit of one upper surface of described annular interposer substrate 12 is separately exposed several connection pad 123, and the opening diameter of described connection pad 123 is about 0.2mm, and its spacing is between 0.3 to 0.085mm, such as, be 0.3,0.2,0.15,0.1 or 0.085mm etc.
Please refer to shown in Fig. 1, the packing colloid 13 of one embodiment of the invention is filled in the gap 14 that formed between described substrate 10 and annular interposer substrate 12, and be filled in the opening 122 of described annular interposer substrate 12, and coated described chip 11 and adapter assembly 121.The height in described gap 14 is about 15 to 25 μm, such as, be 20 μm.Be positioned at a upper surface of the packing colloid 13 of described opening 122 and expose the end face (back side) of described chip 11.Described packing colloid 13 is generally the epoxy resin base material doped with solid filling, and described solid filling can be silica dioxide granule or alumina particle etc.Be positioned at a upper surface of the packing colloid 13 of described opening 122 height can slightly lower than or be substantially equal to the height of upper surface of described annular interposer substrate 12.
Please refer to shown in Fig. 1, the upper packaging body 200 of one embodiment of the invention can be various forms of packaging body, the present invention is not limited, such as described upper packaging body 200 is selected from the packaging body that has stacked chips, the lower surface of its substrate is provided with several Metal Ball 21, can for solder bond on the connection pad 123 of the upper surface of described annular interposer substrate 12, indirectly to form electrical connection with described substrate 10 and chip 11, said lower package body 100 and upper packaging body 200 can form the framework of stacked type packaging body (POP) jointly.
According to the present embodiment, lower package body 100 due to stacked package body (POP) sets up described annular interposer substrate 12, and described packing colloid 13 is filled between described substrate 10 and annular interposer substrate 12, suitably select the substrate type of described substrate 10 and annular interposer substrate 12 simultaneously, therefore the both sides up and down of described packing colloid 13 can be made to have similar substrate properties, so that when reducing described lower package body 100 integral thickness, the both sides up and down of described lower package body 100 are kept to have less thermal expansion coefficient difference as far as possible, relatively to reduce the probability that described lower package body 100 produces warpage, and then improve production reliability and the useful life of described lower package body 100.
Please refer to shown in Fig. 2, another embodiment of the present invention for stacking semiconductor packaging structure similar in appearance to Fig. 1 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of the present embodiment is: the lower package body 100 of the present embodiment sets up a fin 15 further, described fin 15 is embedded in the opening 122 of described annular interposer substrate 12.Be positioned at the upper surface of the packing colloid 13 of described opening 122 slightly lower than the upper surface of described annular interposer substrate 12, to be embedded described fin 15, the thickness of described fin 15 is substantially equal to the difference in height formed between the upper surface of described packing colloid 13 and the upper surface of described annular interposer substrate 12.The lower surface of described fin 15 directly amplexiforms on the packing colloid 13 at described opening 122 place, and the end face (back side) of the lower surface of the described fin 15 also described chip 11 of hot contact.
In the present embodiment, described fin 15 also can select corresponding described opening 122 to arrange at least one filler hole 151.When carrying out transfer casting (transfer molding) technique, described filler hole 151 can facilitate a sealing syringe to be inserted into space in described opening 122, to be filled out in the space in described opening 122 and the gap 14 between described substrate 10 and annular interposer substrate 12 by described packing colloid 13.Moreover have a heat-conducting layer 16 between a lower surface of described fin 15 and the end face of described chip 11, described heat-conducting layer 16 can be selected from heat conduction elargol coating, indium layer or indium tin layer.Described heat-conducting layer 16 is in order to guarantee the hot annexation of described fin 15 and chip 11.
According to the present embodiment, described lower package body 100 can utilize described annular interposer substrate 12 to make the both sides up and down of described packing colloid 13 have similar substrate properties equally, so that when reducing described lower package body 100 integral thickness, the both sides up and down of described lower package body 100 are kept to have less thermal expansion coefficient difference as far as possible, relatively to reduce the probability that described lower package body 100 produces warpage, and then improve production reliability and the useful life of described lower package body 100.Further, in the present embodiment, opening 122 place of described annular interposer substrate 12 more sets up described fin 15, the end face of the described chip 11 of the hot contact of described fin 15, therefore can rapidly the heat energy that described chip 11 produces upwards be derived, and then be conducive to the radiating efficiency improving described lower package body 100, and relatively reduce described lower package body 100 produces warpage probability because of high temperature.
Please refer to shown in Fig. 3 and 3A, further embodiment of this invention for stacking semiconductor packaging structure similar in appearance to Fig. 2 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of the present embodiment is: the fin 15 of the lower package body 100 of the present embodiment is in the upper lip of the opening 122 being positioned at described annular interposer substrate 12, described fin 15 has more several ribs 152 (as shown in Figure 3A) simultaneously, described ribs 152 is extended to several corner position or its adjacent domain of a upper surface of described annular interposer substrate 12 by described opening 122.The upper surface being positioned at the packing colloid 13 of described opening 122 is substantially equal to the upper surface of described annular interposer substrate 12, therefore the lower surface of described fin 15 still can amplexiform on the packing colloid 13 at described opening 122 place, and the lower surface of described fin 15 also can the end face (back side) of the described chip 11 of hot contact.The quantity of the corner of described ribs 152 and described annular interposer substrate 12 is such as all 4, but is not limited to this.The thickness of described fin 15 is less than the thickness of described annular interposer substrate 12 substantially, such as, be 1/2,1/3,1/4 or 1/5 of the thickness of described annular interposer substrate 12 etc.
According to the present embodiment, described lower package body 100 can utilize described annular interposer substrate 12 to make the both sides up and down of described packing colloid 13 have similar substrate properties equally, so that when reducing described lower package body 100 integral thickness, the both sides up and down of described lower package body 100 are kept to have less thermal expansion coefficient difference as far as possible, relatively to reduce the probability that described lower package body 100 produces warpage, and then improve production reliability and the useful life of described lower package body 100.Further, in the present embodiment, opening 122 place of described annular interposer substrate 12 more sets up described fin 15, and the end face of the described chip 11 of the hot contact of described fin 15, therefore can rapidly the heat energy that described chip 11 produces upwards and outwards be derived, and then be conducive to the radiating efficiency improving described lower package body 100, and increase the structural strength of described annular interposer substrate 12, relatively to reduce described lower package body 100 to produce warpage probability because of high temperature.
Please refer to shown in Fig. 4, yet another embodiment of the invention for stacking semiconductor packaging structure similar in appearance to Fig. 1 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of the present embodiment is: be separately folded with an organic spacer substrate (organic interposer) 17 between the annular interposer substrate 12 of the lower package body 100 (semiconductor packaging structure) of the present embodiment and described upper packaging body 200, described organic spacer substrate 17 can be selected from the tellite without core layer of thickness between 50 to 100 μm or pliability film substrate, such as to be selected from thickness be the additional layers without core layer (build-up) tellite (comprising 2 layers of circuit layer) of 90 μm or thickness is the pliability film substrate of 75 μm, but be not limited to this.
According to the present embodiment, described lower package body 100 can utilize described annular interposer substrate 12 to make the both sides up and down of described packing colloid 13 have similar substrate properties equally, so that when reducing described lower package body 100 integral thickness, the both sides up and down of described lower package body 100 are kept to have less thermal expansion coefficient difference as far as possible, relatively to reduce the probability that described lower package body 100 produces warpage, and then improve production reliability and the useful life of described lower package body 100.Further, in the present embodiment, when the thickness of described annular interposer substrate 12 has been designed to make the both sides up and down of described packing colloid 13 have similar substrate properties (containing thermal coefficient of expansion), but when described annular interposer substrate 12 cannot provide enough weld pad distribution again (redistribution) demands or radiating requirements under limited thickness, the present embodiment is namely by additionally using described organic spacer substrate 17 to meet weld pad distribution again demand or radiating requirements.
Please refer to shown in Fig. 5 A, 5B and 5C, it discloses the schematic flow sheet that Fig. 1 embodiment of the present invention is used for the manufacture method of stacking semiconductor packaging structure (lower package body 100).
First, as shown in Figure 5A, first provide a substrate 10, described substrate 10 has a upper surface and a lower surface, and described upper surface has several weld pad 101 and a chip bearing district 102; Then, a chip 11 is fixedly arranged on the chip bearing district 102 of described substrate 10.
Subsequently, as shown in Fig. 5 A and 5B, reoffer an annular interposer substrate 12, and the weld pad 101 of described substrate 10 is electrically connected by several adapter assemblies 121 of a lower surface of described annular interposer substrate 12, wherein said annular interposer substrate 12 offers an opening 122, and described adapter assembly 121 is centered around described opening 122 around
Finally, as shown in Fig. 5 B and 5C, before inserting described packing colloid 13, first on the opening 122 of described annular interposer substrate 12, stick the provisional glued membrane 30 of one deck, or also can described provisional glued membrane 30 be placed on an inner top surface of a die cavity of a mold (not illustrating) in advance, when being put in by all components of Fig. 5 A between described mold and a bed die (not illustrating) and carry out matched moulds, described provisional glued membrane 30 just can be posted on the opening 122 of described annular interposer substrate 12; Then, one packing colloid 13 is inserted in the gap 14 that formed between described substrate 10 and annular interposer substrate 12 and in the opening 122 of described annular interposer substrate 12, the coated described chip 11 of described packing colloid 13 and adapter assembly 121, and the packing colloid 13 in described opening 122 exposes an end face of described chip 11.After completing the step inserting described packing colloid 13, namely remove described provisional glued membrane 30.By above-mentioned steps, the present invention can complete the manufacture for stacking semiconductor packaging structure (lower package body 100).
Moreover, as shown in Figure 1, the present invention also can make described lower package body 100 further combined with packaging body 200 on, Metal Ball 21 solder bond of the lower surface of wherein said upper packaging body 200 is on the connection pad 123 of the upper surface of described annular interposer substrate 12, and said lower package body 100 and upper packaging body 200 can form the framework of stacked type packaging body (POP) jointly.
Please refer to shown in Fig. 6 A and 6B, it discloses the schematic flow sheet that Fig. 3 embodiment of the present invention is used for the manufacture method of stacking semiconductor packaging structure (lower package body 100).The each step of manufacture method of the present embodiment is roughly similar in appearance to each step of manufacture method of Fig. 5 A to 5C embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of the present embodiment is: the lower package body 100 (semiconductor packaging structure) of Fig. 3 be directly with a fin 15 to replace described provisional glued membrane 30.Therefore, before the step inserting described packing colloid 13, the present invention first arranges a fin 15 at opening 122 place of described annular interposer substrate 12, the corresponding described opening 122 of described fin 15 has several filler hole 151, and described fin 15 can be selected to be positioned at described opening 122 (as shown in Figure 2), or in the upper lip being positioned at described opening 122 (as shown in Figure 3); And, in the step inserting described packing colloid 13, insert described packing colloid 13 by the filler hole 151 of described fin 15.Namely, when carrying out transfer casting (transfer molding) technique, described filler hole 151 can facilitate a sealing syringe to be inserted into space in described opening 122, to be filled out in the space in described opening 122 and the gap 14 between described substrate 10 and annular interposer substrate 12 by described packing colloid 13.
Moreover in the present embodiment, have a heat-conducting layer 16 between a lower surface of described fin 15 and the end face of described chip 11, described heat-conducting layer 16 is in order to guarantee the hot annexation of described fin 15 and chip 11.After the step inserting described packing colloid 13, described fin 15 is directly retained in the annular interposer substrate 12 of described lower package body 100, is not removed.In addition, former underfill 112 can be omitted between described chip 11 and the upper surface of described substrate 10, and directly be replaced to fill described packing colloid 13.
The present invention is described by above-mentioned related embodiment, but above-described embodiment is only enforcement example of the present invention.Must it is noted that published embodiment limit the scope of the invention.On the contrary, be contained in the spirit of claims and the amendment of scope and impartial setting to be included in scope of the present invention.

Claims (20)

1. for a stacking semiconductor packaging structure, it is characterized in that: describedly to comprise for stacking semiconductor packaging structure:
One substrate, has a upper surface and a lower surface, and described upper surface has several weld pad and a chip bearing district;
One chip, is fixedly arranged on the chip bearing district of described substrate;
One annular interposer substrate, there is several adapter assembly, several connection pad and an opening, described adapter assembly is located at a lower surface of described annular interposer substrate, described connection pad is located at a upper surface of described annular interposer substrate, described opening runs through described annular interposer substrate, and described adapter assembly is centered around the surrounding of described opening and is electrically connected the weld pad of described substrate; And
One packing colloid, be filled in the gap that formed between described substrate and annular interposer substrate, and be filled in the opening of described annular interposer substrate, and coated described chip and adapter assembly, packing colloid in wherein said opening exposes an end face of described chip
One upper surface of wherein said packing colloid is less than or equal to the upper surface of described annular interposer substrate.
2. as claimed in claim 1 for stacking semiconductor packaging structure, it is characterized in that: described substrate is selected from tellite without core layer or pliability film substrate.
3. as claimed in claim 1 for stacking semiconductor packaging structure, it is characterized in that: described annular interposer substrate is selected from the tellite of tool core layer.
4. as claimed in claim 1 for stacking semiconductor packaging structure, it is characterized in that: the packing colloid of described opening part is separately provided with a fin, the end face of the described chip of the hot contact of described fin.
5. as claimed in claim 4 for stacking semiconductor packaging structure, it is characterized in that: described fin is positioned at described opening, or be positioned in the upper lip of described opening.
6. as claimed in claim 4 for stacking semiconductor packaging structure, it is characterized in that: between a lower surface of described fin and the end face of described chip, there is a heat-conducting layer.
7. as claimed in claim 6 for stacking semiconductor packaging structure, it is characterized in that: described heat-conducting layer is selected from heat conduction elargol coating, indium layer or indium tin layer.
8. as claimed in claim 4 for stacking semiconductor packaging structure, it is characterized in that: described fin has several ribs, described ribs is extended to several corner positions of a upper surface of described annular interposer substrate by described opening part.
9. as claimed in claim 4 for stacking semiconductor packaging structure, it is characterized in that: the corresponding described opening of described fin has at least one filler hole.
10. as claimed in claim 1 for stacking semiconductor packaging structure, it is characterized in that: described semiconductor packaging structure as a lower package body of stacked type packaging body, and by described connection pad in conjunction with packaging body on.
11. is as claimed in claim 10 for stacking semiconductor packaging structure, it is characterized in that: be separately folded with an organic spacer substrate between the annular interposer substrate of described semiconductor packaging structure and described upper packaging body.
12. is as claimed in claim 11 for stacking semiconductor packaging structure, it is characterized in that: described organic spacer substrate is selected from tellite without core layer or pliability film substrate.
13. is as claimed in claim 1 for stacking semiconductor packaging structure, it is characterized in that: be filled with described packing colloid or a underfill between the upper surface of described chip and described substrate.
14. 1 kinds, for the manufacture method of stacking semiconductor packaging structure, is characterized in that: described manufacture method comprises step:
There is provided a substrate, described substrate has a upper surface and a lower surface, and described upper surface has several weld pad and a chip bearing district;
One chip is fixedly arranged on the chip bearing district of described substrate;
One annular interposer substrate is provided, and the weld pad of described substrate is electrically connected by several adapter assemblies of a lower surface of described annular interposer substrate, wherein said annular interposer substrate offers an opening, described adapter assembly is centered around around described opening, and a upper surface of described annular interposer substrate is provided with several connection pad; And
One packing colloid is inserted in the gap formed between described substrate and annular interposer substrate and in the opening of described annular interposer substrate, the coated described chip of described packing colloid and adapter assembly, and the end face ， And that the packing colloid in described opening exposes described chip makes a upper surface of described packing colloid less than or equal to the upper surface of described annular interposer substrate.
15., as claimed in claim 14 for the manufacture method of stacking semiconductor packaging structure, is characterized in that: before the step inserting described packing colloid, first above described annular interposer substrate, use the provisional glued membrane of one deck; And, after carrying out inserting the step of described packing colloid, then remove described provisional glued membrane.
16. as claimed in claim 14 for the manufacture method of stacking semiconductor packaging structure, it is characterized in that: before the step inserting described packing colloid, first arrange a fin at the opening part of described annular interposer substrate, the corresponding described opening of described fin has several filler hole; And, in the step inserting described packing colloid, insert described packing colloid by the filler hole of described fin.
17. as claimed in claim 16 for the manufacture method of stacking semiconductor packaging structure, it is characterized in that: described fin has several ribs, described ribs is extended to several corner positions of a upper surface of described annular interposer substrate by described opening part.
18., as claimed in claim 16 for the manufacture method of stacking semiconductor packaging structure, is characterized in that: described fin is positioned at described opening, or are positioned in the upper lip of described opening.
19. as claimed in claim 14 for the manufacture method of stacking semiconductor packaging structure, it is characterized in that: after the step carrying out inserting described packing colloid, with the lower package body of described semiconductor packaging structure as stacked type packaging body, and by described connection pad in conjunction with packaging body on.
20., as claimed in claim 19 for the manufacture method of stacking semiconductor packaging structure, is characterized in that: be separately folded with an organic spacer substrate between the annular interposer substrate of described semiconductor packaging structure and described upper packaging body.
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