TWI720851B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure includes a circuit substrate, at least one electronic component and a chip, a two-stage thermosetting adhesive, and an encapsulant. The circuit substrate has a first surface and a second surface opposite to each other. The electronic component and the chip are respectively located on the first surface and are electrically connected to the circuit substrate. The electronic component is electrically connected to the circuit substrate with a conductive member. The two-stage thermosetting adhesive includes a first portion and a second portion separated from each other. The first portion completely covers the electronic component and fills a gap between the electronic component and the circuit substrate. The chip is disposed on the second portion and is wire-bonded to the first surface or the second surface of the circuit substrate. The height of the first portion is substantially the same as the height of the second portion. The encapsulant covers the two-stage thermosetting adhesive and the chip. A manufacturing method of a chip package structure is also provided.

Description

Chip packaging structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, and particularly relates to a chip packaging structure and a manufacturing method thereof.

With the changes in the consumer market, consumers' demands for lighter, thinner, shorter products are also increasing. Especially for electronic products, it is often necessary to improve the integration of chip packaging within a limited volume. However, when increasing the integration level of semiconductor packages, it is often impossible to simultaneously meet the design requirements of electronic components with different functions, thereby easily reducing the reliability of the semiconductor package or increasing its manufacturing cost.

For example, due to the difference in the size of electronic components with different functions, the space between the smaller electronic components and the substrate is relatively narrow, so epoxy molding compound (EMC) is directly used to fill the aforementioned narrow space. It's getting harder and harder inside. Furthermore, when filling an epoxy resin molding compound with a larger size filler into the aforementioned narrow space, it is easy to damage the electronic components due to the filling of the filler, or cause the epoxy resin molding compound to be filled incompletely and form air bubbles. (void), thereby reducing the reliability of the semiconductor package. If the aforementioned narrow space is filled with a smaller but more expensive mold underfill (MUF), the manufacturing cost of the semiconductor package will increase.

The invention provides a chip packaging structure and a manufacturing method thereof, which can reduce the manufacturing cost while improving the reliability of the chip packaging structure.

The chip packaging structure of the present invention includes a circuit substrate, at least one electronic component and a chip, a two-stage thermosetting adhesive layer, and a packaging glue. The circuit substrate has a first surface and a second surface opposite to each other. At least one electronic component and the chip are respectively located on the first surface and electrically connected to the circuit substrate. At least one electronic component is electrically connected to the circuit substrate with a conductive element. The two-stage thermosetting adhesive layer includes a first part and a second part that are separated from each other. The first part completely covers the at least one electronic component and fills the gap between the at least one electronic component and the circuit substrate. The chip is disposed on the second part and wire-bonded to the first surface or the second surface of the circuit substrate. The height of the first part is substantially the same as the height of the second part. The packaging glue covers the two-stage thermosetting glue layer and the chip.

The present invention provides a method for manufacturing a chip package structure, which includes at least the following steps. A circuit substrate is provided, wherein the circuit substrate has a first surface and a second surface opposite to each other. At least one electronic component is arranged on the first surface, and the at least one electronic component is electrically connected to the circuit substrate by a conductive member. A two-stage thermosetting adhesive layer is formed on the first surface. The two-stage thermosetting adhesive layer includes a first part and a second part that are separated from each other. The height of the first part is substantially the same as the height of the second part. The first part completely covers the at least one electronic component and fills the gap between the at least one electronic component and the circuit substrate. The chip is arranged on the second part and the chip is wire-bonded to the first surface or the second surface of the circuit substrate. Carry out the curing process to completely cure the two-stage thermosetting adhesive layer. The packaging glue is formed to cover the two-stage thermosetting glue layer and the chip.

Based on the above, the present invention makes the first part of the two-stage thermosetting adhesive layer completely encapsulate the electronic components and fill between the electronic components and the circuit substrate by virtue of the smaller filler size and better fluidity in the two-stage thermosetting adhesive layer. Therefore, it can prevent the large-sized filler in the encapsulation colloid from flowing into the gap and causing damage to the electronic components or causing the filling colloid in the gap to be incompletely filled and having bubbles, thereby effectively protecting the electronic components. Reduce the probability of damage to electronic components and improve the reliability of the chip package structure. In addition, since the material cost of the two-stage thermosetting adhesive layer is lower than that of the molded underfill (MUF), it can improve the reliability of the chip package structure while reducing the manufacturing cost. On the other hand, the height of the first part of the two-stage thermosetting adhesive layer of the present invention is substantially the same as the height of the second part, that is, the die glue layer (that is, the second part of the two-stage thermosetting adhesive layer) can be configured at the same time By forming a protective adhesive layer that completely covers the electronic components (ie, the first part of the two-stage thermosetting adhesive layer) at the same time, the process of separately forming a protective layer for the electronic components can be omitted, thus simplifying the manufacturing process and further reducing the manufacturing cost.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The directional terms used herein (for example, up, down, right, left, front, back, top, bottom) are only used as a reference drawing and are not intended to imply absolute orientation.

Unless expressly stated otherwise, any method described herein is in no way intended to be construed as requiring its steps to be performed in a specific order.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, size, or size of the layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1D are schematic cross-sectional views of a manufacturing method of a chip package structure according to an embodiment of the present invention. In this embodiment, the manufacturing method of the chip package structure 100 may include the following steps.

1A, a circuit substrate 110 is provided, wherein the circuit substrate 110 has a first surface 110a and a second surface 110b opposite to each other. The circuit substrate 110 may include a plurality of pads 112, and the pads 112 may be provided on the first surface 110a for subsequent electrical connections.

In some embodiments, the circuit substrate 110 is, for example, a multi-layer substrate made of a wafer, a glass substrate, a ceramic substrate, a printed circuit board or other suitable materials, and the pad 112 is, for example, a copper pad. Here, the present invention does not limit the type of circuit substrate 110, as long as the circuit substrate 110 has suitable conductive circuits for electrical connections required in subsequent designs, it belongs to the protection scope of the present invention.

Please continue to refer to FIG. 1A, at least one electronic component 130 is disposed on the first surface 110 a, and the electronic component 130 is electrically connected to the circuit substrate 110 by a conductive member 132. Here, the present invention does not limit the number of electronic components 130, and the number of electronic components 130 may be one or more. FIG. 1A only shows two electronic components 130 as an example. For example, the electronic component 130 may include a first electronic component 1301 and a second electronic component 1302. The first electronic component 1301 is electrically connected to the circuit substrate 110 with a first conductive member 1321, and the second electronic component 1302 is electrically connected with a second conductive member. 1322 is electrically connected to the circuit board 110.

In some embodiments, the electronic component 130 may be an active component, a passive component, or a combination thereof. For example, in this embodiment, the first electronic component 1301 may be an active component, and the second electronic component 1302 may be a passive component, but the invention is not limited thereto. In an embodiment not shown, the first electronic component 1301 and the second electronic component 1302 may both be active components or the first electronic component 1301 and the second electronic component 1302 may both be passive components. In the case where the first electronic component 1301 is an active component and the second electronic component 1302 is a passive component, the first electronic component 1301 is configured on the circuit substrate 110 using flip-chip technology, for example, and the first conductive element 1321 may be conductive. Balls, conductive pillars, conductive bumps or a combination thereof, and the second conductive member 1322 is, for example, conductive paste. The conductive member 1321 and the conductive member 1322 are made of tin, for example, but the invention is not limited to this. In an embodiment, the first electronic component 1301 may be, for example, a magnetoresistive random access memory (MRAM), and the second electronic component 1302 may be a resistor, a capacitor, an inductor or the like, but the invention is not limited thereto.

In this embodiment, there is a gap G between the electronic component 130 and the circuit substrate 110. For example, as shown in FIG. 1A, there is a gap G1 between the first electronic component 1301 and the circuit substrate 110, and there is a gap G2 between the second electronic component 1302 and the circuit substrate 110. Furthermore, the conductive member 132 that electrically connects the electronic component 130 and the circuit substrate 110 can maintain a gap G between the electronic component 130 and the circuit substrate 110. For example, the conductive member 1321 that electrically connects the first electronic component 1301 and the circuit substrate 110 can maintain a gap G1 between the first electronic component 1301 and the circuit substrate 110, and electrically connect the second electronic component 1302 and the circuit substrate. The conductive member 1322 of the 110 maintains a gap G2 between the second electronic component 1302 and the circuit substrate 110. In some embodiments, the height of the gap G may be no greater than 75 μm. When the height of the gap G is within this range, it will aggravate the difficulty of filling the gap G, but the present invention is not limited to this.

1B, a two-stage thermosetting adhesive layer 120 is formed on the first surface 110a. The two-stage thermosetting adhesive layer 120 includes a first portion 122 and a second portion 124 that are separated from each other. The height of the first portion 122 is H1 and the second The height H2 of the portion 124 is substantially the same, and the first portion 122 completely covers the electronic component 130 and fills the gap G between the electronic component 130 and the circuit substrate 110, and the second portion 124 can be used for the subsequent chip bonding process. In other words, the top surface 122a of the first portion 122 and the top surface 124a of the second portion 124 may be substantially coplanar. For example, as shown in FIG. 1B, the first portion 122 may include a first portion 1221 and a first portion 1222. The first portion 1221 completely covers the first electronic component 1301 and fills the gap between the first electronic component 1301 and the circuit substrate 110 G1, the first portion 1222 completely covers the second electronic component 1302 and fills the gap G2 between the second electronic component 1302 and the circuit substrate 110.

In this embodiment, the two-stage thermosetting adhesive layer 120 is first formed in the form of an A-stage liquid glue on the circuit substrate 110. The fluidity of the A-stage liquid glue and the application of capillary phenomenon can reduce the filling in the gap G. The difficulty is that the first part 122 of the two-stage thermosetting adhesive layer 120 can completely cover the electronic component 130 and fill the gap G between the electronic component 130 and the circuit substrate 110. Since the size of the filler in the two-stage thermosetting adhesive layer 120 is smaller than that in the epoxy resin molding compound and has better fluidity, the two-stage thermosetting adhesive layer 120 can smoothly and completely fill the electronic component 130 and the circuit substrate 110. The gap G between the gaps effectively protects the electronic component 130 and avoids the problem that the filler cannot be effectively filled due to excessive filling, thereby reducing the probability of damage to the electronic component 130 and improving the reliability of the chip package structure 100. In addition, the material cost of the two-stage thermosetting adhesive layer 120 is lower than that of the molded underfill (MUF), so the manufacturing cost of the chip package structure 100 can also be reduced.

1A and 1B at the same time, the two-stage thermosetting adhesive layer 120 can be formed by the following steps. First, a mold 10 with a plurality of openings OP can be provided. The mold 10 with a plurality of openings OP is used to form an A-stage liquid glue on the first surface 110a by, for example, printing or coating, so as to subsequently form a two-stage thermosetting胶层120。 Adhesive layer 120. In one embodiment, the mold 10 is made of steel plate, for example, but the present invention is not limited to this.

In this embodiment, the plurality of openings OP may respectively correspond to the formation positions of the first part 122 and the second part 124 of the thermosetting adhesive layer 120 in the subsequent two stages. For example, as shown by the dashed outline in FIG. 1A, the plurality of openings OP may include a plurality of openings OP1 and openings OP2 to respectively correspond to the formation positions R1 and the second part of the first part 122 of the thermosetting adhesive layer 120 in the subsequent two stages. 124 is formed at R2.

It should be noted that the present invention does not limit the foregoing method of forming the two-stage thermosetting adhesive layer 120, as long as the two-stage thermosetting adhesive layer 120 including the first part 122 and the second part 124 separated from each other can be formed on the first surface 110a. The height H1 of the first portion 122 and the height H2 of the second portion 124 may be substantially the same, and the first portion 122 completely covers the electronic component 130 and fills the gap G between the electronic component 130 and the circuit substrate 110, all belonging to the present invention protected range.

Please continue to refer to FIG. 1B, after forming the A-stage liquid glue on the first surface 110a corresponding to the formation positions of the first part 122 and the second part 124 of the subsequent two-stage thermosetting glue layer 120, heating, vacuum drying or ultraviolet irradiation is performed. The step is to remove the solvent of the A-stage liquid glue so that the A-stage liquid glue is transformed into a dry and incompletely cured B-stage glue. The B-stage glue is a non-sticky dry film when the temperature is lower than its glass transition temperature (Tg), which is conducive to handling and storage. When the B-stage glue is in an environment higher than its glass transition temperature, it is It is viscous and fluid, which can be used to wet and adhere the chip 140 or other components.

1C, the chip 140 is arranged on the second part 124. In this embodiment, the wafer 140 is arranged on the second part 124 in a pressing manner, and the temperature provided by the pressing step is higher than the glass transition temperature of the two-stage thermosetting adhesive layer 120 in the B-stage glue, so that B The step glue has adhesiveness to bond the circuit substrate 110 and the chip 140. In the present invention, by arranging the die bond layer (ie the second part 124 of the two-stage thermosetting adhesive layer 120), a protective adhesive layer that completely covers the electronic component 130 (ie, the first part of the two-stage thermosetting adhesive layer 120) is formed at the same time. 122), the process of separately forming a protective layer for the electronic element 130 can be omitted, so the process can be simplified and the manufacturing cost can be further reduced.

In this embodiment, the wafer 140 may be wire-bonded to the first surface 110 a of the circuit substrate 110. In other words, the chip 140 may be configured in such a manner that the active surface 140a faces upward and the back surface 140b opposite to the active surface 140a is bonded to the second portion 124 of the two-stage thermosetting adhesive layer 120. For example, the electrical contacts on the chip 140 can be electrically connected to the pads 112 on the first surface 110a through the wires L. The present invention does not limit the type of the chip 140, which may be determined according to actual design requirements.

Please continue to refer to FIG. 1C, before the subsequent curing process is performed to completely cure the two-stage thermosetting adhesive layer 120, in order to reduce the stability of the electronic component 130 during use due to electromagnetic interference, or the electronic component 130 may damage the electronic component due to overheating after operation. In order to further improve the reliability of the chip package structure 100, when the situation such as 130 occurs, the metal sheet 150 can be arranged on the first part 122 when the two-stage thermosetting adhesive layer 120 is in a B-stage adhesive state and has adhesiveness. In this embodiment, the metal sheet 150 may only cover the top surface 122a of the first part 122 to reduce the use of materials and further reduce the manufacturing cost, but the present invention is not limited to this. In an embodiment not shown, the metal sheet 150 may extend to cover the sidewall of the first portion 122.

In some embodiments, based on the different functionality of the electronic component 130, the metal sheet 150 may be a diamagnetic metal sheet, a heat-dissipating metal sheet, or a combination thereof. For example, the first electronic component 1301 completely covered by the first portion 1221 is, for example, a magnetic active component, and the metal sheet 1501 disposed thereon may be a diamagnetic metal sheet (for example, an iron-nickel alloy), which is covered by the first portion 1222. The completely covered second electronic component 1302 is, for example, a passive component, and the metal sheet 1502 disposed thereon may be a heat-dissipating metal sheet (for example, copper or aluminum).

The present invention does not limit the arrangement sequence of the wafer 140 and the metal sheet 150. In some embodiments, the wafer 140 may be disposed first and then the metal sheet 150 may be disposed. In some embodiments, the metal sheet 150 may be configured first, and then the wafer 140 may be configured. In some embodiments, the metal sheet 150 and the wafer 140 may be configured at the same time.

1D, after at least the chip 140 is configured, a curing process is performed to completely cure the two-stage thermosetting adhesive layer 120 in the B-stage adhesive state to the C-stage adhesive state, and present a stable fixed adhesive layer. The curing process is, for example, baking the two-stage thermosetting adhesive layer 120 in a B-stage adhesive state. In addition, an encapsulant 160 is further formed to cover the two-stage thermosetting adhesive layer 120 and the chip 140. In this embodiment, the encapsulant 160 is, for example, epoxy resin molding compound. Furthermore, the curing process can be performed simultaneously in the step of forming the encapsulant 160. In this case, the two-stage thermosetting adhesive layer 120 is still in the B-stage adhesive state and not completely cured when the encapsulant 160 is formed, so it can still be deformed moderately. In the high-pressure environment where the encapsulant 160 is formed, the two-stage thermosetting adhesive layer 120 in a B-stage adhesive state is tightly compressed, so that possible gaps or bubbles are eliminated, so that the bonding area can be effectively increased. In the process of forming the encapsulant 160, an injection temperature higher than the curing temperature of the two-stage thermosetting adhesive layer 120 is provided at the same time, so that the two-stage thermosetting adhesive layer 120 is completely cured. Since the first part 122 of the two-stage thermosetting adhesive layer 120 has been filled in the gap G between the electronic component 130 and the circuit substrate 110, it can prevent the large-sized filler in the packaging gel 160 from flowing into the gap G, causing the electronic component 130 to flow into the gap G. Damage occurs or causes the filling gel in the gap G to have air bubbles. In addition, there is no need to select a molded underfill (MUF) with a smaller filler size but more expensive to fit the gap G, thereby improving the reliability of the chip package structure 100 and reducing its manufacturing cost. In this embodiment, the packaging glue 160 may cover the two-stage thermosetting glue layer 120, the chip 140 and the metal sheet 150. After the above-mentioned manufacturing process, the fabrication of the chip package structure 100 of this embodiment can be substantially completed.

2 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention. Please refer to FIG. 2, the chip package structure 100 a of this embodiment is similar to the chip package structure 100 of the above embodiment, but the difference is that the chip 140 of this embodiment can be wire-bonded to the second surface 110 b of the circuit substrate 110.

Furthermore, the circuit substrate 110 of this embodiment may have a through hole P extending from the first surface 110 a to the second surface 110 b, and the pad 112 may also be disposed on the second surface 110 b of the circuit substrate 110. The active surface 140 a of the chip 140 may face the circuit substrate 110. In other words, the chip 140 may be configured in such a way that its back surface 140b faces upward, and the active surface 140a is bonded to the second portion 124 of the two-stage thermosetting adhesive layer 120. In this embodiment, the number of the second portion 124 of the two-stage thermosetting adhesive layer 120 is two, which are located on both sides of the through hole P. The chip 140 aligns the through hole P with the electrical contacts on the active surface 140a. The way is configured on the second part 124. Therefore, the electrical contacts on the active surface 140a of the chip 140 can be electrically connected to the pads 112 on the second surface 110b by the wires L passing through the through holes P.

On the other hand, in order to protect the conductive path between the chip 140 and the second surface 110b, the encapsulant 160 may be further filled between the two second portions 124 and in the through hole P, and extend to the second surface 110b to ensure The encapsulant 160 completely covers the wire L to effectively protect the conductive path between the chip 140 and the circuit substrate 110.

In summary, the present invention uses the smaller size and better fluidity of the filler in the two-stage thermosetting adhesive layer so that the first part of the two-stage thermosetting adhesive layer completely covers the electronic components and fills the electronic components and the circuit substrate. Therefore, it can prevent the large-sized filler in the packaging colloid from flowing into the gap and causing damage to the electronic components or causing the filling colloid in the gap to be filled incompletely and have bubbles, thereby effectively protecting the electronics Components, reduce the probability of damage to electronic components and improve the reliability of the chip package structure. In addition, since the material cost of the two-stage thermosetting adhesive layer is lower than that of the molded underfill (MUF), it can improve the reliability of the chip package structure while reducing the manufacturing cost. On the other hand, the height of the first part of the two-stage thermosetting adhesive layer of the present invention is substantially the same as the height of the second part, that is, the die glue layer (that is, the second part of the two-stage thermosetting adhesive layer) can be configured at the same time By forming a protective adhesive layer that completely covers the electronic components (ie, the first part of the two-stage thermosetting adhesive layer) at the same time, the process of separately forming a protective layer for the electronic components can be omitted, thus simplifying the manufacturing process and further reducing the manufacturing cost. In addition, a metal sheet can be placed on the first part of the two-stage thermosetting adhesive layer to reduce the stability of electronic components during use due to electromagnetic interference, or damage to electronic components due to overheating during operation, and further improve the chip package structure The reliability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Mould 100, 100a: chip package structure 110: circuit board 110a: first surface 110b: second surface 112: pad 120: Two-stage thermosetting adhesive layer 122, 1221, 1222: Part One 122a: The top surface of the first part 124: Part Two 124a: The top surface of the second part 130, 1301, 1302: electronic components 132, 1321, 1322: conductive parts 140: chip 140a: active side 140b: back 150, 1501, 1502: metal sheet 160: Encapsulation gel G, G1, G2: gap H1, H2: height L: Wire OP, OP1, OP2: opening P: Through hole R1, R2: forming position

1A to 1D are schematic cross-sectional views of a manufacturing method of a chip package structure according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention.

100: Chip package structure

110: circuit board

110a: first surface

110b: second surface

112: pad

120: Two-stage thermosetting adhesive layer

122, 1221, 1222: Part One

124: Part Two

130, 1301, 1302: electronic components

140: chip

140a: active side

140b: back

150, 1501, 1502: metal sheet

160: Encapsulation gel

L: Wire

Claims (10)

A chip packaging structure, including: The circuit substrate has a first surface and a second surface opposite to each other; At least one electronic component and a chip are respectively located on the first surface and electrically connected to the circuit substrate, wherein the at least one electronic component is electrically connected to the circuit substrate by a conductive member; The two-stage thermosetting adhesive layer includes a first part and a second part separated from each other, in which: The first part completely covers the at least one electronic component and fills the gap between the at least one electronic component and the circuit substrate; The chip is disposed on the second part and wire-bonded to the first surface or the second surface of the circuit substrate; and The height of the first part is substantially the same as the height of the second part; and The encapsulation glue covers the two-stage thermosetting glue layer and the chip. The chip package structure according to claim 1, further comprising a metal sheet disposed on the first part. The chip package structure according to claim 1, wherein the top surface of the first part and the top surface of the second part are substantially coplanar. The chip package structure according to claim 1, wherein the conductive member electrically connecting the at least one electronic component and the circuit substrate maintains the gap between the at least one electronic component and the circuit substrate. The chip package structure according to claim 1, wherein the height of the gap is not greater than 75 microns. A method for manufacturing a chip packaging structure includes: Providing a circuit substrate, wherein the circuit substrate has a first surface and a second surface opposite to each other; Disposing at least one electronic component on the first surface, and the at least one electronic component is electrically connected to the circuit substrate with a conductive member; A two-stage thermosetting adhesive layer is formed on the first surface, wherein: The two-stage thermosetting adhesive layer includes a first part and a second part that are separated from each other; The height of the first part is substantially the same as the height of the second part; and The first part completely covers the at least one electronic component and fills the gap between the at least one electronic component and the circuit substrate; Disposing a chip on the second part and wire bonding the chip to the first surface or the second surface of the circuit substrate; Performing a curing process to completely cure the two-stage thermosetting adhesive layer; and A packaging glue is formed to cover the two-stage thermosetting glue layer and the chip. The method for manufacturing a chip package structure according to claim 6, further comprising printing the first part and the second part on the first surface by a mold having a plurality of openings, wherein the plurality of openings The positions respectively correspond to the forming positions of the first part and the second part. The method for manufacturing a chip package structure according to claim 6, wherein before the curing process is performed to completely cure the two-stage thermosetting adhesive layer, a metal sheet is disposed on the first part. The method for manufacturing a chip package structure according to claim 6, wherein the conductive member electrically connecting the at least one electronic component and the circuit substrate maintains the gap between the at least one electronic component and the circuit substrate述 gap. The method for manufacturing a chip package structure according to claim 6, wherein the height of the gap is not greater than 75 micrometers.

Images