KR100729024B1 - Semiconductor package and mold for it - Google Patents

Semiconductor package and mold for it Download PDF

Info

Publication number
KR100729024B1
KR100729024B1 KR1020010016986A KR20010016986A KR100729024B1 KR 100729024 B1 KR100729024 B1 KR 100729024B1 KR 1020010016986 A KR1020010016986 A KR 1020010016986A KR 20010016986 A KR20010016986 A KR 20010016986A KR 100729024 B1 KR100729024 B1 KR 100729024B1
Authority
KR
South Korea
Prior art keywords
circuit board
semiconductor chip
pad
mold
center pad
Prior art date
Application number
KR1020010016986A
Other languages
Korean (ko)
Other versions
KR20020076839A (en
Inventor
최석현
장상재
신원선
이춘흥
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020010016986A priority Critical patent/KR100729024B1/en
Publication of KR20020076839A publication Critical patent/KR20020076839A/en
Application granted granted Critical
Publication of KR100729024B1 publication Critical patent/KR100729024B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

본 발명은 반도체패키지 및 이를 위한 금형에 관한 것으로, 반도체패키지가 한 종류의 봉지재로 감싸여지게 함으로써, 워페이지 현상을 최소화시키고, 금형을 통한 1회의 봉지 공정으로 제조 공정을 간략화시키며, 또한, 도전성볼이 융착되는 회로기판의 일면 전체에도 봉지부가 형성되도록 함으로써, 회로기판과 봉지부와의 접착력을 향상시킬 수 있도록, 하면 중앙에 다수의 입출력패드가 형성된 센터패드형 반도체칩과; 상기 센터패드형 반도체칩의 상면에 접착되고, 상면 내주연에는 다수의 입출력패드가 형성된 엣지패드형 반도체칩과; 상기 센터패드형 반도체칩의 하면에 접착된 동시에, 상면에는 다수의 본드핑거를 포함하는 회로패턴이 형성되고, 하면에는 다수의 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되며, 상기 센터패드형 반도체칩의 입출력패드와 대응되는 영역에는 관통공이 형성된 회로기판과; 상기 센터패드형 반도체칩과 회로기판의 상면에 형성된 본드핑거를 전기적으로 연결함과 동시에, 상기 엣지패드형 반도체칩의 입출력패드와 상기 회로기판의 하면에 형성된 본드핑거를 전기적으로 연결하는 다수의 도전성와이어와; 상기 센터패드형 반도체칩, 엣지패드형 반도체칩 및 도전성와이어를 외부 환경으로부터 보호할 수 있도록 상기 회로기판의 상면, 상기 회로기판의 볼랜드를 제외한 하면 및 상기 회로기판의 관통공 내측에 형성된 봉지부와; 상기 회로기판 하면의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 반도체패키지가 개시되어 있음The present invention relates to a semiconductor package and a mold for the same, by minimizing the warpage phenomenon by allowing the semiconductor package to be wrapped in one type of encapsulant, and simplifying the manufacturing process by one encapsulation process through the mold, A center pad semiconductor chip in which a plurality of input / output pads are formed at the center of the bottom surface of the circuit board to form an encapsulation part on the entire surface of the circuit board on which the conductive balls are fused to improve adhesion between the circuit board and the encapsulation part; An edge pad type semiconductor chip bonded to an upper surface of the center pad type semiconductor chip and having a plurality of input / output pads formed on an inner circumferential surface of the center pad type; While bonded to the lower surface of the center pad semiconductor chip, a circuit pattern including a plurality of bond fingers is formed on the upper surface, a circuit pattern including a plurality of bond fingers and ball land is formed on the lower surface, the center pad semiconductor A circuit board having through holes formed in an area corresponding to the input / output pad of the chip; A plurality of conductive elements electrically connect the center pad semiconductor chip and the bond finger formed on the upper surface of the circuit board and electrically connect the bond pads formed on the bottom surface of the circuit board with the input / output pad of the edge pad semiconductor chip. With wires; An encapsulation portion formed on an upper surface of the circuit board, a lower surface except a ball land of the circuit board, and an inside of a through hole of the circuit board to protect the center pad semiconductor chip, the edge pad semiconductor chip, and the conductive wire from an external environment; ; Disclosed is a semiconductor package including a plurality of conductive balls fused to a ball land on a lower surface of the circuit board.

Description

반도체패키지 및 이를 위한 금형{Semiconductor package and mold for it}Semiconductor package and mold for it

도1a는 종래의 통상적인 반도체패키지를 도시한 단면도이고, 도1b는 이를 위한 금형을 도시한 사시도이다.Figure 1a is a cross-sectional view showing a conventional conventional semiconductor package, Figure 1b is a perspective view showing a mold for this.

도2a 및 도2b는 본 발명에 의한 반도체패키지를 도시한 단면도이다.2A and 2B are cross-sectional views showing a semiconductor package according to the present invention.

도3a 본 발명의 반도체패키지가 봉지되는 금형을 도시한 사시도이고, 도3b는 도3a의 요부(要部)를 확대도시한 단면도이다.Fig. 3A is a perspective view showing a mold in which the semiconductor package of the present invention is enclosed, and Fig. 3B is an enlarged cross-sectional view of the main part of Fig. 3A.

도4a 및 도4b는 본 발명의 반도체패키지가 봉지되는 상태를 도시한 금형의 단면도이다.4A and 4B are cross-sectional views of a mold showing a state in which the semiconductor package of the present invention is sealed.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

101,102; 본 발명에 의한 반도체패키지101,102; Semiconductor package according to the present invention

2; 센터패드형 반도체칩(Center Pad Type Semiconductor Chip)2; Center Pad Type Semiconductor Chip

4; 엣지패드형 반도체칩(Edge Pad Type Semiconductor Chip4; Edge Pad Type Semiconductor Chip

2a,4a; 입출력패드 6; 접착수단2a, 4a; Input / output pad 6; Adhesive means

8a,8b; 도전성와이어(Conductive Wire) 10; 봉지부8a, 8b; Conductive Wire 10; Encapsulation

12; 회로기판 14; 수지층12; Circuit board 14; Resin layer

16a; 본드핑거(Bond Finger) 16b; 볼랜드(Ball Land)16a; Bond Finger 16b; Ball Land

16; 회로패턴 18; 커버코트(cover Coat) 16; Circuit pattern 18; Cover coat                 

20; 도전성 비아홀(Conduvtive Via Hole) 22; 관통공20; Conduvtive Via Hole 22; Through hole

30; 도전성볼(Conductive Ball) 40; 상금형30; Conductive ball 40; Prize

42; 게이트(Gate) 50; 하금형42; Gate 50; Lower mold

40a,50a; 캐비티(Cavity) 51; 중앙캐비티40a, 50a; Cavity 51; Central cavity

52; 돌기 53; 배큠홀(Vacuum Hole)52; Protrusion 53; Vacuum Hole

본 발명은 반도체패키지 및 이를 위한 금형에 관한 것으로, 더욱 상세하게 설명하면 센터패드형 및 엣지패드형 반도체칩이 상호 스택(Stack)된 반도체패키지 및 이를 위한 금형에 관한 것이다.The present invention relates to a semiconductor package and a mold for the same, and more particularly, to a semiconductor package in which a center pad type and an edge pad type semiconductor chip are stacked on each other, and a mold for the same.

전자기기의 박형화, 소형화 추세에 따라 반도체칩을 탑재하는 패키징(Packaging) 기술도 고속, 고기능, 고밀도 실장이 요구되고 있다. 이러한 요구에 부응하여 다수의 반도체칩을 상호 스택한 구조의 반도체패키지가 등장하게 되었다.In accordance with the trend toward thinner and smaller electronic devices, packaging technology for mounting semiconductor chips is also required for high speed, high performance, and high density mounting. In response to this demand, a semiconductor package having a structure in which a plurality of semiconductor chips are stacked on each other has emerged.

특히, 이러한 스택 구조를 적용한 패키징 기술은 플래시 메모리(Flash Memory), DRAM, SRAM, DSP(Digital Signal Processor) 등의 혼합 스택이 가능함으로써, 고기능화, 다기능화의 패키지를 구현하는 장점이 있어, 새로운 어셈블리(Assembling) 기술로 그 적용 범위가 점차 확대되고 있는 추세이다. 더구나, 중앙면에 입출력패드가 배열되는 센터패드형(Center Pad Type) 반도체칩과, 내 주면에 입출력패드가 배열되는 엣지패드형(Edge Pad Type) 반도체칩의 스택은 상기와 같은 장점을 더욱 배가시킬 수 밖에 없다.In particular, the packaging technology employing such a stack structure enables a mixed stack of flash memory, DRAM, SRAM, and DSP (Digital Signal Processor), which has the advantage of implementing a highly functional and multifunctional package, resulting in a new assembly. (Assembling) technology is gradually expanding its application range. In addition, the stack of the center pad type semiconductor chip in which the input / output pads are arranged on the center surface and the edge pad type semiconductor chip in which the input / output pads are arranged on the inner surface thereof doubles the above advantages. I can only do it.

도1a에는 이러한 장점을 갖는 종래의 반도체패키지(100')가 도시되어 있다.Figure 1a shows a conventional semiconductor package 100 'having this advantage.

도시된 바와 같이 하면 중앙면에 입출력패드(2a)가 형성된 센터패드형 반도체칩(2)이 구비되어 있고, 그 상면에는 접착수단(6)이 개재된 채 상면 내주면에 입출력패드(4a)가 형성된 엣지패드형 반도체칩(4)이 구비되어 있다. 또한, 상기 센터패드형 반도체칩(2)의 하면에는 접착수단(6)이 개재된 채 회로기판(12)이 접착되어 있으며, 상기한 회로기판(12)의 구조는 다음과 같다.As shown in the drawing, a center pad-type semiconductor chip 2 having an input / output pad 2a formed on a central surface thereof is provided, and an input / output pad 4a is formed on an inner circumferential surface of the upper surface with an adhesive means 6 interposed therebetween. An edge pad type semiconductor chip 4 is provided. In addition, the circuit board 12 is bonded to the bottom surface of the center pad semiconductor chip 2 with the bonding means 6 interposed therebetween, and the structure of the circuit board 12 is as follows.

수지층(14)을 중심으로 그 상,하면에는 다수의 회로패턴(16)이 형성되어 있고, 상기 상면의 회로패턴(16)은 반도체칩(4)과의 전기적 연결을 위한 본드핑거(16a)를 포함한다. 또한, 수지층(14) 하면의 회로패턴(16)은 반도체칩(2)과의 전기적 연결을 위한 본드핑거(16a)뿐만 아니라, 차후 마더보드(Mother Board)와의 전기적 연결을 위한 볼랜드(16b)가 형성되어 있다. 물론, 상기 수지층(14)은 상기 센터패드형 반도체칩(2)의 입출력패드(2a)가 외부로 개방될 수 있도록 중앙부에 관통공(22)이 형성되어 있다. 또한, 상기 수지층(14) 상,하면의 회로패턴(16)중 필요한 영역이 전기적으로 연결될 수 있도록 상기 수지층(14)을 관통하여서는 도전성비아홀(20)이 형성되어 있다. 한편, 상기 회로패턴(16) 등을 외부환경으로부터 보호하기 위해, 본드핑거(16a) 및 볼랜드(16b)를 제외한 영역에는 절연성 커버코트(18)가 코팅되어 있다.A plurality of circuit patterns 16 are formed on and under the resin layer 14, and the circuit patterns 16 on the upper surface are bonded fingers 16a for electrical connection with the semiconductor chip 4. It includes. In addition, the circuit pattern 16 on the bottom surface of the resin layer 14 is not only a bond finger 16a for electrical connection with the semiconductor chip 2, but also a borland 16b for electrical connection with a motherboard later. Is formed. Of course, the through hole 22 is formed in the center of the resin layer 14 so that the input / output pad 2a of the center pad semiconductor chip 2 can be opened to the outside. In addition, conductive via holes 20 are formed through the resin layer 14 so that required regions of the circuit patterns 16 on the upper and lower surfaces of the resin layer 14 may be electrically connected to each other. On the other hand, in order to protect the circuit pattern 16 and the like from the external environment, the insulating cover coat 18 is coated in the regions except for the bond finger 16a and the borland 16b.

계속해서, 상기 센터패드형 반도체칩(2)의 입출력패드(2a)는 도전성와이어(8b)에 의해 회로기판(12)의 하면에 위치된 회로패턴(16)중 본드핑거(16a)에 연결되어 있고, 상기 엣지패드형 반도체칩(4)의 입출력패드(4a)도 도전성와이어(8a)에 의해 회로기판(12)의 상면에 위치된 회로패턴(16)중 본드핑거(16a)에 연결되어 있다. Subsequently, the input / output pad 2a of the center pad semiconductor chip 2 is connected to the bond finger 16a of the circuit pattern 16 located on the bottom surface of the circuit board 12 by the conductive wire 8b. The input / output pad 4a of the edge pad type semiconductor chip 4 is also connected to the bond finger 16a of the circuit pattern 16 located on the upper surface of the circuit board 12 by the conductive wire 8a. .

또한, 상기 회로기판(12)의 상면 전체에는 센터패드형 반도체칩(2), 엣지패드형 반도체칩(4) 및 도전성와이어(8a) 등을 외부환경으로부터 보호하기 위해 봉지재(예를 들면, 에폭시몰딩컴파운드(Epoxy Molding Compound))로 봉지된 제1봉지부(10a)가 형성되어 있고, 상기 회로기판(12)의 관통공(22)에는 도전성와이어(8b) 등을 외부 환경으로부터 보호하기 위해 액상 봉지재(예를 들면, 글럽탑(Glop Top))로 봉지된 제2봉지부(10b)가 형성되어 있다.In addition, the entire upper surface of the circuit board 12 includes an encapsulant (for example, to protect the center pad semiconductor chip 2, the edge pad semiconductor chip 4, the conductive wire 8a, etc.) from the external environment. The first encapsulation portion 10a encapsulated with an epoxy molding compound is formed, and the through-hole 22 of the circuit board 12 protects the conductive wire 8b from the external environment. A second encapsulation portion 10b encapsulated with a liquid encapsulation material (for example, a glove top) is formed.

여기서, 상기 제1봉지부(10a)는 통상 고체형의 봉지재가 금형내에서 고온,고압으로 융용되어 형성되고, 상기 제2봉지부(10b)는 통상 액상 봉지재가 디스펜서(Dispenser)로부터 분사되어 형성된 것이다.Here, the first encapsulation portion 10a is formed by melting a solid encapsulant in a mold at high temperature and high pressure, and the second encapsulation portion 10b is formed by injecting a liquid encapsulant from a dispenser. will be.

마지막으로, 상기 회로기판(12)의 하면에 위치된 볼랜드(16b)에는 솔더볼과 같은 도전성볼(30)이 융착되어 있으며, 이는 차후 마더보드에 실장되는 영역이다.Finally, conductive balls 30 such as solder balls are fused to the ball lands 16b positioned on the bottom surface of the circuit board 12, which is a region to be mounted on the motherboard later.

여기서, 도1b는 상기 반도체패키지(100')의 제조를 위한 금형을 도시한 사시도이며, 이를 참조하여 종래의 금형 구조 및 봉지 방법을 간략히 설명하기로 한다.1B is a perspective view illustrating a mold for manufacturing the semiconductor package 100 ', and a conventional mold structure and a sealing method will be briefly described with reference to the mold.

먼저 도시되지는 않았지만, 회로기판(12)에 센터패드형 반도체칩(2) 및 엣지패드형 반도체칩(4)을 탑재한 후에는, 상기 엣지패드형 반도체칩(4)의 입출력패드(4a)와 회로기판(12) 상면의 회로패턴(16)중 본드핑거(16a)가 도전성와 이어(8a)에 의해 상호 연결된다. 그런후, 상기 자재(회로기판에 반도체칩이 탑재되고 와이어 본딩된 자재)는 상금형(40)과 하금형(50) 사이에 위치되는데 이러한 상태는 도1b에 도시된 바와 같다. 도시된 바와 같이 상금형(40)에는 상기 엣지패드형 반도체칩(4) 등이 봉지재로 감싸여질 수 있도록 일정 체적의 캐비티(40a)가 형성되어 있고, 상기 캐비티(40a)와 연통되어서는 외부로부터 봉지재가 흘러들어 올 수 있도록 홈 형태의 게이트(42)가 형성되어 있다. 또한, 상기 하금형(50)은 대략 평판상으로서 평판모양의 회로기판(12)이 안착 가능하게 되어 있다. 물론, 봉지 공정중 상기 상금형(40)과 하금형(50)은 강하게 밀착된 상태가 된다.Although not shown first, after the center pad semiconductor chip 2 and the edge pad semiconductor chip 4 are mounted on the circuit board 12, the input / output pad 4a of the edge pad semiconductor chip 4 is mounted. And the bond fingers 16a of the circuit patterns 16 on the upper surface of the circuit board 12 are interconnected by conductive wires 8a. Then, the material (a semiconductor chip mounted on the circuit board and wire-bonded) is positioned between the upper mold 40 and the lower mold 50, as shown in FIG. 1B. As shown in the upper mold 40, a cavity 40a of a predetermined volume is formed so that the edge pad type semiconductor chip 4 and the like may be wrapped with an encapsulant, and communicated with the cavity 40a. A groove-like gate 42 is formed so that an encapsulant can flow in. In addition, the lower die 50 has a substantially flat plate-like circuit board 12 that can be seated thereon. Of course, the upper mold 40 and the lower mold 50 is in a state of being in close contact with each other during the sealing process.

상기와 같은 공정에 의해 제1봉지부(10a)가 형성된 후에는, 센터패드형 반도체칩(2)의 입출력패드(2a)와 회로기판(12) 하면의 회로패턴(16)중 본드핑거(16a)가 도전성와이어(8b)로 상호 연결된다. 상기와 같은 공정이 완료된 후에는 액상의 봉지재가 들어 있는 디스펜서를 이용하여 상기 회로기판(12)의 관통공(22) 내측에 일정량의 액상 봉지재를 디스펜싱함으로써, 제2봉지부(10b)를 형성한다. 물론, 상기 액상의 봉지재에는 많은 량의 공기가 포함되어 있음으로, 이를 제거하기 위한 디게싱(Degassing) 공정 및 그 제2봉지부(10b)의 완전한 경화를 위해 고온에서 수행되는 큐어링(Curing) 공정이 반드시 수반된다.After the first encapsulation portion 10a is formed by the above process, the bond finger 16a of the circuit pattern 16 on the input / output pad 2a of the center pad-type semiconductor chip 2 and the lower surface of the circuit board 12 is formed. ) Are interconnected by conductive wires 8b. After the above process is completed, the second encapsulation portion 10b is dispensed by dispensing a predetermined amount of the liquid encapsulant into the through hole 22 of the circuit board 12 using a dispenser containing a liquid encapsulant. Form. Of course, since the liquid encapsulant contains a large amount of air, a degassing process for removing the liquid and a curing performed at a high temperature for complete curing of the second encapsulation portion 10b. Process is necessarily involved.

그러나, 이러한 종래의 반도체패키지는 상술한 바와 같이 제1봉지부와 제2봉지부의 물성이 전혀 다르고(제1봉지부는 통상 에폭시몰딩컴파운드(Epoxy Molding Compound)이고, 제2봉지부는 통상 글럽탑(Glop Top)으로서, 봉지재의 주요 구성 성분인 레진(Resin), 경화제, 충진제 등의 종류 및 배합비가 상이함), 또한 이에 따 라 열팽창계수차가 상이함으로써, 어느 한쪽으로 심하게 휘는 워페이지(Warpage) 현상이 심하게 발생한다. 비록, 상기 워페이지가 상기 제1봉지부 및 제2봉지부의 열팽창계수차에 의해 전적으로 발생되는 것은 아니지만, 그 기여도가 대단히 높게 나타난다.(상기 워페이지는 회로기판, 반도체칩의 열팽창계수차에 의해 영향받기도 함)However, as described above, the conventional semiconductor package is completely different from the physical properties of the first encapsulation part and the second encapsulation part (the first encapsulation part is usually an epoxy molding compound, and the second encapsulation part is usually a glop top). Top), the main components of the encapsulant (resin, hardener, filler, etc. and the mixing ratio is different), and accordingly the thermal expansion coefficient difference is different, warpage phenomenon that is severely bent to either side Occurs badly. Although the warpage is not entirely generated by the thermal expansion coefficient aberration of the first encapsulation portion and the second encapsulation portion, the contribution is very high. (The warpage is caused by the thermal expansion coefficient aberration of the circuit board and the semiconductor chip. Also affected)

또한, 상기한 바와 같이 제2봉지부가 디스펜서에 의해 형성됨으로써, 제2봉지부 내의 공기를 제거하기 위한 디게싱 공정과 완전 경화를 위한 큐어링 공정이 반듯이 수반되어야 함으로써, 반도체패키지의 제조 공정이 복잡해지고 이에 따라 불량률이 높아질 뿐만 아니라 제조 비용도 상승되는 문제가 있다.In addition, as described above, the second encapsulation portion is formed by the dispenser, so that the degassing process for removing air in the second encapsulation portion and the curing process for complete curing must be accompanied, thereby making the manufacturing process of the semiconductor package complicated. As a result, not only the defective rate is increased but also the manufacturing cost is increased.

더불어, 상기 제1봉지부는 회로기판의 상면과 직접 접착되어 계면(界面)을 이루고 있는데, 이 계면은 외부의 열적, 화학적, 기계적 충격 등에 의해 쉽게 박리(剝離)되고, 이에 따라 수분이 용이하게 침투됨으로써 반도체패키지의 신뢰성을 크게 저하시키는 원인이 되기도 한다.In addition, the first encapsulation portion is directly bonded to the upper surface of the circuit board to form an interface, and the interface is easily peeled off by external thermal, chemical, and mechanical shocks, thereby easily penetrating moisture. As a result, the reliability of the semiconductor package may be greatly reduced.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 본 발명의 첫번째 목적은 스택형 반도체패키지가 한 종류의 봉지재로 감싸여지게 함으로써, 워페이지 현상을 최소화시킬 수 있는 반도체패키지 및 이를 위한 금형의 제공에 있다.Therefore, the present invention has been made to solve the conventional problems as described above, the first object of the present invention is that a semiconductor package that can minimize the warpage phenomenon by allowing the stack-type semiconductor package is wrapped in one type of encapsulation material And a mold for this purpose.

본 발명의 두번째 목적은 금형을 통한 1회의 봉지 공정으로 제조 공정을 간략화시키고, 이에 따라 불량률을 저하시키며 또한 제조 비용도 절감할 수 있는 반 도체패키지 및 이를 위한 금형의 제공에 있다.A second object of the present invention is to provide a semiconductor package and a mold for the same, which simplifies the manufacturing process by one encapsulation process through a mold, thereby lowering a defective rate and also reducing manufacturing costs.

본 발명의 세번째 목적은 도전성볼이 융착되는 회로기판의 소정 영역을 제외한 모든 영역이 봉지부와 인터락킹(Inter-Locking)되도록 함으로써, 계면박리 억제는 물론, 수분의 흡수를 최대한 억제할 수 있는 반도체패키지 및 이를 위한 금형의 제공에 있다.A third object of the present invention is to allow all regions except for a predetermined region of a circuit board on which conductive balls are fused to be interlocked with an encapsulation portion, thereby preventing interfacial peeling and absorbing moisture as much as possible. It is in the provision of a package and a mold for it.

상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 하면 중앙에 다수의 입출력패드가 형성된 센터패드형 반도체칩과; 상기 센터패드형 반도체칩의 상면에 접착되고, 상면 내주연에는 다수의 입출력패드가 형성된 엣지패드형 반도체칩과; 상기 센터패드형 반도체칩의 하면에 접착된 동시에, 상면에는 다수의 본드핑거를 포함하는 회로패턴이 형성되고, 하면에는 다수의 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되며, 상기 센터패드형 반도체칩의 입출력패드와 대응되는 영역에는 관통공이 형성된 회로기판과; 상기 센터패드형 반도체칩과 회로기판의 상면에 형성된 본드핑거를 전기적으로 연결함과 동시에, 상기 엣지패드형 반도체칩의 입출력패드와 상기 회로기판의 하면에 형성된 본드핑거를 전기적으로 연결하는 다수의 도전성와이어와; 상기 센터패드형 반도체칩, 엣지패드형 반도체칩 및 도전성와이어를 외부 환경으로부터 보호할 수 있도록 상기 회로기판의 상면, 상기 회로기판의 볼랜드를 제외한 하면 및 상기 회로기판의 관통공 내측에 형성된 봉지부와; 상기 회로기판 하면의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다. In order to achieve the above object, the semiconductor package according to the present invention comprises a center pad-type semiconductor chip having a plurality of input / output pads formed on a bottom surface thereof; An edge pad type semiconductor chip bonded to an upper surface of the center pad type semiconductor chip and having a plurality of input / output pads formed on an inner circumferential surface of the center pad type; While bonded to the lower surface of the center pad semiconductor chip, a circuit pattern including a plurality of bond fingers is formed on the upper surface, a circuit pattern including a plurality of bond fingers and ball land is formed on the lower surface, the center pad semiconductor A circuit board having through holes formed in an area corresponding to the input / output pad of the chip; A plurality of conductive elements electrically connect the center pad semiconductor chip and the bond finger formed on the upper surface of the circuit board and electrically connect the bond pads formed on the bottom surface of the circuit board with the input / output pad of the edge pad semiconductor chip. With wires; An encapsulation portion formed on an upper surface of the circuit board, a lower surface except a ball land of the circuit board, and an inside of a through hole of the circuit board to protect the center pad semiconductor chip, the edge pad semiconductor chip, and the conductive wire from an external environment; ; It characterized in that it comprises a plurality of conductive balls fused to the ball land on the lower surface of the circuit board.                     

여기서, 상기 봉지부는 회로기판의 측면에도 형성될 수 있다.Here, the encapsulation may be formed on the side of the circuit board.

또한, 상기 회로기판은 하면의 볼랜드 외주연에 커버코트가 코팅되어 있고, 상기 커버코트는 다시 봉지부와 밀착될 수도 있다.In addition, the circuit board is coated with a cover coat on the outer periphery of the borland of the lower surface, the cover coat may be in close contact with the encapsulation again.

더불어, 상기한 목적을 달성하기 위해 본 발명에 의한 금형은 반도체칩이 접착된 회로기판이 위치되어 상부에 일정 체적의 봉지부가 형성되도록 캐비티가 형성된 상금형과; 상기 상금형의 하면에 상기 회로기판의 넓이보다 큰 넓이를 가진 캐비티가 형성되고, 상기 캐비티의 바닥면에는 상기 회로기판중 볼랜드와 직접 접촉되도록 다수의 돌기가 형성된 하금형을 포함하여 이루어진 것을 특징으로 한다.In addition, the mold according to the present invention in order to achieve the above object is the upper die and the cavity is formed so that the circuit board is bonded to the semiconductor chip is formed a predetermined volume of the encapsulation portion; A cavity having an area larger than that of the circuit board is formed on the bottom surface of the upper mold, and a bottom mold having a plurality of protrusions formed on the bottom surface of the cavity to be in direct contact with the ball lands of the circuit board. do.

여기서, 상기 돌기는 높이가 상기 회로기판의 하면과 상기 하금형의 캐비티 바닥면이 상호 일정 거리 이격될 수 있는 높이로 형성됨이 바람직하다.Here, the protrusion is preferably formed so that the height of the lower surface of the circuit board and the bottom surface of the cavity of the lower die can be spaced apart from each other by a predetermined distance.

또한, 상기 돌기에는 상기 회로기판의 볼랜드와 강하게 밀착되도록 배큠이 제공되는 배큠홀(Vacuum Hole)이 더 형성될 수 있다.In addition, the protrusion may further include a vacuum hole provided with vacuum so as to be in close contact with the ball land of the circuit board.

상기와 같이 하여 본 발명에 의한 반도체패키지 및 이를 위한 금형에 의하면, 종래와 다르게 회로기판을 중심으로 상,하면에 동일한 재질의 봉지부(예를 들면, 에폭시몰딩컴파운드)가 형성됨으로써, 반도체패키지의 워페이지 현상이 최소화된다.As described above, according to the semiconductor package and the mold for the same according to the present invention, unlike the related art, an encapsulation portion (for example, an epoxy molding compound) of the same material is formed on the upper and lower surfaces of the semiconductor package. The warpage phenomenon is minimized.

또한, 금형을 통하여 1회의 공정으로 봉지부가 형성됨으로써, 제조 공정이 간략화되고 이에 따라 불량률이 저하됨은 물론, 제조 비용도 절감된다.In addition, since the encapsulation portion is formed in one step through the mold, the manufacturing process is simplified, and as a result, the defect rate is lowered, and the manufacturing cost is also reduced.

더불어, 도전성볼이 융착되는 회로기판의 일정영역을 제외한 모든 영역이 봉지재로 봉지됨으로써, 봉지부와 회로기판간의 인터락킹력이 향상되고, 이에 따라 계면박리 억제는 물론, 수분의 흡수를 최대한 억제하게 된다.In addition, all areas except the predetermined area of the circuit board to which the conductive balls are fused are encapsulated with an encapsulant, thereby improving the interlocking force between the encapsulation part and the circuit board, thereby suppressing interfacial separation and maximizing absorption of moisture. Done.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2a 및 도2b는 본 발명에 의한 반도체패키지(101,102)를 도시한 단면도이다.2A and 2B are cross-sectional views showing semiconductor packages 101 and 102 according to the present invention.

도시된 바와 같이 하면 중앙면에 다수의 입출력패드(2a)가 형성된 센터패드형 반도체칩(2)이 구비되어 있고, 그 상면에는 접착수단(6)이 개재된 채 상면 내주면에는 다수의 입출력패드(4a)가 형성된 엣지패드형 반도체칩(4)이 구비되어 있다.As shown in the drawing, a center pad-type semiconductor chip 2 having a plurality of input / output pads 2a formed on a central surface thereof is provided, and a plurality of input / output pads are formed on an inner circumferential surface of the upper surface with an adhesive means 6 interposed therebetween. The edge pad type semiconductor chip 4 in which 4a) was formed is provided.

또한, 상기 센터패드형 반도체칩(2)의 하면에는 접착수단(6)이 개재된 채, 상면에는 다수의 본드핑거(16a)를 포함하는 회로패턴(16)이 형성되고, 하면에는 다수의 본드핑거(16a) 및 볼랜드(16b)를 포함하는 회로패턴(16)이 형성되며, 상기 센터패드형 반도체칩(2)의 입출력패드(2a)와 대응되는 영역에는 관통공(22)이 형성된 회로기판(12)이 구비되어 있다.In addition, a circuit pattern 16 including a plurality of bond fingers 16a is formed on an upper surface of the center pad semiconductor chip 2 with an adhesive means 6 interposed therebetween, and a plurality of bonds on a lower surface of the center pad semiconductor chip 2. A circuit pattern 16 including a finger 16a and a ball land 16b is formed, and a circuit board having a through hole 22 formed in a region corresponding to the input / output pad 2a of the center pad-type semiconductor chip 2. (12) is provided.

여기서, 상기 회로기판(12) 상면의 본드핑거(16a)를 제외한 표면과, 상기 회로기판(12) 하면의 본드핑거(16a) 및 볼랜드(16b)를 제외한 표면은 도2a에 도시된 바와 같이 절연성 커버코트(18)로 코팅될 수 있다. 또한, 도2b에 도시된 바와 같이 상기 절연성 커버코트(18)는 회로기판(12) 상면의 본드핑거(16a)를 제외한 표면에만 형성될 수도 있다. 즉, 회로기판(12) 하면에는 상기 절연성 커버코트(18)가 형성되지 않을 수도 있다. Here, the surface except for the bond finger 16a on the upper surface of the circuit board 12 and the surface except for the bond finger 16a and the ball land 16b on the lower surface of the circuit board 12 are insulative as shown in FIG. 2A. It may be coated with a covercoat 18. In addition, as shown in FIG. 2B, the insulating cover coat 18 may be formed only on the surface except for the bond finger 16a on the upper surface of the circuit board 12. That is, the insulating cover coat 18 may not be formed on the bottom surface of the circuit board 12.                     

도면중 미설명 부호 14는 상기 회로패턴(16)이 형성되는 열경화성 수지층이고, 20은 수지층(14) 상면의 회로패턴(16)과 하면의 회로패턴(16)을 상호 연결하는 도전성 비아홀이다.In the figure, reference numeral 14 denotes a thermosetting resin layer in which the circuit pattern 16 is formed, and 20 denotes a conductive via hole connecting the circuit pattern 16 on the upper surface of the resin layer 14 and the circuit pattern 16 on the lower surface thereof. .

계속해서, 상기 엣지패드형 반도체칩(4)의 입출력패드(4a)와 상기 회로기판(12) 상면에 형성된 본드핑거(16a)를 전기적으로 연결함과 동시에, 상기 센터패드형 반도체칩(2)의 입출력패드(2a)와 상기 회로기판(12)의 하면에 형성된 본드핑거(16a)를 전기적으로 연결하는 다수의 도전성와이어(8a,8b)(예를 들면, 골드와이어(Au Wire), 구리와이어(Cu Wire), 알루미늄와이어(Al Wire))가 구비되어 있다.Subsequently, the input / output pad 4a of the edge pad semiconductor chip 4 and the bond finger 16a formed on the upper surface of the circuit board 12 are electrically connected to each other, and the center pad semiconductor chip 2 is electrically connected. A plurality of conductive wires 8a and 8b (for example, gold wires and copper wires) for electrically connecting the input / output pads 2a and the bond fingers 16a formed on the lower surface of the circuit board 12. (Cu Wire) and Aluminum Wire (Al Wire) are provided.

한편, 상기 센터패드형 반도체칩(2), 엣지패드형 반도체칩(4) 및 도전성와이어(8a,8b)를 외부 환경으로부터 보호할 수 있도록 상기 회로기판(12)의 상면, 상기 회로기판(12)의 볼랜드(16b)를 제외한 하면 및 상기 회로기판(12)의 관통공(22) 내측에는 한종류의 봉지재(예를 들면, 에폭시몰딩컴파운드)로 형성된 봉지부(10)가 형성되어 있다.The upper surface of the circuit board 12 and the circuit board 12 may protect the center pad semiconductor chip 2, the edge pad semiconductor chip 4, and the conductive wires 8a and 8b from an external environment. An encapsulation portion 10 formed of one kind of encapsulant (for example, epoxy molding compound) is formed on the lower surface except for the ball land 16b) and inside the through hole 22 of the circuit board 12.

즉, 상기 봉지부(10)는 상기 회로기판(12) 상면과 상기 센터패드형 반도체칩(2), 엣지패드형 반도체칩(4) 및 도전성와이어(8a)를 감싸는 동시에, 상기 회로기판(12) 하면의 상기 볼랜드(16b)를 제외한 영역도 감싸고 또한, 상기 회로기판(12) 중앙에 형성된 관통공(22) 및 도전성와이어(8b)도 감싸고 있다. 물론, 상기 봉지부(10)는 상기 회로기판(12)의 측면에도 형성됨으로써, 결국 상기 봉지부(10)에 의해 상기 볼랜드(16b)를 제외한 반도체패키지의 모든 영역이 봉지되어 있다. That is, the encapsulation part 10 surrounds the upper surface of the circuit board 12, the center pad semiconductor chip 2, the edge pad semiconductor chip 4, and the conductive wire 8a, and at the same time, the circuit board 12. The area of the bottom surface of the circuit board 12 except for the ball land 16b is also enclosed, and the through hole 22 and the conductive wire 8b formed in the center of the circuit board 12 are also enclosed. Of course, the encapsulation portion 10 is also formed on the side surface of the circuit board 12, so that all regions of the semiconductor package except for the ball land 16b are encapsulated by the encapsulation portion 10.                     

여기서, 상기 봉지부(10)는 도2a에 도시된 바와 같이 회로기판(12) 하면에 커버코트(18)가 코팅된 경우에는 그 커버코트(18)와 직접 접착된 상태이고, 도2b에 도시된 바와 같이 회로기판(12) 하면에 커버코트(18)가 코팅되지 않은 경우에는 수지층(14)과 직접 접착될 수 있다.Here, the encapsulation part 10 is directly bonded to the cover coat 18 when the cover coat 18 is coated on the bottom surface of the circuit board 12 as shown in FIG. 2A, and is shown in FIG. 2B. As described above, when the cover coat 18 is not coated on the bottom surface of the circuit board 12, the resin layer 14 may be directly bonded to the resin layer 14.

이와 같이 봉지부(10)와 회로기판(12) 하면의 커버코트(18) 또는 수지층(14)이 직접 접착된 경우에는 그 접착력이 매우 우수함으로써, 회로기판(12)과 커버코트(18) 또는 봉지부(10)와의 계면박리(界面剝離) 현상이 최소화되고, 이에 따라 수분 흡수율도 현저히 저하된다.As such, when the encapsulation portion 10 and the cover coat 18 or the resin layer 14 on the lower surface of the circuit board 12 are directly adhered to each other, the adhesive force is very high, so that the circuit board 12 and the cover coat 18 are excellent. Or the interface peeling phenomenon with the sealing part 10 is minimized, and water absorption rate also falls remarkably by this.

또한, 회로기판(12)의 상면, 하면 및 측면이 동일한 재질의 봉지부(10)로 감싸여져 있음으로써, 열팽창계수차가 적어 워페이지 현상이 최소화되기도 한다.In addition, since the top, bottom, and side surfaces of the circuit board 12 are wrapped with the encapsulation portion 10 of the same material, the thermal expansion coefficient difference is small, so that the warpage phenomenon may be minimized.

한편, 상기 회로기판(12) 하면의 각 볼랜드(16b)에는 솔더볼(Solder Ball)과 같은 도전성볼(30)이 각각 융착되어, 차후 마더보드에 실장 가능한 형태로 되어 있다.Meanwhile, conductive balls 30 such as solder balls are fused to each ball land 16b of the lower surface of the circuit board 12 to form a mountable on the motherboard later.

도3a는 본 발명의 반도체패키지(101,102)가 봉지되는 금형을 도시한 사시도이고, 도3b는 도3a의 요부(要部)를 확대도시한 단면도이다.FIG. 3A is a perspective view showing a mold in which the semiconductor packages 101 and 102 of the present invention are encapsulated, and FIG. 3B is an enlarged cross-sectional view showing essential parts of FIG. 3A.

도시된 바와 같이 반도체칩(4)이 접착된 회로기판(12)이 위치되어 상부에 일정 체적의 봉지부(도시되지 않음)가 형성되도록 캐비티(40a)가 형성된 상금형(40)이 구비되어 있다. 상기 캐비티(40a)에 연결되어서는 일측부로 게이트(42)가 형성되어 있으며, 상기 게이트(42)를 통하여 봉지재(예를 들면, 에폭시몰딩컴파운드)가 캐비티(40a) 내측으로 충진된다. As shown, the upper mold 40 having the cavity 40a is provided such that the circuit board 12 to which the semiconductor chip 4 is bonded is formed to form a predetermined volume of an encapsulation portion (not shown). . The gate 42 is formed on one side of the cavity 40a, and an encapsulant (eg, an epoxy molding compound) is filled into the cavity 40a through the gate 42.                     

한편, 상기 상금형(40)의 하부 즉, 상기 회로기판(12)의 하면에는 상기 회로기판(12)의 넓이보다 큰 넓이를 가진 또다른 캐비티(50a)가 형성되고, 상기 캐비티(50a)의 바닥면에는 상기 회로기판(12)중 볼랜드(16b)와 직접 접촉되도록 다수의 돌기(52)가 형성된 하금형(50)이 구비되어 있다.Meanwhile, another cavity 50a having an area larger than that of the circuit board 12 is formed below the upper mold 40, that is, the bottom surface of the circuit board 12. The bottom surface is provided with a lower die 50 having a plurality of protrusions 52 formed in direct contact with the ball lands 16b of the circuit board 12.

상기 돌기(52)는 그 높이가 상기 회로기판(12)의 하면과 상기 하금형(50)의 캐비티(50a) 바닥면이 상호 일정 거리 이격될 수 있는 높이로 형성되어 있다. 즉, 상기 돌기(52)의 상면은 상기 회로기판(12)의 볼랜드(16b)와 직접 접촉되고, 상기 볼랜드(16b)를 제외한 영역은 상기 캐비티(50a)의 바닥면과 일정 거리 이격된 상태가 된다.The protrusion 52 is formed to have a height such that the bottom surface of the circuit board 12 and the bottom surface of the cavity 50a of the lower die 50 can be spaced apart from each other by a predetermined distance. That is, the top surface of the protrusion 52 is in direct contact with the ball land 16b of the circuit board 12, and the area except the ball land 16b is spaced apart from the bottom surface of the cavity 50a by a predetermined distance. do.

또한, 상기 하금형(50)에 형성된 캐비티(50a)의 중앙에는 그 캐비티(50a)보다 더 깊은 중앙캐비티(51)가 형성되어 있으며, 상기 중앙캐비티(51)는 회로기판(12)에 형성된 관통공(22)과 대응되는 위치이다.In addition, a central cavity 51 deeper than the cavity 50a is formed in the center of the cavity 50a formed in the lower die 50, and the central cavity 51 penetrates the circuit board 12. The position corresponding to the ball 22.

더불어, 상기 각각의 돌기(52)에는 상기 회로기판(12)의 볼랜드(16b)와 강하게 밀착되도록 배큠홀(53)이 더 형성될 수도 있다. 즉, 상기 각각의 돌기(52)에는 배큠홀(53)을 형성하고, 봉지 공정중 일정 압력(대기압보다 작은 압력)의 배큠을 제공함으로써, 상기 회로기판(12)의 각 볼랜드(16b)가 상기 돌기(52)에 강하게 밀착되도록 할 수 있다. 상기와 같이 볼랜드(16b)가 돌기(52)에 강하게 밀착되면, 봉지 공정중 봉지재가 상기 볼랜드(16b)의 표면으로 퍼져 형성되는 플래시(Flash)의 발생을 억제할 수 있다.In addition, a back hole 53 may be further formed in each of the protrusions 52 so as to be in close contact with the ball land 16b of the circuit board 12. That is, each of the protrusions 52 is provided with a vacuum hole 53, and by providing a constant pressure (pressure less than the atmospheric pressure) during the encapsulation process, each ball land (16b) of the circuit board 12 is It may be to be in close contact with the projection (52). When the ball land 16b is in close contact with the protrusions 52 as described above, the encapsulant may be prevented from being generated by the encapsulant spreading on the surface of the ball land 16b during the sealing process.

도4a 및 도4b는 본 발명의 반도체패키지가 봉지되는 상태를 도시한 금형의 단면도로서, 이를 참조하여 봉지 방법 및 작용을 설명한다.4A and 4B are cross-sectional views of a mold showing a state in which the semiconductor package of the present invention is encapsulated, and the encapsulation method and operation will be described with reference to the mold.

여기서, 도4a에 도시된 회로기판(12, 회로기판의 상세한 구조는 도2a 또는 도2b를 참조)은 하면의 볼랜드(16b)를 제외한 수지층(14) 및 회로패턴(16) 표면에 커버코트(18)가 코팅된 것이고, 도4b에 도시된 회로기판(12)은 하면에 커버코트(18)가 코팅되지 않은 차이가 있을 뿐으로서, 봉지 방법 및 작용을 별도로 구분하여 설명하지는 않기로 한다.Here, the circuit board 12 shown in FIG. 4A (see FIG. 2A or FIG. 2B for the detailed structure of the circuit board) has a cover coat on the surface of the resin layer 14 and the circuit pattern 16 except for the ball land 16b on the lower surface. (18) is coated, and the circuit board 12 shown in FIG. 4B has only a difference that the cover coat 18 is not coated on the lower surface thereof, and thus the sealing method and operation will not be described separately.

도시된 바와 같이 센터패드형 반도체칩(2) 및 엣지패드형 반도체칩(4)이 안착되고, 와이어 본딩이 완료된 회로기판(12)을 하금형(50)의 캐비티(50a) 내측에 위치시킨다. 이때, 상기 회로기판(12)의 하면에 형성된 볼랜드(16b)는 하금형(50)의 캐비티(50a) 바닥면에 형성된 돌기(52)와 직접 접촉된 상태가 되도록 한다. 따라서, 상기 회로기판(12)은 상기 볼랜드(16b)를 제외한 영역이 상기 하금형(50)의 캐비티(50a) 바닥면과 일정 거리 이격된 상태가 된다. 더불어, 상기 회로기판(12)은 그 면적이 상기 하금형(50)의 캐비티(50a) 면적보다 작게 되어 있음으로, 상기 회로기판(12)의 측면은 상기 하금형(50)의 캐비티(50a) 측면에 접촉되지 않는 상태가 된다.As shown in the drawing, the center pad semiconductor chip 2 and the edge pad semiconductor chip 4 are seated, and the circuit board 12 on which wire bonding is completed is positioned inside the cavity 50a of the lower die 50. At this time, the ball land 16b formed on the lower surface of the circuit board 12 is in direct contact with the protrusions 52 formed on the bottom surface of the cavity 50a of the lower die 50. Accordingly, the circuit board 12 is in a state in which an area except the ball land 16b is spaced apart from the bottom surface of the cavity 50a of the lower die 50 by a predetermined distance. In addition, since the area of the circuit board 12 is smaller than the area of the cavity 50a of the lower die 50, the side surface of the circuit board 12 has a cavity 50a of the lower die 50. The state does not come into contact with the side surface.

또한, 상기 각각의 돌기(52)에 배큠홀(53)이 형성되어 있을 경우에는, 상기 배큠홀(53)을 통하여 일정 압력의 배큠을 제공함으로써, 봉지 공정중 봉지압력에 의해 상기 회로기판(12)이 움직이지 않도록 한다.In addition, in the case where the back holes 53 are formed in the projections 52, the circuit board 12 is provided by the sealing pressure during the sealing process by providing backing of a constant pressure through the back holes 53. ) Does not move.

이어서, 상기 하금형(50)의 상부에는 일정체적의 캐비티(40a)가 형성된 상금형(40)이 밀착된다. 그런후, 상기 상금형(40)의 캐비티(40a)와 연통된 게이트(42) 를 통해서 일정량의 봉지재(예를 들면, 에폭시몰딩컴파운드)가 고온,고압 상태로 충진된다. 상기 봉지재는 상기 상금형(40)의 캐비티(40a) 및 하금형(50)의 캐비티(50a)에 모두 충진됨으로써, 결국 회로기판(12)의 볼랜드(16b)를 제외한 상,하면 및 측면에 동일한 재질의 봉지부(10)가 형성되고, 상기 회로기판(12)의 볼랜드(16b)는 외측으로 개방된다.Subsequently, the upper mold 40 having a predetermined volume of the cavity 40a is in close contact with the lower mold 50. Then, a certain amount of encapsulant (for example, epoxy molding compound) is filled at high temperature and high pressure through the gate 42 communicating with the cavity 40a of the upper mold 40. The encapsulant is filled in both the cavity 40a of the upper mold 40 and the cavity 50a of the lower mold 50, so that the upper, lower and side surfaces of the circuit board 12 are identical except for the ball lands 16b. An encapsulation portion 10 is formed, and the ball land 16b of the circuit board 12 is opened to the outside.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서 본 발명에 의한 반도체패키지 및 이를 위한 금형에 의하면, 종래와 다르게 회로기판을 중심으로 상,하면에 동일한 재질의 봉지부(예를 들면, 에폭시몰딩컴파운드)가 형성됨으로써, 반도체패키지의 워페이지 현상이 최소화되는 효과가 있다.Therefore, according to the semiconductor package and the mold therefor according to the present invention, unlike in the prior art, the encapsulation portion (for example, epoxy molding compound) of the same material is formed on the upper and lower surfaces of the circuit board, and thus warpage phenomenon of the semiconductor package. This has the effect of being minimized.

또한, 봉지재 및 금형을 통하여 1회의 공정으로 봉지부가 형성됨으로써, 제조 공정이 간략화되고 이에 따라 불량률이 저하됨은 물론, 제조 비용도 절감되는 효과가 있다.In addition, since the encapsulation portion is formed in one step through the encapsulant and the mold, the manufacturing process is simplified, thereby reducing the defective rate and reducing the manufacturing cost.

더불어, 도전성볼이 융착되는 회로기판의 일정영역을 제외한 모든 영역이 봉지재로 봉지됨으로써, 봉지부와 회로기판간의 인터락킹력이 향상되고, 이에 따라 계면박리 억제는 물론, 수분의 흡수를 최대한 억제하는 효과가 있다.In addition, all areas except the predetermined area of the circuit board to which the conductive balls are fused are encapsulated with an encapsulant, thereby improving the interlocking force between the encapsulation part and the circuit board, thereby suppressing interfacial separation and maximizing absorption of moisture. It is effective.

Claims (6)

하면 중앙에 다수의 입출력패드가 형성된 센터패드형 반도체칩;A center pad semiconductor chip having a plurality of input / output pads formed at a center thereof; 상기 센터패드형 반도체칩의 상면에 접착되고, 상면 내주연에는 다수의 입출력패드가 형성된 엣지패드형 반도체칩;An edge pad type semiconductor chip adhered to an upper surface of the center pad type semiconductor chip and having a plurality of input / output pads formed on an inner circumferential surface of the center pad type semiconductor chip; 상기 센터패드형 반도체칩의 하면에 접착된 동시에, 상면에는 다수의 본드핑거를 포함하는 회로패턴이 형성되고, 하면에는 다수의 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되며, 상기 센터패드형 반도체칩의 입출력패드와 대응되는 영역에는 관통공이 형성된 회로기판;While bonded to the lower surface of the center pad semiconductor chip, a circuit pattern including a plurality of bond fingers is formed on the upper surface, a circuit pattern including a plurality of bond fingers and ball land is formed on the lower surface, the center pad semiconductor A circuit board having through holes formed in an area corresponding to the input / output pad of the chip; 상기 센터패드형 반도체칩과 회로기판의 상면에 형성된 본드핑거를 전기적으로 연결함과 동시에, 상기 엣지패드형 반도체칩의 입출력패드와 상기 회로기판의 하면에 형성된 본드핑거를 전기적으로 연결하는 다수의 도전성와이어;A plurality of conductive elements electrically connect the center pad semiconductor chip and the bond finger formed on the upper surface of the circuit board and electrically connect the bond pads formed on the bottom surface of the circuit board with the input / output pad of the edge pad semiconductor chip. wire; 상기 센터패드형 반도체칩, 엣지패드형 반도체칩 및 도전성와이어를 외부 환경으로부터 보호할 수 있도록 상기 회로기판의 상면, 상기 회로기판의 볼랜드를 제외한 하면 및 상기 회로기판의 관통공 내측에 형성된 봉지부; 및,An encapsulation portion formed on an upper surface of the circuit board, a lower surface except a ball land of the circuit board, and an inside of a through hole of the circuit board so as to protect the center pad semiconductor chip, the edge pad semiconductor chip, and the conductive wire from an external environment; And, 상기 회로기판 하면의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 반도체패키지.A semiconductor package comprising a plurality of conductive balls fused to the ball land on the lower surface of the circuit board. 제1항에 있어서, 상기 봉지부는 회로기판의 측면에도 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 1, wherein the encapsulation part is formed on a side surface of the circuit board. 제1항 또는 제2항에 있어서, 상기 회로기판은 하면의 볼랜드 외주연에 커버코트가 코팅되어 있고, 상기 커버코트는 다시 봉지부와 밀착된 것을 특징으로 하는 반도체패키지.The semiconductor package according to claim 1 or 2, wherein the circuit board is coated with a cover coat on the outer periphery of Borland, and the cover coat is in close contact with the encapsulation part. 반도체칩이 접착된 회로기판이 위치되어 상부에 일정 체적의 봉지부가 형성되도록 캐비티가 형성된 상금형; 및,An upper mold in which a cavity is formed such that a circuit board to which a semiconductor chip is bonded is formed so that a predetermined volume of encapsulation is formed thereon; And, 상기 회로기판의 하면에 상기 회로기판의 넓이보다 큰 넓이를 가진 캐비티가 형성되고, 상기 캐비티의 바닥면에는 상기 회로기판중 볼랜드와 직접 접촉되도록 다수의 돌기가 형성된 하금형을 포함하여 이루어진 것을 특징으로 하는 금형.A cavity having an area larger than an area of the circuit board is formed on a lower surface of the circuit board, and a bottom die of the cavity includes a lower die having a plurality of protrusions formed in direct contact with a ball land of the circuit board. Mold. 제4항에 있어서, 상기 돌기의 높이는 상기 회로기판의 하면과 상기 하금형의 캐비티 바닥면이 상호 일정 거리 이격될 수 있는 높이로 형성된 것을 특징으로 하는 금형.The mold according to claim 4, wherein the height of the protrusion is formed at a height such that the bottom surface of the circuit board and the bottom surface of the cavity of the lower mold can be spaced apart from each other by a predetermined distance. 제4항에 있어서, 상기 돌기는 상기 회로기판의 볼랜드와 강하게 밀착되도록 배큠이 제공되는 배큠홀(Vacuum Hole)이 더 형성된 것을 특징으로 하는 금형.The mold according to claim 4, wherein the protrusion is further formed with a vacuum hole provided with a vacuum so as to be in close contact with the ball land of the circuit board.
KR1020010016986A 2001-03-30 2001-03-30 Semiconductor package and mold for it KR100729024B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010016986A KR100729024B1 (en) 2001-03-30 2001-03-30 Semiconductor package and mold for it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010016986A KR100729024B1 (en) 2001-03-30 2001-03-30 Semiconductor package and mold for it

Publications (2)

Publication Number Publication Date
KR20020076839A KR20020076839A (en) 2002-10-11
KR100729024B1 true KR100729024B1 (en) 2007-06-14

Family

ID=27699390

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010016986A KR100729024B1 (en) 2001-03-30 2001-03-30 Semiconductor package and mold for it

Country Status (1)

Country Link
KR (1) KR100729024B1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825623A (en) * 1995-12-08 1998-10-20 Vlsi Technology, Inc. Packaging assemblies for encapsulated integrated circuit devices
KR19990056987A (en) * 1997-12-29 1999-07-15 윤종용 High density mounting semiconductor package and mold for manufacturing semiconductor package
KR20000040586A (en) * 1998-12-18 2000-07-05 윤종용 Multi chip package having printed circuit substrate
KR20010068513A (en) * 2000-01-06 2001-07-23 윤종용 Stacked chip package comprising circuit board with windows
KR20020060311A (en) * 2001-01-10 2002-07-18 윤종용 Structures and manufacturing method of stack chip package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825623A (en) * 1995-12-08 1998-10-20 Vlsi Technology, Inc. Packaging assemblies for encapsulated integrated circuit devices
KR19990056987A (en) * 1997-12-29 1999-07-15 윤종용 High density mounting semiconductor package and mold for manufacturing semiconductor package
KR20000040586A (en) * 1998-12-18 2000-07-05 윤종용 Multi chip package having printed circuit substrate
KR20010068513A (en) * 2000-01-06 2001-07-23 윤종용 Stacked chip package comprising circuit board with windows
KR20020060311A (en) * 2001-01-10 2002-07-18 윤종용 Structures and manufacturing method of stack chip package

Also Published As

Publication number Publication date
KR20020076839A (en) 2002-10-11

Similar Documents

Publication Publication Date Title
KR100260997B1 (en) Semiconductor package
US7327020B2 (en) Multi-chip package including at least one semiconductor device enclosed therein
KR100559664B1 (en) Semiconductor package
JP5095074B2 (en) Package stacking structure
US20020006686A1 (en) Die to die connection method and assemblies and packages including dice so connected
US20020140085A1 (en) Semiconductor package including passive elements and method of manufacture
US20070069371A1 (en) Cavity chip package
US5796038A (en) Technique to produce cavity-up HBGA packages
KR101059629B1 (en) Semiconductor Package Manufacturing Method
US20040217451A1 (en) Semiconductor packaging structure
US6650005B2 (en) Micro BGA package
KR100729024B1 (en) Semiconductor package and mold for it
JPH05160296A (en) Resin sealing method of semiconductor integrated circuit bare chip
KR20010063236A (en) Stack package and manufacturing method thereof
US6404067B1 (en) Plastic ball grid array package with improved moisture resistance
US20040061222A1 (en) Window-type ball grid array semiconductor package
KR100443516B1 (en) Stack package and manufacturing method thereof
KR100610916B1 (en) Semiconductor package
KR100549299B1 (en) Semiconductor package and its manufacturing method
KR100357883B1 (en) Semiconductor device and its manufacturing method
KR100533761B1 (en) semi-conduSSor package
KR100473336B1 (en) semiconductor package
KR100421777B1 (en) semiconductor package
KR100459820B1 (en) Chip scale package and its manufacturing method
KR100400827B1 (en) semiconductor package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130607

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20140603

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20150604

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20160607

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20170602

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20180605

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20190604

Year of fee payment: 13