201234545 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種攜帶式快閃記憶體儲存裝置的封裝 結構及其封裝方法，尤指一種適用於USB 3.0通訊協定的 攜帶式快閃兄憶體儲存裝置的封裝結構及其封裝方法。 【先前技術】201234545 VI. Description of the Invention: [Technical Field] The present invention relates to a package structure and a package method of a portable flash memory storage device, and more particularly to a portable flash brother review for a USB 3.0 protocol The package structure of the body storage device and the packaging method thereof. [Prior Art]
在現代社會中，為了能機動性存取使用電腦設備或相 關應用設備巾的資料，故使用者會使用既有之攜帶式快閃 記憶體儲存裝置，以便將所需資料便利地隨身攜帶至位於 他處的設備存取使用，且因近年來攜帶式快閃記憶體儲存 裝置的儲存容量增大，故攜帶式快閃記憶體儲存裝置需要 支援傳輸速度快速的USB 3.0(通用序列匯流排3〇)，既有 支援USB 3.0之攜帶式快閃記憶體儲存裝置係在一表面設 有一個以上晶片的基板一側電連接有一符合USB 3 〇通訊 協定的接頭，並在基板外包覆一層保護該基板用的外殼， 即完成了既有支援USB 3.0之攜帶式快閃記憶體儲存裝 置。唯，因既有支援USB 3.0之攜帶式快閃記憶體儲存裝 置是分開組裝’故組裝過程繁複，且體積較大，插設在筆 記型電腦或相關應用設備的插槽時其外崎交且# 丄 丨从奋易擋到相鄰丨 插槽，造成使用上的不便。以上所述者皆盔 -----------------------為既術未3 理想之處，實有待進一步檢討，並謀求可行的解'決方案一: 【發明内容】 201234545 有鑑於既有攜帶式快閃記憶體儲存裝置結構的缺點， 本發明的主要目的在於提供一種攜帶式快閃記憶體儲存裝 置的封裝結構，其可有效縮小該攜帶式快閃記憶體儲存裝 置的尺寸。 為達成料目的採取的主要技術手段係令前述攜帶式 快閃S己憶體儲存裝置的封裝結構包括有： 一基板，其上分別形成有一組以上的晶片接點、一組 端子接點及連接前述晶片接點、端子接點的線路； 一個以上的記憶體晶片，係電連接於基板的其中一組 晶片接點上； ^ 一端子模組，主要係於一絕緣的連接件上分設有一第 一端子組及一第二端子組，該第一端子組的各端子一端係 位於連接件頂面上方，另端係與基板上的端子接點連接； 又第二端子組的各端子一端係位於連接件頂面，另端則與 基板上的其他端子接點電連接； 一外封膠層’係覆蓋於基板上並包覆其上的記憶體晶 片，而令端子模組的連接件頂面露出於外封膠層外，進而 使連接件與其頂面所設第一'第二端子組的端子一端構成 一接頭；其中： 第一、第二端子組在該連接件頂面的位置係對應於USB-3.0通訊協定的連接器。 前述封裝結構係在基板上設有連接件的一端形成有一 接頭，故不須再另外外接接頭，且因第一端子組與第二端子 组在連接件頂面的位置係對應於USB 3〇通訊協定的連接 态，故可透過USB 3.0通訊協定與連接器連結並傳輸訊號， .201234545 故本發明可構成一支援USB 3 〇通訊協定的攜帶式快閃記 ^绪存裝置’且一外封踢層覆設在基板上並包覆設於基 板t的記憶體晶片，可保護該基板與設於該基板上的記憶 體曰曰片，不需另外在基板外包覆保護外殼，故可有效縮小 該攜帶式快閃記憶體儲存裝置的尺寸，且簡化封裝過程。 本發月又一目的在提供一種前述攜帶式快閃記憶體儲 存裝置的封裝方法，其包括以下步驟： 鲁 提供一基材； 在前述基材上定義一個以上的基板，每一基板上分別形 成 i以上的晶片接點、端子接點及連接晶片接點、端子接 點的線路； 在各基板上安裝晶片，並使晶片與基板上的晶片接點構 成電連接； 在刚述基板上安裝一端子模組，並使端子模組上的端子 與基板上的端子接點構成電連接； # 在前述基材上進行封膠以形成外封膠層，令外封膠層覆 蓋各基板，並使其上的端子模組局部露出，以構成一接頭； 以基板為單位’對前述基材進行裁切。 則述封裝方法係將一外封膠層覆設在各基板上並包覆 在記憶體晶片外’以保護該基板與該基板上的記憶體晶 片，不需另外在基板外包覆外殼，故可有效縮小該攜帶式 快閃δ己憶體儲存裝置的尺寸；且該外封膠層覆蓋各基板時使 基板上的端子模組局部露出，以構成有一接頭，故不須再另 外外接接頭，可簡化封裝過程，故具有製造方便的優點。 201234545 【實施方式】 以下配合圖式與本發明之較佳實施例，進一步閣述本 發明為達成預定發明目的所採取的技術手段。 請參閱圖1、圖2與圖1 〇所示，該攜帶式快閃記憶體 儲存裝置係在一基板1 0上設有一組以上的晶片接點（圖中 未示），且在該基板10上的一端設有一組端子接點1〇1，且 該基板10上設有連接前述晶片接點與端子接點1〇1的線路 (圖中未示），一個以上的記憶體晶片11係電連接於該基板 1〇的其中一組晶片接點上’在基板1〇的端子接點上 係設有一端子模組20，且一外封膠層30覆蓋於基板彳〇上 並包覆其上的記憶體晶片11，且使該基板1 〇上的端子模組 20局部露出，以構成一接頭。 又在此較佳實施例中，該基板10上設有一個以上的被 動元件102,且該基板1〇上的端子接點1〇1的數量可為九 個。 該記憶體晶片11的數量可為一個，且該記憶體晶片，】 可為NAND Flash ;在此較佳實施例中，該基板1〇上另設 有一個以上的控制晶片12，其係電連接於基板彳〇中的另一 組晶片接點上，且該控制晶片彳2的數量可為一個。 該端子模組20主要係於一絕緣的連接件21上分設有 -第-端子組22及一第二端子，组23,請參閱，與圖2 所不’圖2係為從圖】的剖面線2_2剖開之剖面圖，該第 一端子組22的各端子一端係位於連接件21頂面上方，另 端係與基板to上的端子接點101連接；第二端子組23的 各端子一端係位於連接件21頂面，另端則與基板1〇上的 .201234545 其他端子接·點101電連接；該第一端子·组22的-端在該連 接件21頂面排列成一排’請參閱圖1與圖1〇所示，圖1〇 係為從圖1的剖面線10-10剖開之剖面圖，而該第二端子 且23的端係在連接件21頂面排列成另一排，故第一端子 組22與第二端子組23在連接件21的頂面排列成前後兩 排’且位置係對應於_ USB 3〇通訊協定的電連接器。 又請參閱圖1'圖2與圖1〇所示，在此較佳實施例中， 該連接件21上形成有複數溝槽211，該第一端子組22各端 子的一端係位於該連接件21的溝槽上方且該連接件 21的内側端底側以水平方向凸設有一卡合塊212，當該外封 膠層30覆設在基板1〇上時，該卡合塊212可讓連接件 與外封膠層30卡合的更緊密；且該連接件21靠近端子接 點1〇1 —端的頂側以水平方向巴設有一固定塊213，該固定 塊213也有加強該連接件21與外封膠層3〇卡合結構的效 果。在此較佳實施例中，該第一端子址22巾的端子數量可 •為五個’且該第一端子組22的各端子另端係分別固定在該 基板10上由左至右數來第…三、五 '七、九個端子接點 101 ’該第一端子組22中的各端子分別具有一垂直部222 與一彈片狀的電接觸部223,該電接觸部223係穿過於該連 接件21並位於該連接件21上對應溝槽211上方，並位於 該連接件21頂面的上方β 在此較佳實施例中，該第二端子組23中的端子數量可 為四個，且該第二端子組23的各端子一端係位於連接件21 頂面，並分別構成一電接觸部，另端係分別固定在該基板 1〇上由左至右數來第二、四、六、八個端子接點1〇1。 7 201234545 該外封膠層30係覆蓋於基板1〇上並包覆設於基板上 的記憶體晶片11、控制晶片12、被動元件102…等元件， 而令端子模組20的連接件21頂面路出於外封膠層外， 進而使連接件21與其頂面所設第一、第二端子組22、23 的端子一端構成一接頭。 在此較佳實施例中’該記憶體晶片11與該控制晶片’ 2 係透過複數導線1 3與該基板10上相對應的晶片接點】〇4 電連接’且該導線13可透過打線（wire bonding)構成；— 個以上的内封膠層14係覆設在各導線13外用以固定並保 護該導線13,且該内封膠層14係覆設在該控制晶片彳之外 且包覆連接該控制晶片12與基板10的導線13。 前述封裝結構係在基板1 0上設有端子模組2〇的一端 直接形成有一插接電連接器的接頭，故不須再另外外接接 頭；且因第一端子組22與第二端子組23在連接件21的頂 面分別排列成兩排，且第一端子組22與第二端子組23在連 接件21頂面的位置係對應於USB 3.0通訊協定的電連接 器，故可形成有一對應於USB 3.0通訊協定電連接器的接 頭，故本發明可形成適用於USB 3 〇通訊協定的攜帶式快 閃記憶體儲存裝置；且因本發明直接用外封膠層3〇覆蓋於 基板1 〇上並包覆設於基板上的記憶體晶片n '控制晶片 12、被動元件1〇2…等元件，以保護該基板1〇與該基板忉 上的兀件，故不需另外在基板1〇外包覆外殼，故可有效縮 小該搞帶式快閃記憶體儲存裝置的尺寸，且可簡化組裝過 程。 本發明另提供一種前述攜帶式快閃記憶體儲存裝置的 201234545 封裝方法，請參閱圖3所示，係提供一基材彳，該基材] 可為印刷電路板，在該基材1上定義一個以上的基板1Q， 又在每一基板10上形成一組以上的晶片接點104，且在每 一基板10上的一端分設有一組端子接點1〇1，且各基板1〇 上設有連接前述晶片接點104與端子接點1〇1的線路（圖中 未不）；請參閱圖4所示，在各基板1〇上安裝一個以上的 被動元件102;請參閱圖5與圖9所示，並在各基板上 φ女裝一個以上的記憶體晶片11與一個以上的控制晶片 1 2，並使該記憶體晶片1 1及控制晶片i 2與基板彳〇上的晶 片接點104分別構成電連接，該記憶體晶片]，及控制晶片 1 2的數量可分別為一個； 在此較佳實施例中，該記憶體晶片]】及控制晶片^ 2 與基板10上的晶片接點104分別構成電連接的方式是用打 線接合（wire-bonding)’該記憶體晶片η及控制晶片12上 係分設有複數金屬接點，且將複數導線彳3連接複數金屬接 • 點與基板1 〇上的晶片接點1 04，讓該記憶體晶片1 ]及控 制晶片1 2與基板1 〇上的晶片接點]〇4分別構成電連接； 請參閱圖6與圖9所示，接下來以點膠的方式在打線處形 成内封膠層14以固定該導線13;如果是用其他連接法，如 覆晶.方式.構成電連接，則可省略點膠的步驟。 請參閱圖7所示’先將第一端子組22及第二端子組23 與一連接件21連接組成一端子模組2〇後，在前述各基板 10上安裝該端子模組20,第一端子組22及第二端子組23 與基板10上的端子接點1〇1構成電接連，且第一端子組 22及第一端子組23支撐該連接件21該連接件μ懸空， 9 201234545 各基板1〇安裝完該端子模組20後的剖面圖便如圖9所干. 請參閱圖8所不，此時在前述基材]上進行封膠以形成 膠層3〇’令外⑽層3G覆蓋各基板1〇,且使該連接件21 頂面露出’且外封膠層3G會填滿該連接件21與該基板^ 之間’以進-步支樓固定該連接件21;最後以基板1〇 位，對前述基# 1進行裁切，即完成了該攜帶式快閃記怜 體儲存裝置的封裝步驟。 "In modern society, in order to be able to access the data of computer equipment or related application equipment, the user can use the existing portable flash memory storage device to conveniently carry the required information to the location. The device access is used elsewhere, and since the storage capacity of the portable flash memory storage device has increased in recent years, the portable flash memory storage device needs to support the USB 3.0 with high transmission speed (universal serial bus 3〇) The portable flash memory storage device supporting USB 3.0 is electrically connected to a connector conforming to the USB 3 〇 communication protocol on the side of the substrate having more than one wafer on the surface, and is covered with a layer of protection on the substrate. The housing for the substrate completes the portable flash memory storage device that supports USB 3.0. However, because the portable flash memory storage device that supports USB 3.0 is separately assembled, the assembly process is complicated and large, and it is inserted in the slot of the notebook computer or related application device.丄丨 From the end to the adjacent slot, it is inconvenient to use. All of the above are helmets ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Solution 1: [Invention] The present invention is directed to providing a package structure for a portable flash memory storage device, which can effectively reduce the carrying capacity. The size of the flash memory storage device. The main technical means for achieving the objective is that the package structure of the portable flash memory device includes: a substrate on which more than one set of wafer contacts, a set of terminal contacts and connections are respectively formed. The circuit of the wafer contacts and the terminal contacts; one or more memory chips are electrically connected to one of the chip contacts of the substrate; ^ a terminal module is mainly provided on an insulating connecting member a first terminal group and a second terminal group, wherein one end of each terminal of the first terminal group is located above the top surface of the connecting member, the other end is connected with the terminal contact on the substrate; and the end of each terminal of the second terminal group is Located on the top surface of the connector, the other end is electrically connected to other terminal contacts on the substrate; an outer sealing layer is overlying the substrate and covering the memory chip thereon, and the terminal of the terminal module is connected The surface is exposed outside the outer sealing layer, so that the connecting member forms a joint with the terminal end of the first 'second terminal group provided on the top surface thereof; wherein: the positions of the first and second terminal groups on the top surface of the connecting member are Corresponding to Connector for the USB-3.0 protocol. The foregoing package structure is formed with a joint at one end of the substrate on which the connecting member is disposed, so that no external joint is required, and the position of the first terminal group and the second terminal group on the top surface of the connecting member corresponds to USB 3〇 communication. The connection state of the protocol, so that the signal can be connected and transmitted through the USB 3.0 protocol, .201234545. Therefore, the present invention can constitute a portable flash memory device that supports the USB 3 protocol, and an outer layer of the kick layer. The memory chip is disposed on the substrate and covered on the substrate t, and the substrate and the memory chip disposed on the substrate can be protected, and the protective case can be effectively covered without separately covering the substrate. The size of the portable flash memory storage device and simplify the packaging process. A further object of the present invention is to provide a packaging method for the aforementioned portable flash memory storage device, comprising the steps of: providing a substrate; defining one or more substrates on the substrate, respectively forming on each substrate a wafer contact, a terminal contact, and a line connecting the wafer contact and the terminal contact; mounting a wafer on each substrate, and electrically connecting the wafer to the wafer contact on the substrate; mounting a substrate on the substrate The terminal module is configured to make an electrical connection between the terminal on the terminal module and the terminal contact on the substrate; # sealing on the substrate to form an outer sealing layer, so that the outer sealing layer covers each substrate, and The terminal module thereon is partially exposed to form a joint; the substrate is cut in units of a substrate. The encapsulation method covers an external encapsulant layer on each substrate and is coated on the outside of the memory wafer to protect the substrate and the memory wafer on the substrate, without separately covering the substrate with the outer casing. The size of the portable flash δ hex memory storage device can be effectively reduced; and the outer sealing layer covers the respective substrates to partially expose the terminal module on the substrate to form a connector, so that no external connector is needed. The packaging process can be simplified, so that it has the advantage of being convenient to manufacture. 201234545 [Embodiment] The following is a technical means for achieving the intended purpose of the present invention in conjunction with the preferred embodiments of the present invention. Referring to FIG. 1 , FIG. 2 and FIG. 1 , the portable flash memory storage device is provided with more than one set of wafer contacts (not shown) on a substrate 10 , and the substrate 10 is disposed on the substrate 10 . The upper end is provided with a set of terminal contacts 1〇1, and the substrate 10 is provided with a line connecting the wafer contacts and the terminal contacts 1〇1 (not shown), and more than one memory chip 11 is electrically connected. Connected to one of the wafer contacts of the substrate 1 'a terminal module 20 is disposed on the terminal contact of the substrate 1 , and an outer sealant layer 30 is overlaid on the substrate and covered thereon The memory chip 11 is partially exposed to the terminal module 20 on the substrate 1 to form a joint. In this preferred embodiment, more than one passive component 102 is disposed on the substrate 10, and the number of terminal contacts 1〇1 on the substrate 1 can be nine. The number of the memory chips 11 may be one, and the memory chip may be a NAND flash; in the preferred embodiment, the substrate 1 is further provided with one or more control wafers 12, which are electrically connected. The other set of wafer contacts in the substrate stack, and the number of the control wafers 2 may be one. The terminal module 20 is mainly provided with an -in-terminal group 22 and a second terminal, and a group 23, as shown in FIG. 2, which is not shown in FIG. A cross-sectional view of the section line 2_2, wherein one end of each terminal of the first terminal group 22 is located above the top surface of the connector 21, and the other end is connected to the terminal contact 101 on the substrate to; the terminals of the second terminal group 23 One end is located on the top surface of the connecting member 21, and the other end is electrically connected to the other terminal connection point 101 of the .201234545 on the substrate 1; the end of the first terminal group 22 is arranged in a row on the top surface of the connecting member 21' Referring to FIG. 1 and FIG. 1A, FIG. 1 is a cross-sectional view taken along line 10-10 of FIG. 1, and the ends of the second terminals 23 are arranged on the top surface of the connecting member 21 to form another In one row, the first terminal group 22 and the second terminal group 23 are arranged in the front and rear rows on the top surface of the connector 21 and the position corresponds to the electrical connector of the _USB 3〇 communication protocol. Referring to FIG. 1 and FIG. 1 and FIG. 1 , in the preferred embodiment, the connecting member 21 is formed with a plurality of grooves 211 , and one end of each terminal of the first terminal set 22 is located at the connecting member. A latching block 212 is protruded from the bottom surface of the connecting member 21 in a horizontal direction. When the outer sealing layer 30 is disposed on the substrate 1 , the engaging block 212 can be connected. The connecting member 21 is closer to the outer sealing layer 30; and the connecting member 21 is disposed near the top side of the terminal contact 1〇1 end in a horizontal direction with a fixing block 213, and the fixing block 213 also strengthens the connecting member 21 and The effect of the outer sealant layer 3 〇 snap structure. In the preferred embodiment, the number of terminals of the first terminal address 22 can be five's, and the terminals of the first terminal group 22 are respectively fixed on the substrate 10 from left to right. The third, fifth 'seven, nine terminal contacts 101' each of the terminals in the first terminal group 22 has a vertical portion 222 and a resilient electrical contact portion 223, the electrical contact portion 223 is passed through The connecting member 21 is located above the corresponding groove 211 of the connecting member 21 and above the top surface of the connecting member 21. In the preferred embodiment, the number of terminals in the second terminal set 23 can be four. And one end of each terminal of the second terminal group 23 is located on the top surface of the connecting member 21, and respectively constitutes an electrical contact portion, and the other ends are respectively fixed on the substrate 1 由 from left to right to the second, fourth, fourth, Six or eight terminal contacts 1〇1. 7 201234545 The outer sealant layer 30 covers the substrate 1 and covers the memory chip 11, the control wafer 12, the passive component 102, etc. on the substrate, and the connector 21 of the terminal module 20 is topped. The surface path is outside the outer sealing layer, and the connecting member 21 and the top end of the first and second terminal groups 22, 23 provided on the top surface thereof form a joint. In the preferred embodiment, the memory chip 11 and the control chip 2 are electrically connected to the corresponding wafer contacts 〇4 through the plurality of wires 13 and the wires 13 are permeable to the wires ( Wire bonding); more than one inner sealing layer 14 is disposed on each of the wires 13 for fixing and protecting the wire 13, and the inner sealing layer 14 is coated on the outer surface of the control wafer and coated The control wafer 12 and the wires 13 of the substrate 10 are connected. The foregoing package structure directly forms a connector for inserting the electrical connector on one end of the substrate 10 on which the terminal module 2 is disposed, so that no additional external connector is required; and the first terminal group 22 and the second terminal group 23 are The top surfaces of the connecting members 21 are respectively arranged in two rows, and the positions of the first terminal group 22 and the second terminal group 23 on the top surface of the connecting member 21 correspond to the electrical connectors of the USB 3.0 protocol, so that a corresponding correspondence can be formed. In the connector of the USB 3.0 communication protocol electrical connector, the present invention can form a portable flash memory storage device suitable for the USB 3 〇 communication protocol; and the invention directly covers the substrate 1 with the outer sealing layer 3 〇 The memory chip n' is mounted on the substrate to control the wafer 12, the passive component 1〇2, etc. to protect the substrate 1 and the substrate on the substrate, so that it is not required to be additionally on the substrate 1 The outer cover of the outer casing can effectively reduce the size of the tape-type flash memory storage device and simplify the assembly process. The present invention further provides a 201234545 packaging method for the aforementioned portable flash memory storage device. Referring to FIG. 3, a substrate raft is provided, which can be a printed circuit board on which the substrate 1 is defined. One or more substrate contacts 1Q, one or more wafer contacts 104 are formed on each substrate 10, and a set of terminal contacts 1〇1 is disposed at one end of each substrate 10, and each substrate is disposed on the substrate 1 There is a line connecting the wafer contact 104 and the terminal contact 1〇1 (not shown); as shown in FIG. 4, one or more passive components 102 are mounted on each substrate 1; see FIG. 5 and FIG. 9, and on each substrate, more than one memory wafer 11 and one or more control wafers 12, and the memory wafer 11 and the control wafer i 2 are connected to the wafer on the substrate Each of the memory chips, and the number of control wafers 1 2 may be one; in the preferred embodiment, the memory chip and the control wafer 2 are connected to the wafers on the substrate 10. The way in which the dots 104 respectively form an electrical connection is by wire bonding (wire-bo Nding) 'The memory wafer η and the control wafer 12 are provided with a plurality of metal contacts, and the plurality of wires 彳3 are connected to the plurality of metal contacts and the wafer contacts 104 on the substrate 1 to make the memory The wafer 1] and the control wafer 12 and the wafer contacts on the substrate 1 are respectively electrically connected; as shown in FIG. 6 and FIG. 9, the adhesive layer is formed at the bonding line by dispensing. 14 to fix the wire 13; if other connection methods, such as flip chip, are used to form an electrical connection, the step of dispensing may be omitted. Referring to FIG. 7 , the first terminal block 22 and the second terminal group 23 are connected to a connector 21 to form a terminal module 2 , and the terminal module 20 is mounted on each of the substrates 10 . The terminal group 22 and the second terminal group 23 are electrically connected to the terminal contacts 1〇1 on the substrate 10, and the first terminal group 22 and the first terminal group 23 support the connector 21, and the connector μ is suspended, 9 201234545 The cross-sectional view of the substrate 1 after mounting the terminal module 20 is as shown in Fig. 9. Please refer to Fig. 8 for the case where the substrate is coated on the substrate to form a glue layer 3'. 3G covers each substrate 1〇, and the top surface of the connecting member 21 is exposed 'and the outer sealing layer 3G fills the connecting member 21 and the substrate ^' to fix the connecting member 21 in an advance step; The substrate 1 is cut by the substrate 1 to complete the packaging step of the portable flash memory storage device. "
因本發明係在各基板10上直接形成一插接電連接器的 接頭，且係直接用外封膠層30包覆在基板1〇外且可同 時保護該基板10與該基板10上的記憶體晶片11、控制晶 片12、被動元件102...等元件，故不需另外在基板外包 覆保護用的外殼，故可有效縮小該„式快閃記憶體儲存 裝置的尺寸，且可簡化組裝過程。Because the present invention directly forms a connector for inserting the electrical connector on each of the substrates 10, and directly covering the substrate 1 with the outer sealant layer 30 and simultaneously protecting the memory on the substrate 10 and the substrate 10. The components such as the bulk wafer 11, the control wafer 12, the passive component 102, etc., so that it is not necessary to additionally cover the outer casing of the protective substrate, so that the size of the flash memory storage device can be effectively reduced and simplified. Assembly process.
以上所述僅為本創作之較佳實施例，並非對本創作作 任何形式上之限制’雖然本創作已以較佳實施例揭露如 上，然而並非用以限定本創作，任何熟悉本專業的技術人 員，在不脫離本創作技術方案的範圍内，當可利用上述揭 示的技術内容作出些許更動或修飾為等同變化的等效實施 例，但凡是未脫離本創作技術方案的内容，依據本創作的 技術實質對以上實施例所作的任何簡單修改、等同變化與 修飾’均仍屬於本創作技術方案的範圍内。 【圖式簡單說明】 圖1係為本發明一較佳實施例之外觀圖。 圖2係為本發明一較佳實施例之剖面圖。 圖3係為本發明一較佳實施例之一封裝步驟示意圖。 10 201234545 圖4係為本發明一較佳實施例之第二封 θ ς^ 、步帮示意圖 係為本發明一較佳實施例之第三封裝一立 圖係為本發明一較佳實施例之第四封裝步驟示今圖 圖7係為本發明一較佳實施例之第五封裝步立 〇 ^ 娜不忍圖0 圖8係為本發明一較佳實施例之第六封裝步驟示专圖 圖9係為本發明一較佳實施例未覆設外封膠 θ @〈剖面 圆。 鲁圖1 0係為本發明一較佳實施例之另一剖面圖。 【主要元件符號說明】 1基材 1 〇基板 1〇1端子接點 102被動元件 1 04晶片接點 11記憶體晶片 12控制晶片 13金屬導線 14内封膠層 20端子模組 21連接件 211溝槽 21 2卡合塊 213固定塊 22第一端子組 222垂直部 223電接觸部 23第二端子組 3〇外封膠層 11The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the present invention, and any skilled person skilled in the art. The equivalents of the above-discussed technical content may be modified or modified to equivalent variations, without departing from the spirit and scope of the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments are still within the scope of the present technical solution. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an external view of a preferred embodiment of the present invention. Figure 2 is a cross-sectional view of a preferred embodiment of the present invention. 3 is a schematic diagram of a packaging step in accordance with a preferred embodiment of the present invention. 10 201234545 FIG. 4 is a second embodiment of a preferred embodiment of the present invention. The third package is a preferred embodiment of the present invention. FIG. 7 is a fifth package step of the preferred embodiment of the present invention. FIG. 8 is a diagram showing a sixth package step according to a preferred embodiment of the present invention. 9 is a cross-section of the outer sealant θ @ < cross section of a preferred embodiment of the invention. Lutu 10 is another cross-sectional view of a preferred embodiment of the invention. [Main component symbol description] 1 substrate 1 〇 substrate 1 〇 1 terminal contact 102 passive component 1 04 wafer contact 11 memory wafer 12 control wafer 13 metal wire 14 inner sealing layer 20 terminal module 21 connector 211 groove Slot 21 2 snap block 213 fixing block 22 first terminal group 222 vertical portion 223 electrical contact portion 23 second terminal group 3 〇 outer sealant layer 11