CN104885217A - Multiple die stacking for two or more die - Google Patents

Multiple die stacking for two or more die Download PDF

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Publication number
CN104885217A
CN104885217A CN201380067609.4A CN201380067609A CN104885217A CN 104885217 A CN104885217 A CN 104885217A CN 201380067609 A CN201380067609 A CN 201380067609A CN 104885217 A CN104885217 A CN 104885217A
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CN
China
Prior art keywords
microelectronic element
contact
module
microelectronic
contacts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201380067609.4A
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Chinese (zh)
Inventor
韦勒·佐尼
贝尔加桑·哈巴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
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Filing date
Publication date
Priority claimed from US13/658,401 external-priority patent/US8952516B2/en
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of CN104885217A publication Critical patent/CN104885217A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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  • Theoretical Computer Science (AREA)
  • Semiconductor Memories (AREA)

Abstract

A microelectronic package (1310) can include a substrate (1340) having first and second surfaces (1341, 1342), and first and second microelectronic elements (1320, 1330). The substrate (1340) can have substrate contacts (1347a, 1347b) at a first surface (1341) and a plurality of terminals (1350) at a second surface (1342). Element contacts (1324, 1334) of the microelectronic elements 1320, 1330 can be joined with corresponding ones of the substrate contacts (1347a, 1347b). A front surface (1331) of the second microelectronic element (1330) can partially overlie a rear surface (1322) of the first microelectronic element (1320) and can be attached thereto. The element contacts (1324) of the first microelectronic element (1320) can be arranged in an area array and can be flip chip bonded with the substrate contacts (1347a). The element contacts (1334) of the second microelectronic element (1330) can be joined with the substrate contacts (1347b) by conductive masses (1375).

Description

The polycrystalline unit of two or more wafer is stacking
The cross reference of related application
The application is the U.S. Patent application No.13/658 submitted on October 23rd, 2012, the continuation application of 401, U.S. Patent application No.13/658,401 is the U.S. Patent application No.13/306 submitted on November 29th, 2011, the part continuation application of 203, U.S. Patent application No.13/306,203 require the U.S. Provisional Patent Application No.61/477 that on April 21st, 2011 submits to, the rights and interests of 820, its disclosure is incorporated to herein by reference.Following jointly all applications are incorporated to herein by reference, comprising: all in the U.S. Provisional Patent Application 61/477,877,61/477/883 and 61/477,967 of application on April 21st, 2011.
Background technology
The present invention relates to stacking micromodule, manufacture the method for this assembly, and for the parts of this assembly.
Semiconductor chip is set to independent pre-packaged units usually.Standard chips has with the flattened rectangular body before large, should before there is the contact of the internal circuit being connected to chip.Each independent chip is typically installed in a package, and encapsulation is arranged on circuit board such as printed circuit board again, encapsulates the conductor contact of chip being connected to circuit board.In a lot of conventional design, the area of the area ratio chip that chip package takies in the circuit board itself is much larger.
As with reference to have in the disclosure of flat chip above " area of chip " that use should be understood to refer to as described in before area.In " flip-chip " design, in the face of the face of package substrate before chip, that is, by soldered ball or other Connection Elements, the contact on chip carrier and chip is bonded directly to the contact of chip carrier.Chip carrier can be bonded to circuit board again by the terminal covered before chip." flip-chip " design provides the layout of relative compact; The area of the circuit board that each chip takies is equal to or slightly greater than the area before chip, such as, at the common United States Patent (USP) 5,148 transferred the possession of, 265,5,148,266 and 5,679, disclosed in some embodiment in 977, its whole disclosure is incorporated to herein by reference.
The tightness that theres is provided of mounting technique of some innovation close to or equal the tightness of conventional flip-chips bonding.Can be equal to or slightly greater than chip itself area circuit board area in the encapsulation of accommodating one single chip be commonly called " wafer-level package ".
Except minimizing the area of plane of the circuit board taken by micromodule, also need to produce a kind of whole height perpendicular to circuit board plane or the less chip package of size.This thin microelectronics Packaging allows the circuit board being wherein provided with encapsulation to be close to adjacent structure and places, and reduces the overall dimensions comprising the product of circuit board thus.
Various proposals for arranging multiple chip in single package or module have been proposed.In " multi-chip module " of routine, chip is arranged on single package substrate abreast, then this package substrate can be mounted to circuit board.This method is only to provide the limited reduction of the gross area of the circuit board shared by chip.The gross area is still greater than the total surface area of each chip in module.
Multiple chip package has also been proposed to arrange in (namely multiple chip is placed to a layout on another) " stacking ".In stacked arrangement, multiple chip can be arranged in the area of the circuit board less than the gross area of chip.Such as, at above-mentioned United States Patent (USP) 5,679,977,5,148,265 and 5, disclose some stacked chip arrangements in some embodiment of 347,159, its whole disclosure is incorporated to herein by reference.Also be incorporated to that United States Patent (USP) 4,941,033 is herein open a kind ofly to be arranged by reference, its chips one is stacking in another Shangdi, and interconnected amongst one another by the conductor on so-called " wiring membrane " that be associated with chip.
Although multi-chip package has obtained certain development, in order to make its minimized in size and improve its performance, still need further improvement.Feature of the present invention is by the constitution realization by micromodule described below.
Summary of the invention
According to aspects of the present invention, a kind of microelectronics Packaging can comprise and has relative first surface and the substrate of second surface, and has the first microelectronic element of front surface and second microelectronic element of the first surface in the face of substrate.Substrate can have the multiple substrate contact at first surface place and the multiple terminals at second surface place, for microelectronics Packaging being connected at least one parts of package outside.Each microelectronic element has the multiple element contacts at its front surface place.The element contacts of each microelectronic element can be connected with corresponding substrate contact.The front surface of the second microelectronic element partly can cover and be attached to the rear surface of the first microelectronic element.The element contacts of the first microelectronic element can be arranged in the battle array of face and with first group of substrate contact flip-chip bonding.The element contacts of the second microelectronic element is connected by conducting block and second group of substrate contact.
In a particular example, the element contacts of the second microelectronic element can protrude from outside the lateral edges of the first microelectronic element.In one embodiment, at least one in the first microelectronic element and the second microelectronic element comprises memory component.In one exemplary embodiment, microelectronics Packaging also can comprise the multiple lead-in wires extending to terminal from least some substrate contact.This lead-in wire can be used for carrying address signal with at least one in the first microelectronic element and the second microelectronic element to memory component addressing.In one example, the signal of at least some terminal between to can be used for carrying in each terminal and the first microelectronic element and the second microelectronic element each or at least one in reference potential.
In one embodiment, microelectronics Packaging also can comprise multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to substrate.In a particular example, multiple 3rd microelectronic element can be arranged to stacked structure, and each 3rd microelectronic element has the facing front surface of the front surface of three microelectronic element adjacent with or rear surface or rear surface.In one embodiment, multiple 3rd microelectronic element can be arranged to planar structure, and each 3rd microelectronic element has the facing peripheral surface of the peripheral surface of three microelectronic element adjacent with.
In one exemplary embodiment, second microelectronic element can comprise volatibility RAM, each 3rd microelectronic element can comprise non-volatile flash memory, and the first microelectronic element can comprise the processor being mainly used in controlling external module and the data between the second microelectronic element and the 3rd microelectronic element and transmitting.In one example, the second microelectronic element can comprise volatibility frame buffer memory element, and each 3rd microelectronic element can comprise non-volatile flash memory, and the first microelectronic element can comprise graphic process unit.
In a particular embodiment, a kind of system can comprise multiple above-mentioned microelectronics Packaging, circuit board and processor.The terminal of microelectronics Packaging is electrically connected with the plate contact of circuit board.Each microelectronics Packaging is used in the clock cycle and transmits N number of parallel data bit, and processor is used in the clock cycle and transmits M parallel data bit, and M is more than or equal to N.In a particular example, a kind of system can comprise an above-mentioned microelectronics Packaging, and is electrically connected to other electronic units one or more of this microelectronics Packaging.In one embodiment, system also can comprise housing, and above-mentioned microelectronics Packaging and other electronic units are mounted to this housing.
According to a further aspect in the invention, a kind of module can comprise the module card with first surface and second surface, and the first microelectronic element and the second microelectronic element have the front surface of the first surface in the face of module card.Module card can have the edge contact of multiple parallel exposure, and this edge contact is close to the edge of at least one in first surface and second surface, for when module inserts socket, and the contact docking corresponding to socket.Module card can have multiple card contacts on the first surface.Each microelectronic element can have the multiple element contacts at its front surface place.The element contacts of each microelectronic element can be connected with corresponding card contact.The front surface of the second microelectronic element partly can cover and be attached to the rear surface of the first microelectronic element.The element contacts of the first microelectronic element can be arranged in the battle array of face and with first group of card contact flip-chip bonding.The element contacts of the second microelectronic element is connected by conducting block and second group of card contact.
In one exemplary embodiment, the element contacts of the second microelectronic element can protrude from outside the lateral edges of the first microelectronic element.In one example, edge contact can be exposed at least one place in the first surface of module card or second surface.In a particular embodiment, at least one the comprised memory component in the first microelectronic element and the second microelectronic element.In one embodiment, module can comprise the multiple lead-in wires extending to edge contact from least some card contact.This lead-in wire can be used for carrying address signal with at least one in the first microelectronic element and the second microelectronic element to memory component addressing.In a particular example, the signal of at least some edge contact between to can be used for carrying in each edge contact and the first microelectronic element and the second microelectronic element each or at least one in reference potential.
In a particular example, module also can comprise multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to module card.In one example, multiple 3rd microelectronic element can be arranged to stacked structure, and each 3rd microelectronic element has the facing front surface of the front surface of three microelectronic element adjacent with or rear surface or rear surface.In a particular embodiment, multiple 3rd microelectronic element can be arranged to planar structure, and each 3rd microelectronic element has the facing peripheral surface of the peripheral surface of three microelectronic element adjacent with.
In one embodiment, second microelectronic element can comprise volatibility RAM, each 3rd microelectronic element can comprise non-volatile flash memory, and the first microelectronic element can comprise the processor being mainly used in controlling external module and the data between the second microelectronic element and the 3rd microelectronic element and transmitting.In a particular example, the second microelectronic element can comprise volatibility frame buffer memory element, and each 3rd microelectronic element can comprise non-volatile flash memory, and the first microelectronic element can comprise graphic process unit.
In one exemplary embodiment, a kind of system can comprise multiple above-mentioned module, circuit board and processor.The contact of the exposure of module be inserted into be electrically connected with circuit board to plug receptacle.Each module is used within the clock cycle, transmit N number of parallel data bit, and processor is used within the clock cycle, transmit M parallel data bit, and M is more than or equal to N.In one example, a kind of system can comprise above-mentioned module, and is electrically connected to other electronic units one or more of this module.In a particular embodiment, system also can comprise housing, and above-mentioned module and other electronic units are mounted to this housing.
Accompanying drawing explanation
Figure 1A is the schematic cross sectional views of the stacking micromodule according to the embodiment of the present invention;
Figure 1B be the stack assemblies of Figure 1A along the line 1B-1B in Figure 1A face upward cutaway view;
Fig. 1 C is the sectional view of the stack assemblies of Figure 1B along the line 1C-1C in Figure 1B;
Fig. 2 is the schematic cross sectional views with the stacking micromodule of the microelectronic element of flip-chip bonding according to another embodiment;
Fig. 3 is the schematic cross sectional views with the stacking micromodule of supine microelectronic element according to another embodiment;
Fig. 4 has according to another embodiment single opening in module card to extend through the stacking micromodule being attached to two microelectronic elements schematic cross sectional views for line bonding.
Fig. 5 is the schematic cross sectional views with the stacking micromodule of wire bonding according to another embodiment;
Fig. 6 is the schematic cross sectional views with the stacking micromodule of the solder contacts of lengthening according to another embodiment;
Fig. 7 A is the schematic cross sectional views with the stacking micromodule of the microelectronic element with the contact being positioned at its adjacent edges according to another embodiment;
Fig. 7 B be the stacked package of Fig. 7 A along the line 7B-7B in Fig. 7 A face upward cutaway view;
Fig. 7 C is the partial view of the optional layout of the contact illustrated for the part in Fig. 7 B;
Fig. 8 is the modification of facing upward cutaway view of the stack assemblies of Figure 1B, and one of them microelectronic element has the multirow central contact that direction is the multirow central contact being approximately perpendicular to another microelectronic element;
Fig. 9 A is the schematic cross sectional views with the stacking micromodule of lead frame according to another embodiment;
Fig. 9 B be the stack assemblies of Fig. 9 A along the line 9B-9B in Fig. 9 A face upward cutaway view;
Fig. 9 C is the sectional view of the stack assemblies of Fig. 9 B along the line 9C-9C in Fig. 9 B;
Figure 10 A is the schematic plan with the stacking micromodule of multiple stacking microelectronic element (not shown sealant) according to another embodiment;
Figure 10 B is the sectional view of the stack assemblies of Figure 10 A along the line 10B-10B in Figure 10 A;
Figure 10 C is the schematic plan with the stacking micromodule of multiple mutually adjacent microelectronic element according to another embodiment;
Figure 11 is the schematic perspective view comprising the stacking micromodule of the module card of two mutual bondings according to another embodiment;
Figure 12 is the schematic diagram comprising the system of multiple module according to an embodiment;
Figure 13 A is the schematic cross sectional views of the stacked microelectronic packages according to another embodiment;
Figure 13 B be along the line 13A-13A in Figure 13 A Figure 13 A shown in stacked package face upward cutaway view;
Figure 14 A to Figure 14 E is the partial sectional view of the modification of a part for the stacked microelectronic packages of Figure 13 A shown by dash area 14 in Figure 13 A;
Figure 15 is the schematic cross sectional views with the stacked microelectronic packages of the solder contacts of prolongation according to another embodiment;
Figure 16 is the schematic diagram of a kind of system according to an embodiment of the invention.
Embodiment
Referring to figs. 1A to Fig. 1 C, module 10 can comprise the first microelectronic element 20, second microelectronic element 30 and have the module card 40 of edge contact 50 of exposure according to an embodiment of the invention.First sealant 60 can cover microelectronic element 20 and 30, and a part for module card 40.
In certain embodiments, at least one in the first microelectronic element 20 and the second microelectronic element 30 can be semiconductor chip, wafer or similar.Such as, one or two the comprised memory component in the first microelectronic element 20 and the second microelectronic element 30, as DRAM.Just as used in this, " memory component " refers to that multiple memory cell is arranged to array, is used from stores and therefrom retrieve data, such as, for passing through the transmission data of electrical interface with circuit one.In a particular example, module 10 can be included in single row direct insert memory modules (SIMM) or DIMM (dual in-line memory module) (DIMM).
First microelectronic element 20 can have front surface 21, away from the rear surface 22 of front surface 21, and the lateral edges 23 extended between the front and back surfaces.Electric contact 24 is exposed to front surface 21 place of the first microelectronic element 20.As described herein, the electric contact 24 of the first microelectronic element 20 also can refer to " chip contacts ".As used in the present invention, the state representation conducting element that conducting element " is exposed to " surface of structure can be used for at the theoretical punctiform contact perpendicular to the surface movement from structural outer towards structure in the surface direction of structure.Therefore, the terminal or other conducting elements that are exposed to the surface of structure can be given prominence to from such surface; Can be concordant with such surface; Or can be recessed into relative to such surface and be exposed by the hole in structure or recess.The contact 24 of the first microelectronic element 20 is exposed to front surface 21 place in the central area 25 of the first microelectronic element.Such as, contact 24 can be arranged to a line at the center of contiguous front surface 21 or two parallel row.
Second microelectronic element 30 can have front surface 31, away from the rear surface 32 of front surface 31, and the lateral edges 33 extended between the front and back surfaces.Electric contact 34 is exposed to front surface 31 place of the first microelectronic element 30.As described herein, the electric contact 34 of the second microelectronic element 30 also can refer to " chip contacts ".The contact 34 of the second microelectronic element 30 is exposed to front surface 31 place in the central area 35 of the second microelectronic element.Such as, contact 34 can be arranged to a line at the center of contiguous front surface 31 or two parallel row.
As figs. ia and 1 c show, the first microelectronic element 20 and the second microelectronic element 30 mutually stacking.In certain embodiments, the rear surface 22 of the front surface 31 of the second microelectronic element 30 and the first microelectronic element 20 mutually faced by.The rear surface 22 that can cover the first microelectronic element 20 at least partially of the front surface 31 of the second microelectronic element 30 at least partially.The lateral edges 23 that can protrude past the first microelectronic element 20 at least partially of the central area 35 of the second microelectronic element 30.Correspondingly, the contact 34 of the second microelectronic element 30 can be placed on the position of the lateral edges 23 protruding past the first microelectronic element 20.
Micromodule 10 can comprise the module card 40 of the first surface 41 faced by having relatively and second surface 42 further.One or more conductive contact 44 can be exposed to second surface 42 place of module card 40.Module card 40 can comprise one or more hole further, such as the first hole 45 and the second hole 46.As shown in Figure 1A and Fig. 1 C, the first microelectronic element 20 and the respective front surface 21 and 31 of the second microelectronic element 30 can in the face of the first surfaces 41 of module card 40.
Module card 40 can be partly or wholly made up of any suitable dielectric material.Such as, module card 40 can comprise the board-like material of relative stiffness, the thick-layer of such as fiber reinforced epoxy resin, such as, and Fr-4 plate or Fr-5 plate.No matter use which kind of material, dielectric material that is that module card 40 can comprise individual layer or multilayer.In a particular embodiment, module card 40 can be made up of the material had lower than the thermal coefficient of expansion of 30/1000000ths every degree Celsius (" 30ppm/ DEG C ") substantially.
As shown in Figure 1, module card 40 can extend over the lateral edges 23 of the first microelectronic element 20 and the lateral edges 33 of the second microelectronic element 30.The first surface 41 of module card 40 can be arranged side by side with the front surface 21 of the first microelectronic element 20.
In the embodiment that Figure 1A to Fig. 1 C describes, module card 40 comprises first hole 45 of substantially aliging with the central area 25 of the first microelectronic element 20 and second hole 46 of substantially aliging with the central area 35 of the second microelectronic element 30, contacts contact 24 and 34 thus respectively by the first hole with the second hole.First hole 45 and the second hole 46 can extend between the first surface 41 of module card 40 and second surface 42.As shown in Figure 1B, can align with the respective chip contact 24 or 34 of each first microelectronic element 20 and the second microelectronic element 30 in hole 45 and 46.
Module card 40 also can comprise the conductive contact 44 being exposed to its second surface 42 place and the conductive trace 55 extended between contact 44 and the edge contact 50 exposed.The edge contact 50 that contact 44 electrical coupling extremely exposes by conductive trace 55.In a particular embodiment, contact 44 can be the end of each trace 55.
In a particular embodiment, module card 40 can have the edge contact 50 of multiple parallel exposure, at least one interpolation edge 43 in the contiguous first surface 41 in these contacts 50 and second surface 42, during for inserting socket (shown in Figure 12) when module 10, the contact corresponding to this socket is docked.As shown in Figure 1B, can internally position by insert edge edge 43, make in hole 45 and 46 each have and deviating from the length L that the direction at the interpolation edge 43 of module card 40 extends.Some or all of edge contact 50 can be exposed to one or two place in the first surface 41 of module card 40 or second surface 42.
The edge contact 50 exposed and interpolation edge 43 can be designed size with the corresponding socket (Figure 12) of other connectors of insertion system, such as, can be arranged on mainboard.The edge contact 50 of this exposure can be adapted at docking to multiple corresponding spring contact (Figure 12) in this jack connetor.This spring contact can be arranged on each groove monolateral or polygon on, to dock with the edge contact 50 of corresponding exposure.In one example, the signal of at least some edge contact 50 between to can be used for carrying in each edge contact and the first microelectronic element 20 and the second microelectronic element 30 each or at least one in reference potential.
As shown in Figure 1A to Fig. 1 C, the contact 34 of the contact 24 of the first microelectronic element 20 and the second microelectronic element 30 can be connected to the edge contact 50 of exposure by electrical connection or lead-in wire 70.Lead-in wire 70 can comprise line bonding 71 and 72, and conductive trace 55.In one embodiment, lead-in wire 70 can be considered for microelectronic element 20 and 30 is all electrically connected to module card 40.In particular example, lead-in wire 70 can be used for carrying address signal with at least one in the first microelectronic element 20 and the second microelectronic element 30 to memory component addressing.
As used herein, " lead-in wire " is part or all of the electrical connection extended between two conducting elements, such as, go between 70 to comprise line bonding 71 and conductive trace 55.This conductive trace 55 extends through the edge contact 50 that 45 to one, the first hole exposes from a contact 24 of the first microelectronic element 20.
In one example, module 10 can comprise multiple in hole 45 and 46 from the first microelectronics 20 and the second microelectronic element 30 chip contacts 24 and 34 of at least one extend to the lead-in wire 70 of the edge contact 50 of exposure.In particular example, lead-in wire 70 can be included in the conductive trace 55 in module card 40 and extend to the line bonding 71,72 of the chip contacts 24 and 34 of at least one the first microelectronics 20 and the second microelectronic element 30 from conductive trace.
Shown in Figure 1B, the conductive trace 55 of lead-in wire 70 can extend along the second surface 42 of module card 40.In particular example, the conductive trace 55 of lead-in wire 70 can extend along the first surface 41 of module card 40, or the conductive trace of lead-in wire can extend along the first surface 41 of module card and second surface 42.The part of conductive trace 55 can extend to the edge contact 50 of exposure on the direction of length L being roughly parallel to hole 45 and 46 from each contact 24 and 34 along the surface 41 or 42 of module card 40.In a particular embodiment, conductive trace 55 can be arranged along the mode on the surface 41 or 42 of module card 40, and the length of lead-in wire 70 between each contact 24 and 34 and the edge contact 50 exposed can be minimized.
Each in line bonding 71 and 72 can extend across each the first hole 45 or the second hole 46, and can by each contact 24 or 34 electrical coupling to the corresponding contacts 44 of module card 40.The forming process of line bonding 71 and 72 can comprise passing hole 45,46 and insert, bonding tool conductive contact 24,34 to be electrically connected to the corresponding conductive contact 44 of module card 40.
In a particular embodiment, each in line bonding 71 and 72 can be the multi-thread bonding comprising line bonding mutually almost parallel in multiple directions.This multi-thread bonding structure comprising multiple line bonding 71,72 may be provided in the parallel electrically conductive path between contact 24 or 34 and the corresponding contacts 44 of module card 40.
Distance piece 12 can between a part for the first surface 41 of the front surface 31 of the second microelectronic element 30 and module card 40.This distance piece 12 can be made up of such as dielectric material (such as silicon diode), semi-conducting material (such as silicon) or one or more layers adhesive.If distance piece 12 comprises adhesive, the second microelectronic element 30 can be connected to module card 40 by adhesive.In one embodiment, distance piece 12 can have on the vertical direction V of first surface 41 being basically perpendicular to module card 40 with the first microelectronic element 20 between front surface 21 and rear surface 22 the substantially equal thickness T1 of thickness T2.
In a particular embodiment, distance piece 12 can be replaced by the buffer chip had in the face of the first surface 41 of module card 40.In one example, this buffer chip can be bonded to the contact at first surface 41 place being exposed to module card 40 by flip-chip.This buffer chip can be used for helping to provide each impedance about the external component of module 10 in microelectronic element 20,30 to isolate.
One or more adhesive phase 14 can between the first microelectronic element 20 and module card 40, between the first microelectronic element 20 and the second microelectronic element 30, between the second microelectronic element 30 and distance piece 12, and between distance piece 12 and module card 40.This adhesive phase 14 can comprise the adhesive for the mutual bonding of above-mentioned parts by module 10.In a particular embodiment, one or more adhesive phase 14 can extend between the first surface 41 of module card 40 and the first surface 21 of the first microelectronic element 20.In one embodiment, one or more adhesive phase 14 can by the rear surface 22 being attached to the first microelectronic element 20 at least partially of the front surface 31 of the second microelectronic element 30 at least partially.
In one example, each adhesive phase 14 can be partly or wholly made up of wafer adhesive, and can be made up of low modulus of elasticity materials (such as silicone elastomer).In one embodiment, wafer adhesive can be compatibility.In another example, if two microelectronic elements 20 and 30 are the conventional semiconductor chips formed by same material, each adhesive phase 14 can be partly or wholly made up of skim high elastic modulus adhesive or solder, this is because, in response to variations in temperature, microelectronic element will be expanded or shrink with reaching unanimity.No matter use which kind of material, each adhesive phase 14 can comprise single layer or multiple layer wherein.In the specific embodiment that distance piece 12 is made up of adhesive, the adhesive phase 14 between distance piece 12, second microelectronic element 30 and module card 40 can be omitted.
Module 10 also can comprise the first sealant 60 and the second sealant 65.First sealant 60 can cover, such as, and the respective rear surface 22 and 32 of the first microelectronic element 20 and the second microelectronic element 30, and the part of the first surface 41 of module card 40.In a particular embodiment, the first sealant 60 can be rubber-coating module (overmold).One or more sealant 65 can cover the front surface 21 and 31 be exposed within respective hole 45 and 46 of the first microelectronic element 20 and the second microelectronic element 30, the part of the second surface 42 of module card 40, contact 24,34 and 44, and extend in the line bonding 71 and 72 between each contact 24,34 and corresponding contact 44.In a particular embodiment, the second sealant 65 can cover the part of the lead-in wire 70 extended between chip contacts 24,34 and module card 40.
A kind of according in the technique of specific embodiment, the first sealant 60 may be injected on the respective rear surface 22 and 32 of the first microelectronic element 20 and the second microelectronic element 30, and on the first surface 41 of module card 40.In a kind of technique according to an example, the second sealant 65 injectable enters in the first hole 45 and the second hole 46, and the part of lead-in wire 70 between chip contacts 24,34 and module card 40 is covered by the second sealant.
Fig. 2 is the modification about the embodiment described in Figure 1A to Fig. 1 C.In this modification, module 210 is identical with above-mentioned module 10, and except the first microelectronic element 220 flip-chip is bonded on the first surface 241 of module card 240, instead of line is bonded to the second surface of module card.
Conductive contact 224 is exposed to front surface 221 place of the first microelectronic element 220.Conductive contact or chip contacts 224 are electrically connected to the conductive contact 247 at first surface 241 place being exposed to module card 240 by such as conducting block 273.Conducting block 273 can comprise the fusible metal had compared with low melting glass, such as, and solder, tin or comprise the eutectic mixture of various metals.Alternatively, conducting block 273 can comprise wettable metal, such as, copper or other there is noble metal higher than the melt temperature of solder or other fusible metals or base metal.In a particular embodiment, conducting block 273 can comprise distribution electric conducting material in media as well, such as, and conducting resinl, metal filled glue, fill solder glue, isotropic conducting resinl or anisotropic conducting resinl.
Conductive trace (not shown in Figure 2) can extend to the edge contact of the exposure at the interpolation edge (the interpolation edge 43 such as shown in Figure 1B and Fig. 1 C) in module card along the first surface 241 of module card 240 from conductive contact 247.As in above-mentioned module 10, the chip contacts 234 of the second microelectronic element 230 is electrically connected to the corresponding conductive contact 244 of module card 240 by the line bonding 272 in the hole 246 extending through module card.Conductive trace also can extend to the edge contact of the exposure at the interpolation edge (the interpolation edge 43 such as shown in Figure 1B and Fig. 1 C) in module card along the second surface 242 of module card 240 from conductive contact 244.
Fig. 3 is the another kind of modification about the embodiment described in Figure 1A to Fig. 1 C.In this modification, module 310 is identical with above-mentioned module 10, except the first microelectronic element 320 is placed to the first surface 341 of its rear surface 322 in the face of module card 340, and its front surface 321 at least partly in the face of and partly cover at least part of of the front surface 331 of the second microelectronic element 330.The rear surface 322 of the first microelectronic element 320 is attached to the first surface 341 of module card 340 by one or more adhesive phase (adhesive phase 14 such as shown in Figure 1A and Fig. 1 C).Conductive contact 324a and 324b (being jointly conductive contact 324) can be exposed to front surface 321 place of the first microelectronic element 320.The chip contacts 324 of the first microelectronic element 320 can comprise any structure of conductive contact 324a and/or 324b.
The conductive contact 324a of the first microelectronic element 320 can be exposed to first surface 321 place in the central area 325 of the first microelectronic element.Such as, contact 324a can be arranged to a line at the center of contiguous front surface 321 or two parallel row.Conductive contact 324a is electrically connected to the conductive contact 347 at first surface 341 place being exposed to module card 340 by such as line bonding 371a.
The conductive contact 324b of the first microelectronic element 320 can be exposed to front surface 321 place near the lateral edges 323 of the first microelectronic element.Such as, contact 324b can be arranged to a line of the lateral edges 323 of contiguous first microelectronic element 320 or two parallel row.Conductive contact 324b (can pass through, such as line bonding 371b) conductive contact 347 being electrically connected to first surface 341 place being exposed to module card 340.
Similar with Fig. 2, conductive trace (not shown in Figure 3) can extend to the edge contact of the exposure of the interpolation edge (the interpolation edge 43 such as shown in Figure 1B and Fig. 1 C) in module card respectively along the first surface 341 of module card 340 and second surface 342 from conductive contact 347 and 344.
Although the embodiment shown in Fig. 3 illustrates that the second microelectronic element 330 is electrically connected to module card 340 by line bonding 372, but in other embodiments, second microelectronic element is electrically connected to module card by other modes various, comprise such as, wire bonding (as shown in Figure 5) or utilize the flip-chip bonding (as shown in Figure 6 and Figure 7) of solder.
Fig. 4 is the another kind of modification of the embodiment according to Figure 1A to Fig. 1 C.In this modification, module 410 is identical with above-mentioned module 10, except the first microelectronic element 410 and the second microelectronic element 420 are electrically connected to module card 440 by extend through each line bonding 471 and 472 in the common hole 446 extended between the first surface 441 and second surface 442 of module card, instead of each microelectronic element is allowed to be electrically connected to module card by extend through the line bonding in each hole separated of module card.
As shown in Figure 4, the conductive contact 424 of the first microelectronic element 420 can be exposed to front surface 421 place near the lateral edges 423 of the first microelectronic element.Such as, contact 424 can be arranged to the row of the lateral edges 423 of contiguous first microelectronic element 420.Conductive contact 424 is electrically connected to the conductive contact 444 of the second surface 442 being exposed to module card 440 by such as line bonding 471.
The conductive contact 434 of the second microelectronic element 430 can be exposed to front surface 431 place in the central area 435 of the second microelectronic element.Such as, contact 434 can be arranged to the row at the center close to front surface 431.Conductive contact 434 is electrically connected to the conductive contact 444 of the second surface 442 being exposed to module card 440 by such as line bonding 472.
In the embodiment shown in fig. 4, module 410 can comprise single second sealant 465.Such as, second sealant 465 can cover, be exposed to the part of the respective front surface 421 and 431 of microelectronic element 420 and 430 within single cordonnier 446, the part of the second surface 442 of module card 440, contact 424,434 and 444, and the line bonding 471 and 472 extended between each contact 424,434 and corresponding contact 444.
Fig. 5 is the another kind of modification of the embodiment according to Figure 1A to Fig. 1 C.In this modification, module 510 is identical with above-mentioned module 10, except the first microelectronic element 520 flip-chip is bonded to the first surface 541 (mode with shown in Fig. 2) of module card 540, and the second microelectronic element 530 is by extending to wire bonding 574a and 574b (being jointly wire bonding 574) of chip contacts 534 instead of being electrically connected to module card 540 by line bonding from conductive trace.
As shown in Figure 5, conductive contact 534a and 534b (being jointly conductive contact 534) of the second microelectronic element 530 can be exposed to front surface 531 place in the central area 535 of the second microelectronic element.Such as, contact 534 can be arranged to a line at the center of contiguous front surface 531 or two parallel row.Some conductive contacts 534a is electrically connected to the conductive contact 544 of the second surface 542 being exposed to module card 540 by such as wire bonding 574a.Other conductive contact 534b is electrically connected to the conductive contact 547 of the first surface 541 being exposed to module card 540 by such as wire bonding 574b.As shown in Figure 5, conductive contact 544 and 547 can be the conductive contact portions of each wire bonding 574a and wire bonding 574b.
The technique forming wire bonding 574 can roughly as the common United States Patent (USP) 5,915,752 and 5,489 transferred the possession of, and describe in 749, its disclosure is incorporated to herein by reference.In wire bonding process, each lead-in wire 570 is engaged with corresponding conductive contact 534 by displacement downwards by instrument (as Heat Ultrasonic Bonding instrument).This bonding tool inserts by hole 546, so that lead-in wire 570 is electrically connected to corresponding conductive contact 534.The fragile part of lead-in wire 570 may rupture in the process.
Fig. 6 is the another kind of modification about the embodiment described in Figure 1A to Fig. 1 C.In this modification, module 610 is identical with above-mentioned module 10, except the first microelectronic element 620 flip-chip is bonded to the first surface 641 (mode with shown in Fig. 2) of module card 640, and the second microelectronic element 630 by the second microelectronic element conductive contact 634 and be exposed to the conducting block 675 extended between the conductive contact 647 at the first surface place of module card, instead of be bonded to the first surface of module card by line bonding flip-chip.In a particular embodiment, module card 640 may not extend through the lead-in wire in the hole (hole 45 and 46 as shown in Figure 1A) between its first surface 641 and second surface 642.
Similar with above-mentioned module 10, the conductive contact 634 of the second microelectronic element 630 can be exposed to front surface 631 place in the central area 635 of the second microelectronic element.Such as, contact 634 can be arranged to a line at the center of contiguous front surface 631 or two parallel row.
Conducting block 675 can be, and such as, elongated solder connects, soldered ball or any other material above-mentioned with reference to conducting block 273.This conducting block 675 can extend across the space between distance piece 612 and the lateral edges 623 of the first microelectronic element 620, to be electrically connected with module card 640 by the second microelectronic element 630.
Fig. 7 A and Fig. 7 B is the another kind of modification about the embodiment described in Fig. 6.In this modification, module 710 is identical with above-mentioned module 610, except the second microelectronic element 730 by the lateral edges 733 at contiguous second microelectronic element conductive contact 734 and be exposed to the first surface 741 that conducting block 775 flip-chip extended between the conductive contact 747 at the first surface place of module card is bonded to module card 740, instead of allow between the conductive contact at the front surface place of second microelectronic element of conducting block in the central area being exposed to the second microelectronic element and extend.
First microelectronic element 720 can have multiple element contacts 724 at first surface 721 place at the first microelectronic element.Element contacts 724 can connect with first group of substrate contact 747a, makes element contacts and substrate contact flip-chip bonding.As shown in Figure 7 B, each in element contacts 724 and first group of substrate contact 747a is arranged to face battle array structure.
In particular example, the contact 734 at front surface 731 place of the second microelectronic element 730 can be arranged to the row of the lateral edges 733 of contiguous second microelectronic element, makes contact 734 can protrude past the lateral edges 723 of the first microelectronic element 720.Element contacts 734 can connect with second group of substrate contact 747b, makes element contacts and substrate contact flip-chip bonding.
Although contact 724,734 and 747 is arranged to illustrated contact parallel columns, present invention contemplates that other arrangements of contact.Such as, although Fig. 7 B does not show, at least one contact can be arranged between adjacent rows of contacts.In another example (such as shown in Fig. 7 C), contact can comprise a row contact, and wherein row axle 719 extends through the major part in this row contact 724, and the major part namely in this row contact 724 is placed in the middle relative to row axle 719.But in this row, one or more contact 724 may be placed in the middle relative to row axle 719, the such as this situation in contact 724 '.In the case, although this (or these) contact may be not placed in the middle relative to row axle 719 because from particular column axle 719 than its from other axles arranged more close to, so these one or more contacts 724 ' can regard the part of particular column as.Row axle 719 can extend across above-mentioned one or more contacts not placed in the middle relative to row axle, or in some cases, contact not placed in the middle may be farther from row axle, makes row axle 719 even may not pass these contacts not placed in the middle of these row.At row or even may have one in multiple row, several or a lot of contact is not placed in the middle relative to the axle of row separately.
In addition, microelectronic element 720,730 and substrate 740 probably comprise in groups but not contact 724,734,747 in column, the layout of the ring-type of such as contact, polygon-shaped or even distributing distribution.
In one embodiment, similar with above-mentioned module 610, module card 740 can not extend through the lead-in wire in the hole between its first surface 741 and second surface 742.
Fig. 8 is the another kind of modification about the embodiment described in Figure 1B.In this modification, module 810 is identical with above-mentioned module 10, and the more lines of conductive contact 824 except the first microelectronic element 820 can be essentially perpendicular to the more lines of conductive contact 834 of the second microelectronic element 830.In this embodiment, the second hole 846 (being similar to the second hole 46 shown in Figure 1B) can have and deviating from the length L that the direction at the interpolation edge 843 of module card 840 extends.First hole 845 can have at the interpolation edge 843 being in substantially parallel relationship to module card 840 and be generally perpendicular to the length L ' that the direction of the length L in the second hole 846 extends.
Lead-in wire 870 can comprise the pattern of the conductive trace 855a identical with the pattern of the conductive trace 55 shown in Figure 1B.Lead-in wire 870 can comprise the optional pattern of the conductive trace 855a extending to the edge contact 850 of exposure from the conductive contact 844b of the second surface 842 being exposed to module card 840 further.In a particular embodiment, some in conductive trace 855b can extend around the lateral edges 848 in the first hole 845.
Fig. 9 is a kind of modification about the embodiment described in Figure 1A to Fig. 1 C.In this modification, module 910 is identical with above-mentioned module 10, except the first microelectronic element 920 and the second microelectronic element 930 are arranged on lead frame 980, instead of is arranged on (module card 40 such as shown in Figure 1A) in module card.In a particular embodiment, the first microelectronic element 920 and the respective front surface 921 and 931 of the second microelectronic element 930 can in the face of the first surfaces 981 of lead frame 980, and each microelectronic element is electrically connected to lead frame.
U.S. Patent No. 7,176,506 and No.6,765,287 illustrate and describe the example of lead frame structure, and its disclosure is incorporated to herein by reference.Usually, lead frame (such as lead frame 980) is a kind of structure formed by conducting metal (as copper) layer, and is patterned to the fragment comprising multiple lead-in wire or conductive trace part 985.In the exemplary embodiment, at least one the be directly installed on lead-in wire in the first microelectronic element 920 and the second microelectronic element 930, this lead-in wire can at the downward-extension of microelectronic element.In this embodiment, the contact 924,934 on microelectronic element is by soldered ball or similar be electrically connected to each lead-in wire.Then lead-in wire can be used for being formed and the electrical connection of other conductive structures multiple, to arrive or from the electronic signal current potential of the first microelectronic element 920 and the second microelectronic element 930 for carrying.(comprise when construction package is complete and form sealant 960 thereon), interim element, such as framework (not shown), can remove from the lead-in wire of lead frame 980, to form independent lead-in wire or conductive trace part 985.
First microelectronic element 920 is attached to lead frame 980 by the one or more adhesive phases 914 extended between the front surface 921 and the first surface 981 of lead frame of the first microelectronic element.This adhesive phase 914 can be similar to the above adhesive phase 14 described referring to figs. 1A to Fig. 1 C.Distance piece 912 can be attached to lead frame 980, and one or more adhesive phase 914 extends between the front surface 913 and the first surface 981 of lead frame of distance piece.The front surface 931 of the second microelectronic element 930 partly can cover the rear surface 922 of the first microelectronic element 920 and the rear surface 915 of distance piece 912 at least partly.The front surface 931 of the second microelectronic element 930 is attached to the rear surface 922 of the first microelectronic element 920 and the rear surface 915 of distance piece 912 by one or more adhesive phase 914.
As shown in Fig. 9 A to 9C, the contact 934 of the contact 924 of the first microelectronic element 920 and the second microelectronic element 930 can be connected to the module contact 950 of exposure by electrical connection or lead-in wire 970.Lead-in wire 970 can comprise line bonding 971 and 972, and the conductive trace part 985 of lead frame 980.In particular example, lead-in wire 970 can be used for carrying address signal with at least one in the first microelectronic element 920 and the second microelectronic element 930 to memory component addressing.
In one example, lead frame 980 can be limited to the first gap 945 and the second gap 946 extended between the first surface 981 of lead frame and the second surface 982 relative to first surface 981.Can align with the chip contacts 924 of the first microelectronic element 920 in first gap 945, make line bonding 971 can extend through the first gap between chip contacts 924 and the second surface 982 of lead frame.Can align with the chip contacts 934 of the second microelectronic element 930 in second gap 946, make line bonding 972 can extend through the second gap between chip contacts 934 and the second surface 982 of lead frame.
Module 910 also can comprise the sealant 960 of covering first microelectronic element 920, second microelectronic element 930 and part lead frame 980, makes the module contact 950 exposed can be exposed to lower surface 962 place of the interpolation portion 961 of sealant.Sealant 960 also can cover contact 924,934, and the line bonding 971,972 extended between each contact 924,934 and lead frame 980.When module 910 inserts socket, the interpolation portion 961 of sealant 960 can have the suitable size and dimension docked with corresponding socket (shown in Figure 12).
In a particular embodiment, module 910 can have the module contact 950 of contiguous first surface 981 and the multiple parallel exposure at the interpolation edge 983 of at least one in second surface 982, for when module 910 inserts socket, dock with the corresponding contact of socket (shown in Figure 12).On one or two in the first surface 981 of some or all the be exposed to lead frames 980 in module contact 950 and second surface 982.
Figure 10 A and Figure 10 B is a kind of modification about the embodiment described in Fig. 2.In this modification, module 1010 is identical with above-mentioned module 210, is arranged on folded 3rd microelectronic element 1090 of one in module card 1040 except module 1010 also comprises.
Similar with Fig. 2, the first microelectronic element 1020 flip-chip is bonded to the first surface 1041 of module card 1040.The conductive contact of the first microelectronic element 1020 or chip contacts 1024 are electrically connected to the conductive contact 1047 at first surface 1041 place being exposed to module card 1040 by such as conducting block 1073.The chip contacts 1034 of the second microelectronic element 1030 is electrically connected to the corresponding conductive contact 1044 of module card 1040 by the line bonding 1072 in the hole 1046 extending through module card.Conductive trace (not shown in Figure 10 A and Figure 10 B) can extend to the edge contact 1050 at the interpolation edge (such as edge 1043 or edge 1043a) being exposed to module card along the first surface 1041 of module card 1040 and/or second surface 1042 from conductive contact 1044 and 1047.As shown in Figure 10 B, edge contact 1050 can be exposed to first surface 1041 place, or second surface 1042 place, or first surface and second surface place.
This folded 3rd microelectronic element 1090 can be arbitrary number, comprises, such as the 3rd microelectronic element 1090a and 1090b of two shown in Figure 10 B.3rd microelectronic element 1090 is interconnected by interconnection structure, and/or is connected with edge contact 1050.Such as, lower 3rd microelectronic element 1090a is connected with the contact of the surface being exposed to module card 1040 by flip-chip bonding, line bonding, wire bonding or other interconnection structures.One or more upper 3rd microelectronic element 1090b is connected with the contact of module card 1040 by extending through down the conductive through hole of the 3rd microelectronic element 1090a, line bonding, wire bonding or other interconnection structures.
In the exemplary embodiment, module 1010 can be configured to and drives as solid-state storage.In such examples, first microelectronic element 1020 can comprise the semiconductor chip being mainly used in actuating logic function, such as solid-state driving governor, and the second microelectronic element 1030 can comprise memory storage element, such as volatibility RAM (as DRAM).3rd microelectronic element 1090 can comprise memory storage element, such as non-volatile flash memory.First microelectronic element 1020 can comprise application specific processor, and application specific processor is used for the CPU of deactivation system (system 1200 of such as Figure 12) to the management of the transmission of the data of the memory storage element be included in the second microelectronic element 1030 and the 3rd microelectronic element 1090 of coming in and going out.This first microelectronic element 1020 comprising solid-state driving governor can be provided to and from the direct memory access of the data/address bus on the motherboard (circuit board 1202 such as, shown in Figure 12) of system (such as system 1100).
In another embodiment, module 1010 can be configured to as figure module, such as, can insert the PCI card slot of notebook computer.In such examples, first microelectronic element 1020 can comprise the semiconductor chip being mainly used in actuating logic function, such as graphic process unit, and the second microelectronic element 1030 can comprise memory storage element, such as volatibility RAM (as DRAM), it can be used as the volatibility frame buffer calculating graphic plotting.Each 3rd microelectronic element 1090 can comprise memory storage element (such as non-volatile flash memory).
Figure 10 C is a kind of modification about the embodiment described in Figure 10 A and Figure 10 B.In this modification, module 1010 ' is identical with above-mentioned module 1010, except module 1010 ' comprises mutually adjacent and non-stacking multiple 3rd microelectronic elements 1090 ' be arranged in module card 1040.Similar with module 1010, the 3rd microelectronic element 1090 ' is connected with the contact of the surface being exposed to module card 1040 by any interconnection structure (such as flip-chip bonding, line bonding, wire bonding or other interconnection structures).Module 1010 ' can be used for the exemplary functions identical with module 1010, and such as solid-state memory drives or figure module.
Figure 11 describes the parts 1100 of the first module 1110a and the second module 1110b (module 10 such as described in Figure 1A to Fig. 1 C) comprised according to above-mentioned any embodiment.First module 1110a and the second module 1110b by least one layer 1165 mutually bonding, the second surface 1142 making the modules card 1140 of module mutually faced by.In a particular embodiment, above-mentioned at least one layer 1165 can be single common sealant (the second sealant 65 as shown in Figure 1A and 1B).In another example, above-mentioned at least one layer 1165 can be the one or more adhesive phases be similar to referring to figs. 1A to the adhesive phase 14 described in Fig. 1 C.
Parts 1100 can have a line at interpolation edge 1143 of adjacent components or the edge contact 1150 of the exposure of more parallel rows.Each had a line in first module 1110a and the second module 1110b is exposed to the edge contact 1150 at first surface 1141 place of modules card 1140, make when parts 1100 insert socket, this edge contact can be suitable for docking with the corresponding contact of socket (being similar to the socket shown in Figure 12).
Can be used for building multiple electronic system referring to figs. 1A to the module described in Figure 10 and parts, such as, system 1200 shown in Figure 12.Such as, comprise above-mentioned multiple module or parts 1206 according to the system 1200 of the further embodiment of the present invention, and other electronic units 1208 and 1210.
System 1200 can comprise multiple socket 1205, each socket is included in multiple contacts 1207 of socket one or both sides, makes each socket 1205 can be suitable for docking with the edge contact of corresponding exposure of corresponding module or parts 1206 or the module contact of exposure.In shown example system 1200, system can comprise circuit board or mainboard 1202 (such as flexible printed circuit board), circuit board comprises module or parts 1206 a lot of conductors 1204 interconnected amongst one another, in fig. 12 one of them conductor is only shown.But this is exemplary; Any suitable structure for the manufacture of the electrical connection between module or parts 1206 can be used.
In a particular embodiment, system 1200 also can comprise processor (as semiconductor chip 1208), each module or parts 1206 were used in the clock cycle and transmit N number of parallel data bit, and processor is used in transmission M parallel data bit in the clock cycle, M is more than or equal to N.
In one example, system 1200 can comprise the processor chips 1208 for transmitting 32 parallel data bits within the clock cycle, and this system also can comprise four modules 1206 (such as referring to figs. 1A to the module 10 described in 1C), each module 1206 for transmitting 8 parallel data bits (namely each module 1206 can comprise the first microelectronic element and the second microelectronic element, in two microelectronic elements each for transmission 4 parallel data bits within the clock cycle) within the clock cycle.
In another example, system 1200 can comprise the processor chips 1208 for transmitting 64 parallel data bits within the individual clock cycle, and this system also can comprise four modules 1206 (parts 1000 such as described in reference diagram 12), each module 1206 for transmitting 16 parallel data bits (namely each module 1206 can comprise two group of first microelectronic element and the second microelectronic element, and each in four microelectronic elements for transmitting 4 parallel data bits within the clock cycle) within the clock cycle.
In the example described in Figure 12, parts 1208 are semiconductor chip and parts 1210 are display screens, but any other parts can be used in system 1200.Certainly, although the clearness in order to illustrate, illustrate only two extra parts 1208 and 1210 in fig. 12, system can comprise any amount of this parts.
Module or parts 1206 and parts 1208 and 1210 are arranged in shared housing 1201 (schematically illustrating with dotted line), and where necessary each other electrical interconnection to form the circuit expected.Housing 1201 is shown in the portable housing of type available in such as mobile phone or personal digital assistant, and screen 1210 can be exposed to the surface of housing.Comprise in structure 1206 in the embodiment of photo-sensitive cell (such as imager chip), lens 1211 or other Optical devices can also be set for light is directed to this structure.In addition, the system of the simplification shown in Figure 12 is exemplary; Above-mentioned structure can be used to manufacture other system, comprise the system being usually considered to fixed structure, such as desktop computer, router etc.
Figure 13 A and Figure 13 B is a kind of modification about the embodiment described in Fig. 7 A and Fig. 7 B.In this modification, microelectronics Packaging 1310 is identical with above-mentioned module 710, be mounted to substrate 1340 but not the microelectronic element 1320 and 1330 of module card except microelectronics Packaging 1310 comprises, and microelectronics Packaging 1310 have for parts but not edge contact interconnection terminal 1350.In one embodiment, similar with above-mentioned module 710, substrate 1340 can not extend through the lead-in wire in the hole of substrate.
First microelectronic element 1320 can have the front surface 1321 of the first surface 1341 in the face of substrate 1340.First microelectronic element 1320 can have multiple element contacts 1324 at front surface 1321 place at the first microelectronic element.Element contacts 1324 can connect with first group of substrate contact 1347a, makes element contacts and substrate contact flip-chip bonding.As shown in Figure 13 B, element contacts 1324 and first group of substrate contact 1347a can be arranged to face battle array structure.
Second microelectronic element 1330 can have the front surface 1331 of the first surface 1341 in the face of substrate 1340.The front surface 1331 of the second microelectronic element 1330 partly can cover the rear surface 1322 of the first microelectronic element 1320, and such as can be attached to rear surface 1322 by adhesive phase 1314.
Second microelectronic element 1330 can have the multiple element contacts 1334 at its front surface 1331 place.Element contacts 1334 can connect with second group of substrate contact 1347b, makes element contacts and substrate contact flip-chip bonding.As shown in Figure 13 B, element contacts 1334 and second group of substrate contact 1347b can be arranged to array structure.
Although contact 1324,1334 and 1347 is arranged to the parallel rows of contacts illustrated, as described in above reference diagram 7A-7C, present invention contemplates that other arrangements of contact.
Substrate 1340 can be included in multiple terminals 1350 at second surface 1342 place further, for microelectronics Packaging 1310 being connected to parts of package outside.Conducting block 1351 can be arranged on the surface of the exposure of terminal 1350.This conducting block 1351 can be, such as, and soldered ball or reference conducting block 273 any other material above-mentioned.In one example, external component can be the circuit board (as circuit board 1602) described at hereinafter with reference Figure 16.
Contact 1324 and 1334 is electrically connected to each group of substrate contact 1347a and 1347b by such as each conducting block 1373 and 1375.Conducting block 1373 can be, such as, and soldered ball or any other material above-mentioned with reference to conducting block 273.Conducting block 1375 can be, and such as, elongated solder connects, soldered ball or any other material above-mentioned with reference to conducting block 273.
As shown in Figure 14 A, in the modification of the embodiment of Figure 13 A and Figure 13 B, conducting block 1375 and/or conducting block 1373 can be replaced by conductive connector 1475 at least partly.Conductive connector can comprise deposition (as coating or the plating) part within opening, and the contact 1434 of the second microelectronic element is exposed in opening.Such as, conductive connector 1475 can be formed by plated metal or other electric conducting materials (as conductive substrate material) extending in the corresponding hole 1476 least partially penetrating sealant 1460, and the technique that make use of such as described in U.S. Patent Publication No.2012/0126389, its disclosure is incorporated to herein by reference.
In another modification, as shown in Figure 14B, binding post can comprise multiple giving prominence to away from the element contacts 1434 of the second microelectronic element 1430 towards the frustoconical binding post 1477 of corresponding substrate contact 1447b.Each binding post 1477 consists essentially of the electric conducting material of rigidity substantially, such as, and metal (as copper or aluminium).In one embodiment, binding post 1477 can be formed by a kind of structure of etching (being such as attached to the continuous print of contact or discrete sheet metal).Conducting block 1473 can be arranged between binding post 1477 and substrate contact 1447b to provide electrical connection therebetween.As shown in Figure 14B, binding post 1477 can be taper, each binding post is had be greater than the first width of the neighbouring element contact 1434 of second width of adjacent substrate contact 1447b.
See Figure 14 C, in the modification of the embodiment of Figure 14 B, binding post can comprise multiple giving prominence to away from substrate contact 1447b towards the frustoconical binding post 1478 of the element contacts 1434 of corresponding second microelectronic element 1430.Conducting block 1473 can be arranged between binding post 1478 and element contacts 1434 to provide electrical connection therebetween.As shown in Figure 14 C, binding post 1478 can be taper, each binding post is had be greater than first width of the adjacent substrate contact 1447b of the second width of neighbouring element contact 1434.
See Figure 14 D, in another modification, at least some conducting block 1375 can be replaced by conductive connector 1479a and 1479b, binding post 1479a extends from the element contacts 1434 of the second microelectronic element 1430 towards some corresponding substrate contact 1447b, and binding post 1479b extends from substrate contact towards binding post 1479a.Conducting block 1473 can be arranged between conductive connector 1479a and 1479b to provide electrical connection therebetween.As shown in fig. 14d, terminal 1479a and 1479b can be taper, each binding post is had and is greater than the neighbouring element contact 1434 of the second width of contiguous conducting block 1473 or first width of substrate contact 1447b.
See Figure 14 E, in another modification of the embodiment of Figure 14 B, elongated solder connects 1480 and can be arranged on around the binding post 1477 between substrate contact 1447b and the corresponding element contacts 1434 of the second microelectronic element 1430, to provide the electrical connection between binding post and substrate contact.What the conducting block 1473 shown in any embodiment of Figure 14 B, 14C and 14D can be extended by each binding post 1477,1478 between element contacts 1434 and substrate contact 1447b and 1479 surroundings is connected 1480 replacements by elongated solder.
Figure 15 is a kind of modification about the embodiment described in Fig. 6.In this modification, microelectronics Packaging 1510 is identical with above-mentioned module 610, substrate 1540 is mounted to but not the microelectronic element 1520 and 1530 of module card except microelectronics Packaging 1510 comprises, and microelectronics Packaging 1510 have be exposed to second surface 1542 place for by encapsulation 1510 terminal 1550 with another component connection, instead of embodiment illustrated in fig. 6 in edge contact.In one embodiment, similar with above-mentioned module 610, substrate 1540 can not extend through the lead-in wire in the hole of substrate.
The conductive contact 1534 being similar to above-mentioned module 10, second microelectronic element 1530 can be exposed to front surface 1531 place in the central area 1535 of the second microelectronic element.Such as, contact 1534 can be arranged to into a line at the center of contiguous front surface 1531 or two parallel row.
Conducting block 1575 can be, and such as, elongated solder connects, soldered ball or any other material above-mentioned with reference to conducting block 273.This conducting block 1575 can extend across the space between distance piece 1512 and the lateral edges 1523 of the first microelectronic element 1520, to be electrically connected with substrate 1540 by the second microelectronic element 1530.
Conducting block 1575 shown in Figure 15 can be replaced by the arbitrary optional connection between element contacts 1534 and substrate contact 1547b (as shown in Figure 14 A to 14E).
Extra microelectronic element can be comprised with reference to the arbitrary microelectronics Packaging described in figure 13A to Figure 15, the 3rd microelectronic element 1090a and 1090b (being jointly the 3rd microelectronic element 1090) such as shown in Figure 10 A and 10B, and the 3rd microelectronic element 1090 ' shown in Figure 10 C.
In a particular embodiment, microelectronics Packaging 1310 (or 1510) can comprise, and in the structure being similar to the layout of the microelectronic element shown in Figure 10 B, is arranged on folded 3rd microelectronic element 1090 of one on the first surface 1341 of substrate 1340.In such an embodiment, the 3rd microelectronic element 1090a and 1090b has the surface of first surface 1341 in the face of substrate, this surface and microelectronic element 1320 with 1330 front surface 1321 with 1331 faced by the surface of substrate identical.This substrate 1340 comprising the 3rd microelectronic element 1090 also can have second surface 1342 place for the terminal 1350 with another component connection, instead of the edge contact shown in Figure 10 B.In such an embodiment, the 3rd microelectronic element 1090 of any number can be had during this is stacking, comprise, such as, two the 3rd microelectronic element 1090a and 1090b in the embodiment shown in Figure 10 B.
In one example, microelectronics Packaging 1310 (or 1510) can comprise, being similar in the structure that the microelectronic element shown in Figure 10 C arranges, be arranged on adjacent and non-stacking multiple 3rd microelectronic elements 1090 ' on the first surface 1341 of substrate 1340.In such an embodiment, each 3rd microelectronic element 1090 ' can have the surface of first surface 1341 in the face of substrate, this surface and microelectronic element 1320 with 1330 front surface 1321 with 1331 faced by the surface of substrate identical.This substrate 1340 comprising the 3rd microelectronic element 1090 ' also can have second surface 1342 place for the terminal 1350 with another component connection, instead of the edge contact shown in Figure 10 C.In such an embodiment, the 3rd microelectronic element 1090 ' of any number can be had during this is stacking, comprise, such as, four the 3rd microelectronic elements 1090 ' in the embodiment shown in Figure 10 C.
Can be used to construct multiple electronic system referring to figs. 1A to the module described in Figure 15 and microelectronics Packaging, such as, system 1600 shown in Figure 16.Such as, system 1600 according to a further embodiment of the invention comprises one or more module or parts 1606 (such as above-mentioned microelectronics Packaging 1310) and other electronic units 1608 and 1610.
In shown example system 1600, system can comprise circuit board, mainboard or expansion board 1602 (such as flexible printed circuit board), circuit board comprises module or parts 1606 a lot of conductors 1604 interconnected amongst one another, in figure 16 one of them conductor is only shown.This circuit board 1602 can transmit and to arrive or from the signal of the microelectronics Packaging be included in system 1600 and/or micromodule.But this is exemplary; Any suitable structure for the manufacture of the electrical connection between module or parts 1606 can be used.
In a particular embodiment, system 1600 also can comprise processor (as semiconductor chip 1608), each module or parts 1606 were used in the clock cycle and transmit N number of parallel data bit, and processor is used in transmission M parallel data bit in the clock cycle, M is more than or equal to N.
In the example described in Figure 16, parts 1608 are semiconductor chip and parts 1610 are display screens, but any other parts can be used in system 1600.Certainly, although the clearness in order to illustrate, illustrate only two extra parts 1608 and 1610 in figure 16, system 1600 can comprise any amount of this parts.
Module or parts 1606 and parts 1608 and 1610 can be arranged in shared housing 1601 (schematically illustrating with dotted line), and where necessary each other electrical interconnection to form the circuit expected.Housing 1601 is shown in the portable housing of type available in such as mobile phone or personal digital assistant, and screen 1610 can be exposed to the surface of housing.Comprise in structure 1606 in the embodiment of photo-sensitive cell (such as imager chip), lens 1611 or other Optical devices can also be set for light is directed to this structure.In addition, the system of the simplification shown in Figure 16 is exemplary; Above-mentioned structure can be used to manufacture other system, comprise the system being usually considered to fixed structure, such as desktop computer, router etc.
Potential advantages according to module of the present invention or parts are the (module 10 such as shown in Figure 1A to Fig. 1 C, wherein the rear surface of surface coverage second microelectronic element of the first microelectronic element is at least partially) can be used for providing, by the shorter lead-in wire that the edge contact (edge contact 50 such as exposed) that specifically exposes is electrically connected with a specific electric contact (such as electric contact 24) at the front surface place being exposed to a specific microelectronic element (such as the first microelectronic element 20).Parasitic capacitance between adjacent legs is sizable, especially has in high contact density and closely spaced micromodule.In the micromodule with shorter lead-in wire 70 (as module 10), parasitic capacitance can be reduced, the parasitic capacitance especially between adjacent legs.
Another potential advantages according to module of the present invention or parts are, as mentioned above, it can be used for providing the lead-in wire of similar-length (as gone between 70), such as, be electrically connected by the electric contact 24,34 at the respective front surface place of data input/output signal terminal (edge contact 50 such as exposed) and the first microelectronic element 20 and the second microelectronic element 30.In system (such as comprising the system 1200 of multiple module or parts 1206), there is the lead-in wire 70 of relative similar-length, can allow the propagation delay of the data input/output signal between each microelectronic element and the edge contact of exposure can relatively matched.
Another potential advantages according to module of the present invention or parts are, as mentioned above, it can be used for providing the lead-in wire of similar-length (as gone between 70), then, such as, the electric contact 24,34 at the respective front surface place of sharing clock signal terminal and/or shared data strobe signal terminal (such as, the edge contact 50 of exposure) and the first microelectronic element 20 and the second microelectronic element 30 can be electrically connected.Data strobe signal terminal or clock signal terminal or both can have roughly the same loading to each microelectronic element 20 and microelectronic element 30 and conductive path length, and can be relatively short to the path of each microelectronic element.
In aforesaid arbitrary or all modules or parts, the one or more rear surface in the first microelectronic element or the second microelectronic element can be exposed to the outer surface of micromodule at least in part after completing making.Therefore, referring to figs. 1A in the assembly described in 1C, one or two in the respective rear surface 22 and 32 of the first microelectronic element 20 and the second microelectronic element 30 can partly or completely be exposed in completed module 10.Although rubber-coating module (as the first sealant 60) or other sealing or encapsulating structure can contact or be disposed adjacent to microelectronic element, rear surface 22 and 32 can partly or completely be exposed.
In above-mentioned any embodiment, micromodule can comprise the radiator be made up of metal, graphite or any other suitable Heat Conduction Material.In one embodiment, radiator comprises the metal level that contiguous first microelectronic element is arranged.Metal level can be exposed on the rear surface of the first microelectronic element.Alternatively, radiator can comprise rubber-coating module or the sealant of the rear surface at least covering the first microelectronic element.
Although invention has been described with reference to specific embodiment, it should be understood that these embodiments are only the explanations to principle of the present invention and application.Therefore, it should be understood that when do not depart from by the appended claims the spirit and scope of the present invention, various amendment can be carried out to above-mentioned illustrative embodiment and can design other arrange.
It should be understood that each dependent claims and the feature wherein enumerated can combine with the feature in original claim in a different manner.It will also be appreciated that the feature described in conjunction with each embodiment can be shared with other features of described embodiment.
Industrial applicibility
The present invention has industrial applicibility widely, includes but not limited to the manufacture method of microelectronics Packaging and microelectronics Packaging.
Claims (amendment according to treaty the 19th article)
1. a microelectronics Packaging, comprising:
Substrate, described substrate has relative first surface and second surface, and the multiple substrate contact at described first surface place and the multiple terminals at described second surface place, for described microelectronics Packaging being connected at least one parts of described package outside; And
First microelectronic element and the second microelectronic element, described first microelectronic element and the second microelectronic element have the front surface of the first surface in the face of described substrate respectively, each microelectronic element has multiple element contacts at front surface place described in it, described element contacts and the corresponding described substrate contact of each microelectronic element are connected, the described front surface portion of described second microelectronic element covers and is attached to the rear surface of described first microelectronic element, the described element contacts of described second microelectronic element is exposed in the central area of the described front surface of described second microelectronic element,
The described element contacts of wherein said first microelectronic element to be arranged in the battle array of face and with substrate contact flip-chip bonding described in first group, the described element contacts of described second microelectronic element is connected by substrate contact described in conducting block and second group.
2. microelectronics Packaging according to claim 1, the described element contacts of wherein said second microelectronic element protrudes from outside the lateral edges of described first microelectronic element.
3. microelectronics Packaging according to claim 1, at least one in wherein said first microelectronic element and the second microelectronic element comprises memory component.
4. microelectronics Packaging according to claim 3, also comprise the multiple lead-in wires extending to described terminal from substrate contact described at least some, wherein said lead-in wire can be used for carrying address signal with at least one in described first microelectronic element and the second microelectronic element to described memory component addressing.
5. microelectronics Packaging according to claim 1, the wherein signal of terminal described at least some between to can be used for carrying in each terminal described and described first microelectronic element and the second microelectronic element each or at least one in reference potential.
6. microelectronics Packaging according to claim 1, also comprises multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to described substrate.
7. microelectronics Packaging according to claim 6, wherein said multiple 3rd microelectronic element is arranged to stacked structure, and each described 3rd microelectronic element has the facing front surface of the front surface of described three microelectronic element adjacent with or rear surface or rear surface.
8. microelectronics Packaging according to claim 6, wherein said multiple 3rd microelectronic element is arranged to planar structure, and each described 3rd microelectronic element has the facing peripheral surface of the peripheral surface of described three microelectronic element adjacent with.
9. microelectronics Packaging according to claim 6, wherein said second microelectronic element comprises volatibility RAM, each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises the processor being mainly used in controlling external module and the data between described second microelectronic element and the 3rd microelectronic element and transmitting.
10. microelectronics Packaging according to claim 6, wherein said second microelectronic element comprises volatibility frame buffer memory element, and each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises graphic process unit.
11. microelectronics Packaging according to claim 1, wherein the described element contacts of the second microelectronic element is arranged to a line at the center of the described front surface of contiguous described second microelectronic element or two parallel row.
12. microelectronics Packaging according to claim 1, wherein said conducting block is that elongated solder connects.
13. 1 kinds of systems, comprise multiple microelectronics Packaging according to claim 1, circuit board and processor, the described terminal of described microelectronics Packaging is electrically connected with the plate contact of described circuit board, each microelectronics Packaging is used within the clock cycle, transmit N number of parallel data bit, described processor is used within the clock cycle, transmit M parallel data bit, and M is more than or equal to N.
14. 1 kinds of systems, comprise microelectronics Packaging according to claim 1, and are electrically connected to other electronic units one or more of described microelectronics Packaging.
15. systems according to claim 14, also comprise housing, and described microelectronics Packaging and other electronic units described are mounted to described housing.
16. 1 kinds of modules, comprising:
Module card, described module card has first surface, the edge contact of second surface and multiple parallel exposure, described edge contact is close to the edge of at least one in described first surface and second surface, for when described module inserts socket, the contact docking corresponding to socket, described module card has multiple card contacts on the first surface; And
First microelectronic element and the second microelectronic element, described first microelectronic element and the second microelectronic element have the front surface of the described first surface in the face of described module card respectively, each microelectronic element has multiple element contacts at front surface place described in it, described element contacts and the corresponding described card contact of each microelectronic element are connected, the described front surface portion of described second microelectronic element covers and is attached to the rear surface of described first microelectronic element, the described element contacts of described second microelectronic element is exposed in the central area of the described front surface of described second microelectronic element,
The described element contacts of wherein said first microelectronic element to be arranged in the battle array of face and with card contact flip-chip bonding described in first group, the described element contacts of described second microelectronic element is connected by card contact described in conducting block and second group.
17. modules according to claim 16, the described element contacts of wherein said second microelectronic element protrudes from outside the lateral edges of described first microelectronic element.
18. modules according to claim 16, wherein said edge contact is exposed at least one place in the described first surface of described module card or second surface.
19. modules according to claim 16, at least one in wherein said first microelectronic element and the second microelectronic element comprises memory component.
20. modules according to claim 19, also comprise the multiple lead-in wires extending to described edge contact from card contact described at least some, wherein said lead-in wire can be used for carrying address signal with at least one in described first microelectronic element and the second microelectronic element to described memory component addressing.
21. modules according to claim 16, the wherein signal of edge contact described at least some between to can be used for carrying in each edge contact described and described first microelectronic element and the second microelectronic element each or at least one in reference potential.
22. modules according to claim 16, also comprise multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to described module card.
23. modules according to claim 22, described multiple 3rd microelectronic element is arranged to stacked structure, and each described 3rd microelectronic element has the facing front surface of the front surface of described three microelectronic element adjacent with or rear surface or rear surface.
24. modules according to claim 22, described multiple 3rd microelectronic element is arranged to planar structure, and each described 3rd microelectronic element has the facing peripheral surface of the peripheral surface of described three microelectronic element adjacent with.
25. modules according to claim 22, wherein said second microelectronic element comprises volatibility RAM, each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises the processor being mainly used in controlling external module and the data between described second microelectronic element and the 3rd microelectronic element and transmitting.
26. modules according to claim 22, wherein said second microelectronic element comprises volatibility frame buffer memory element, and each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises graphic process unit.
27. modules according to claim 16, wherein the described element contacts of the second microelectronic element is arranged to a line at the center of the described front surface of contiguous described second microelectronic element or two parallel row.
28. modules according to claim 16, wherein said conducting block is that elongated solder connects.
29. 1 kinds of systems, comprise multiple module according to claim 16, circuit board and processor, the contact of the described exposure of described module be inserted into be electrically connected with described circuit board to plug receptacle, each module is used within the clock cycle, transmit N number of parallel data bit, described processor is used within the clock cycle, transmit M parallel data bit, and M is more than or equal to N.
30. 1 kinds of systems, comprise module according to claim 16, and are electrically connected to other electronic units one or more of described module.
31. systems according to claim 30, also comprise housing, and described module and other electronic units described are mounted to described housing.

Claims (27)

1. a microelectronics Packaging, comprising:
Substrate, described substrate has relative first surface and second surface, and the multiple substrate contact at described first surface place and the multiple terminals at described second surface place, for described microelectronics Packaging being connected at least one parts of described package outside; And
First microelectronic element and the second microelectronic element, described first microelectronic element and the second microelectronic element have the front surface of the first surface in the face of described substrate respectively, each microelectronic element has multiple element contacts at front surface place described in it, described element contacts and the corresponding described substrate contact of each microelectronic element are connected, the described front surface portion of described second microelectronic element covers and is attached to the rear surface of described first microelectronic element
The described element contacts of wherein said first microelectronic element to be arranged in the battle array of face and with substrate contact flip-chip bonding described in first group, the described element contacts of described second microelectronic element is connected by substrate contact described in conducting block and second group.
2. microelectronics Packaging according to claim 1, the described element contacts of wherein said second microelectronic element protrudes from outside the lateral edges of described first microelectronic element.
3. microelectronics Packaging according to claim 1, at least one in wherein said first microelectronic element and the second microelectronic element comprises memory component.
4. microelectronics Packaging according to claim 3, also comprise the multiple lead-in wires extending to described terminal from substrate contact described at least some, wherein said lead-in wire can be used for carrying address signal with at least one in described first microelectronic element and the second microelectronic element to described memory component addressing.
5. microelectronics Packaging according to claim 1, the wherein signal of terminal described at least some between to can be used for carrying in each terminal described and described first microelectronic element and the second microelectronic element each or at least one in reference potential.
6. microelectronics Packaging according to claim 1, also comprises multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to described substrate.
7. microelectronics Packaging according to claim 6, wherein said multiple 3rd microelectronic element is arranged to stacked structure, and each described 3rd microelectronic element has the facing front surface of the front surface of described three microelectronic element adjacent with or rear surface or rear surface.
8. microelectronics Packaging according to claim 6, wherein said multiple 3rd microelectronic element is arranged to planar structure, and each described 3rd microelectronic element has the facing peripheral surface of the peripheral surface of described three microelectronic element adjacent with.
9. microelectronics Packaging according to claim 6, wherein said second microelectronic element comprises volatibility RAM, each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises the processor being mainly used in controlling external module and the data between described second microelectronic element and the 3rd microelectronic element and transmitting.
10. microelectronics Packaging according to claim 6, wherein said second microelectronic element comprises volatibility frame buffer memory element, and each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises graphic process unit.
11. 1 kinds of systems, comprise multiple microelectronics Packaging according to claim 1, circuit board and processor, the described terminal of described microelectronics Packaging is electrically connected with the plate contact of described circuit board, each microelectronics Packaging is used within the clock cycle, transmit N number of parallel data bit, described processor is used within the clock cycle, transmit M parallel data bit, and M is more than or equal to N.
12. 1 kinds of systems, comprise microelectronics Packaging according to claim 1, and are electrically connected to other electronic units one or more of described microelectronics Packaging.
13. systems according to claim 12, also comprise housing, and described microelectronics Packaging and other electronic units described are mounted to described housing.
14. 1 kinds of modules, comprising:
Module card, described module card has first surface, the edge contact of second surface and multiple parallel exposure, described edge contact is close to the edge of at least one in described first surface and second surface, for when described module inserts socket, the contact docking corresponding to socket, described module card has multiple card contacts on the first surface; And
First microelectronic element and the second microelectronic element, described first microelectronic element and the second microelectronic element have the front surface of the described first surface in the face of described module card respectively, each microelectronic element has multiple element contacts at front surface place described in it, described element contacts and the corresponding described card contact of each microelectronic element are connected, the described front surface portion of described second microelectronic element covers and is attached to the rear surface of described first microelectronic element
The described element contacts of wherein said first microelectronic element to be arranged in the battle array of face and with card contact flip-chip bonding described in first group, the described element contacts of described second microelectronic element is connected by card contact described in conducting block and second group.
15. modules according to claim 14, the described element contacts of wherein said second microelectronic element protrudes from outside the lateral edges of described first microelectronic element.
16. modules according to claim 14, wherein said edge contact is exposed at least one place in the described first surface of described module card or second surface.
17. modules according to claim 14, at least one in wherein said first microelectronic element and the second microelectronic element comprises memory component.
18. modules according to claim 17, also comprise the multiple lead-in wires extending to described edge contact from card contact described at least some, wherein said lead-in wire can be used for carrying address signal with at least one in described first microelectronic element and the second microelectronic element to described memory component addressing.
19. modules according to claim 14, the wherein signal of edge contact described at least some between to can be used for carrying in each edge contact described and described first microelectronic element and the second microelectronic element each or at least one in reference potential.
20. modules according to claim 14, also comprise multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to described module card.
21. modules according to claim 20, described multiple 3rd microelectronic element is arranged to stacked structure, and each described 3rd microelectronic element has the facing front surface of the front surface of described three microelectronic element adjacent with or rear surface or rear surface.
22. modules according to claim 20, described multiple 3rd microelectronic element is arranged to planar structure, and each described 3rd microelectronic element has the facing peripheral surface of the peripheral surface of described three microelectronic element adjacent with.
23. modules according to claim 20, wherein said second microelectronic element comprises volatibility RAM, each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises the processor being mainly used in controlling external module and the data between described second microelectronic element and the 3rd microelectronic element and transmitting.
24. modules according to claim 20, wherein said second microelectronic element comprises volatibility frame buffer memory element, and each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises graphic process unit.
25. 1 kinds of systems, comprise multiple module according to claim 14, circuit board and processor, the contact of the described exposure of described module be inserted into be electrically connected with described circuit board to plug receptacle, each module is used within the clock cycle, transmit N number of parallel data bit, described processor is used within the clock cycle, transmit M parallel data bit, and M is more than or equal to N.
26. 1 kinds of systems, comprise module according to claim 1, and are electrically connected to other electronic units one or more of described module.
27. systems according to claim 26, also comprise housing, and described module and other electronic units described are mounted to described housing.
CN201380067609.4A 2012-10-23 2013-10-18 Multiple die stacking for two or more die Pending CN104885217A (en)

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US13/658,401 US8952516B2 (en) 2011-04-21 2012-10-23 Multiple die stacking for two or more die
PCT/US2013/065605 WO2014066153A1 (en) 2012-10-23 2013-10-18 Multiple die stacking for two or more die

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CN110895630B (en) * 2018-09-12 2022-06-07 长鑫存储技术有限公司 Wafer stacking method and device, storage medium and electronic equipment
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WO2014066153A1 (en) 2014-05-01
TW201423954A (en) 2014-06-16

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