201239998 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之封裝製造技術，特別係 有關於一種防止基板周邊外露之模封陣列處理方法。 【先前技術】 傳統在半導體封裝技術中基於成本考量與量產需求 普遍採用模封陣列處理（Mold Array process，MAp)製 程。以一基板條（substrate strip)作為多個晶片之載體， 基板條包含有複數個排列成一矩陣之基板單元，在經過 設置晶片、電性連接等半導體封裝作業後，一形成面積 大於矩陣之模封膠體係連續覆蓋基板單元及基板單元之 間的切割道，再沿著切割道進行單體化切割，便可製得 複數個半導體封裝構造。 第1圖為一種利用模封陣列處理製得之習知窗口球 格陣列型態之半導體封裝構造，第2圖為模封陣列處理 中所使用之基板條。如第1圖所示，習知半導體封裝構 造100係主要包含一基板單元113、一晶片12〇、一封膠 體130。該晶片120係設置於該基板單元113之上表面 ill。如為窗口球格陣列型態時，該基板單元ιΐ3更具有 一貫穿上表面ill與下表面112之中央槽孔117，並且 位於該晶片120之主動面121之複數個電極122係對準 於該中央槽孔m内。該曰曰曰μ 120係常見地藉由複數個 打線形成之銲線150通過該中央槽孔U7電性連接該此 電極122至該基板單元113。而該封膠體13〇係形成於 201239998 - 該基板單元113之該上表面111上與該中央槽孔117 . 内’以密封該晶片120與該些銲線150，並且該基板單 元113之該下表面係可設有複數個銲球ι6〇，以作為該 半導體封裝構造1 〇〇對外電性連接之端子。然而依目前 習知模封陣列處理技術’該封膠體i 3 〇係無法覆蓋至該 基板單元113之側邊116，不可避免地造成該基板單元 11 3内部的核心層與金屬線路外露，使得水氣容易入侵 到封裝内部，導致產品可靠度不佳。 如第2圖所示，上述的基板單元113在習知模封陣列 處理過程中係為多個一體形成並呈矩陣排列在一習知基 板條110内。在相鄰基板單元113之間與周邊係定義有 複數個縱橫交錯的切割道114。配合參閱第丨圖，在黏 晶與電性連接之後，上述的封膠體丨30為模封形成並連 續地覆蓋在該些基板單元113與該些切割道114上。而 在每一基板單元11 3之間的切割道114在製程後段必須 被移除’以達到單體化分離，故基板條110之切割道114 部位與在該些切割道114上的封膠體不會存在於最終的 封裝產品内。當依據該些切割道114切離該基板單元113 時’會同時切穿該封膠體130與該基板條11〇，使得該 基板單元11 3具有切齊於該封膠體13 〇被切侧面之顯露 側邊11 6 ’即該基板單元11 3之侧邊1 1 6無法被該封膠 體1 3〇保護。因此，在單體化分離之後，該基板單元U3 之側邊11 6的電鍍線路與核心層會呈現外露狀態，導致 耐濕性較差’且易受到外界異物之干擾。此外=在單體[ 201239998 2分離過程中切割工具容易… ： 皁兀* Π3的周 戈疋破镇到位於該基板 【發明内容】 而造成後續以良影響。‘ 有鑒於此， ’本發明之主要目的禕力 板周邊外露 係在於楗供一種防止基 製程中的形成 列處理方法，利用兩種封装材料在 列處理方法中Μ㈣’解決習知模封陣 基板側邊外露的問題，可避争其扣留-邊之金屬了避免基板卓疋周 化、抗濕氣及對以冑’進而使封裝產品達到抗氧 封裝產品的耐"、^境侵害的作用，讀升半導體 本發明的日 案來實現的。本發明：其技術問題是採用以下技術方 陣列處理方法。：ΓΓ種防止基板周邊外露之模封 一 首先，k供一基板條。該基板條係具有 一上表面與—相對之下表面，該基板條係包含有複數個 基板單元，备~ A -k: SS -., 土扳單7G的尺寸係對應於一半導體封裝 構造’在相鄰基板單元之間係定義有一切割道。接著， 設置複數個晶片至該些基板單元上。之後，電性連接該 些晶片至對應之該些基板單元。之後，模封形成_第— 封裝材料於該基板條之該上表面，以連續地覆蓋該些基 板單元以及該些切割道。之後，進行一預切割步驟，其 係至少在該些切割道上形成複數個貫穿該基板條之切割 槽，但未貫穿該第一封裝材料，每一切割槽之寬度係大 於對應切割道之寬度，以使該些基板單元具有顯露在該 些切割道之外之周邊，之後，形成一第二封裝材料於該 201239998 些切割槽内，以包覆該些基板單元之周邊。最後，以切 割方式移除在該些切割道上之該第一封裝材料與在該些 切割道内之第二封裝材料，以單體化分離該些基板單元 為個別的半導體封裝構造’並且在切割後該些基板單元 之周邊係仍被該第二封裝材料所包覆。 本發明的目的及解決其技術問題還可採用以下技術201239998 VI. Description of the Invention: [Technical Field] The present invention relates to a package manufacturing technique for a semiconductor device, and more particularly to a method of processing a package array for preventing exposure of a periphery of a substrate. [Prior Art] Traditionally, based on cost considerations and mass production requirements in semiconductor packaging technology, a Mold Array process (MAp) process is commonly used. A substrate strip is used as a carrier for a plurality of wafers, and the substrate strip comprises a plurality of substrate units arranged in a matrix. After a semiconductor package operation such as a wafer or an electrical connection is formed, a mold having an area larger than a matrix is formed. The glue system continuously covers the scribe line between the substrate unit and the substrate unit, and then singulates along the scribe line to obtain a plurality of semiconductor package structures. Fig. 1 is a conventional semiconductor package structure of a conventional window grid array obtained by a mask array process, and Fig. 2 is a substrate strip used in a mold array process. As shown in FIG. 1, the conventional semiconductor package structure 100 mainly includes a substrate unit 113, a wafer 12, and a gel 130. The wafer 120 is disposed on the upper surface ill of the substrate unit 113. In the case of a window grid array, the substrate unit ι3 further has a central slot 117 extending through the upper surface ill and the lower surface 112, and the plurality of electrodes 122 located on the active surface 121 of the wafer 120 are aligned with the Inside the central slot m. The 曰曰曰μ 120 is commonly electrically connected to the substrate unit 113 through the central slot U7 through a plurality of bonding wires 150 formed by wires. The sealing body 13 is formed on the upper surface 111 of the substrate unit 113 and the central slot 117. The inner sealing hole 117 is sealed to seal the wafer 120 and the bonding wires 150, and the substrate unit 113 is disposed. The surface system may be provided with a plurality of solder balls ι6 〇 as terminals for externally electrically connecting the semiconductor package structure 1 . However, according to the conventional masking array processing technology, the encapsulant i 3 can not cover the side 116 of the substrate unit 113, which inevitably causes the core layer and the metal line inside the substrate unit 11 to be exposed, making the water vapor easy. Intrusion into the interior of the package results in poor product reliability. As shown in Fig. 2, the above-described substrate unit 113 is integrally formed and arranged in a matrix in a conventional substrate strip 110 during the conventional mold array processing. A plurality of criss-crossing dicing streets 114 are defined between adjacent substrate units 113 and the peripheral system. Referring to the first drawing, after the adhesive bonding and electrical connection, the above-mentioned sealing body 30 is formed by molding and continuously covers the substrate unit 113 and the cutting channels 114. The scribe line 114 between each of the substrate units 11 3 must be removed at the end of the process to achieve singulation separation, so that the scribe lines 114 of the substrate strip 110 and the sealant on the scribe lines 114 are not Will exist in the final packaged product. When the cutting unit 114 is cut away from the substrate unit 113, the sealing body 130 and the substrate strip 11 are cut through at the same time, so that the substrate unit 11 3 has the same surface as the sealing body 13 The side edge 1 6 ′, that is, the side edge 1 16 of the substrate unit 11 3 cannot be protected by the sealant 1 3〇. Therefore, after the singulation, the plating line and the core layer of the side edge 116 of the substrate unit U3 are exposed, resulting in poor moisture resistance and being susceptible to foreign foreign matter. In addition = in the monomer [201239998 2 separation process, the cutting tool is easy... : saponin * Π 3 week 疋 疋 镇 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 。 。 。 。 。 。 。 。 。 。 。 。 。 In view of the above, the main purpose of the present invention is to provide a method for preventing the formation of a column in a base process, using two kinds of packaging materials in the column processing method (4) to solve the side of the conventional die-laying substrate. Exposed problems can be avoided by detaining the metal of the side to avoid the durability of the substrate, the resistance to moisture, and the effect of 封装' and thus the packaged products to achieve the resistance of the antioxidant products. The semiconductor is realized by the daily case of the present invention. The present invention has a technical problem in that the following technique-side array processing method is employed. : A mold that prevents the periphery of the substrate from being exposed. First, k is supplied to a substrate strip. The substrate strip has an upper surface and a lower surface, the substrate strip includes a plurality of substrate units, and the size of the A-k: SS-., the size of the soil sheet 7G corresponds to a semiconductor package structure. A scribe line is defined between adjacent substrate units. Next, a plurality of wafers are disposed on the substrate units. Thereafter, the wafers are electrically connected to the corresponding substrate units. Thereafter, a mold-forming material is formed on the upper surface of the substrate strip to continuously cover the substrate units and the scribe lines. Thereafter, a pre-cutting step is performed to form a plurality of cutting grooves extending through the substrate strip at least on the dicing streets, but not through the first packaging material, and the width of each cutting groove is greater than the width of the corresponding cutting track. The substrate unit has a periphery exposed outside the dicing streets, and then a second encapsulating material is formed in the cutting grooves of the 201239998 to cover the periphery of the substrate units. Finally, the first encapsulating material on the dicing streets and the second encapsulating material in the dicing streets are removed in a dicing manner to singulate the substrate units into individual semiconductor package structures ′ and after dicing The periphery of the substrate units is still covered by the second encapsulating material. The object of the present invention and solving the technical problems thereof can also adopt the following technologies
措施進'步實現D 在前述的模封陣列處理方法中，該基板條在每一基板 單^内可另形成有-中央槽孔’在設置該些晶片之步驟 中，該些晶片之主叙 及 乃I主動面係可貼附至該基板條，並且該些 晶片之複數個電極係顯露在該中央槽孔内。 在前述的模封陣列處理方法中，在形成 料之步驟中，該篦展符 第一封裝材料係可更形成於該些中央槽 孔内。 、 在前述的模封陣列處理方法中，在所述的預切割步驟 央槽孔係可藉由形成在該基板條之該下表面 之凹槽而與該些切割槽連通。 在前述的模封陣列虚理 壯# Μ 〗處理方法中，在模封形成該第一封 裝材料之步驟中，該第一 封裝材料係可更形成於該此中 央槽孔内。 二Υ 在前述的模封陣列處 曰 處理方法中，所述的電性連接該些 曰日片與該些基板單元之 , ’驟係可包含以打線方式形成複 數個銲線’該些銲線係麵丄斗 ’'由該些中央槽孔連接該4b晶片 與該些基板單元。 —晶月 201239998 在前述的模封陣列處理方法中，所述的電性連接該些 晶片與該些基板單元之步驟係可包含以該基板條之複數 内引線通過該些中央槽孔接合至該些晶片之複數個電 極0 在則述的模封陣列處理方法中，在所述的形成該第二 ，装材料之步驟之後與在所述的單體化分離步驟之前， °另包3之步驟為：形成複數個銲球於該基板條之該下 表面。 在前述的模封陣列處理方法中，該第一封裝材料與該 第一封裝材料所切割移除之間隙寬度係可相同於該歧切 割道之寬度。 在刖述的模封陣列處理方法中，在所述的形成該第 〇材料之步驟之後與在所述的單體化分離步驟之前 =包含之步驟為：進行—後烘烤步驟，卩固化該第 封裝材料與該第二封裝材料。 由以上技術方案可以看出，本發明之防止基板周邊外 模封陣列處理方法，具有以下優點與功效： ―、可藉由在第一次模封之後在切割道上預切形成貫穿 基板條之切割槽作為本發明之其中一技術手段其 中切割槽之寬度大於對應切割道之寬度，再以第二 封裝材料形成於切割槽内’以包覆基板單元之； 邊。故在單體化分離步驟時，只會切穿封裝材料， 不會切到基板結構，解決習知模封陣列處理方法中 基板側邊外露㈣題，可避免基板單元周邊之金屬 7 201239998 線路與核心層外露，進而使封裝產品達到抗氧化、 抗濕氣及對抗其它環境侵害的作用，並提升半導體 封裝產品的耐用度。 二、可藉由兩種封裝材料在map製程中的形成以及其間 的預切割操作作為本發明之其中一技術手段，在模 封陣列處理之單體化分離步驟中不會切到基板結 構’避免單體化分離步驟的厚切割應力作用於基板 而造成内部線路變形或位移。 二、可藉由兩種封裝材料在MAP製程中的形成以及其間 的預切割操作作為本發明之其中一技術手段，配合 一同時固化兩種封裝材料之後烘烤步驟，以簡化 MAP製程步驟。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係’圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計’詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種防止基板周邊外 露之模封陣列處理方法舉例說明於第3A至3H圖之各步 驟中兀件之截面示意圖與第4圖完成預切割步驟後之基 201239998 板條之底視不意圖。該P方丨卜其你闲沒从办 邊防止丞板周邊外露之模封陣列處 理方法詳細說明如下。 首先，如第3A圖所示，提供一基板條21〇。該基板 條21〇係具有-上表自211與一相對之下表自212。該 上表面211係可供黏晶材料與封裝材料之設置，該下表 面212係可供接合複數個銲球，以供對外表面接合。通 常該基板條210係為一印刷電路板並設有單面或雙面電 性導通之金屬線路。該基板條21G亦可為__軟性電㈣ 膜或陶究電路板。如第4圖所*，該基板條2iq係包含 有複數個基板單元213，為半導體封裝構造内部的晶片 載體。每一基板單元213的尺寸係對應於一半導體封裝 構造200(如第3H圖所示），即第3A圖之基板單元213 之一寬度相同於第3H圖半導體封裝構造2〇〇之同一截 面方向之寬度。在相鄰基板單元213之間係定義有一切 割道214。該些基板單元213是矩陣排列在該基板條21〇 内，每一基板單元213係可概成矩形或正方形。在大量 生產時，該些基板單元213係整合地一體形成於該基板 條210内，該基板條210之側邊可設有對位孔（圖未繪出） 使彳牙在封裝製程得以自動化傳輸與定位。而該些切割道 214可包括橫向切割道與縱向切割道，並定義在相鄰基 板單元2 1 3之間，不作為半導體封裝構造之内部基板部 分。 接著’如第3B圖所示，設置複數個晶片22〇至該些 基板單το 2 1 3上，例如可以利用既有的黏晶操作達成。 201239998 而該些晶片220之材暫從-τ·* ^ 買係了為石夕、神化鎵或其它半導體 材質。該些晶片220之主叙而，及出二、> 動面221係形成有各式積體電 路元件’例如DDR2、DOR3 nnD/·够和 DDR3、DDR4等動態隨機存取記 憶體或者是非揮發性記，陰Μ ^ ^ lL _ t 干货丨王。己隐體，而該些電極222係為晶片 内部連接積體電路之對外端點，通常該些電極222係為 鋁或銅材質之銲墊，或可為突出於該些主動面221之導 電凸塊。該些電極222係可設置於該些晶4 22〇之該些 主動面22 1之單-側邊、兩對應側邊、四周侧邊或是中 央位置。通常該些晶片22〇係設置於對應基板單元213 内的中央位置。在本實施例中，每一基板單元上2丨3皆 設有一晶片220，但不受限定地，亦可應用至多晶片堆 疊之封裝，在每一基板單元213上可疊設複數個晶片。 可利用一雙面PI膠帶、液態環氧膠、預型片、B階黏膠 (B-stage adhesive)或是晶片貼附物質（Die AuachIn the foregoing method for processing a sealed array, the substrate strip may be further formed with a central slot in each substrate unit. In the step of disposing the wafers, the main description of the wafers And an active surface system can be attached to the substrate strip, and a plurality of electrode systems of the wafers are exposed in the central slot. In the above-described mold array processing method, in the step of forming a material, the first encapsulating material may be formed in the central slots. In the above-described mold array processing method, in the pre-cutting step, the central slot can communicate with the cutting grooves by grooves formed in the lower surface of the substrate strip. In the foregoing method of processing a molded array, the first package material may be further formed in the central slot in the step of molding the first package. In the above-mentioned method for processing a package array, the method of electrically connecting the plurality of wafers and the substrate units, the system may include forming a plurality of bonding wires by wire bonding. The tether bucket '' connects the 4b wafer and the substrate units from the central slots. - 晶月 201239998 In the foregoing method of processing a sealed array, the step of electrically connecting the wafers and the substrate units may include bonding the plurality of inner leads of the substrate strip through the central slots to the a plurality of electrodes 0 of the wafers, in the method of processing the package array described above, after the step of forming the second material, and before the step of separating the monomerization step To form a plurality of solder balls on the lower surface of the substrate strip. In the foregoing method of processing a sealed array, the gap width of the first encapsulating material and the first encapsulating material may be the same as the width of the tangential cut. In the method of processing the encapsulated array described above, after the step of forming the second material and before the step of separating the monomerization, the step of including: performing a post-baking step, curing the a first encapsulating material and the second encapsulating material. It can be seen from the above technical solution that the method for preventing the outer peripheral sealing array of the substrate has the following advantages and effects: ―, the cutting through the substrate strip can be pre-cut on the cutting path after the first molding. The groove is one of the technical means of the present invention, wherein the width of the cutting groove is larger than the width of the corresponding cutting channel, and then the second sealing material is formed in the cutting groove to cover the substrate unit; Therefore, in the singulation separation step, only the encapsulation material is cut through, and the substrate structure is not cut, so that the side of the substrate is exposed in the conventional mold-sealing array processing method (4), and the metal around the substrate unit can be avoided 7 201239998 line and core layer Exposed, which in turn makes the packaged products resistant to oxidation, moisture and other environmental insults, and enhances the durability of semiconductor package products. 2. The formation of the two encapsulating materials in the map process and the pre-cutting operation therebetween can be used as one of the technical means of the present invention, and the substrate structure is not cut in the singulation separation step of the mold array processing. The thick cutting stress of the singulation separation step acts on the substrate to cause internal line deformation or displacement. 2. The formation of the two encapsulating materials in the MAP process and the pre-cutting operation therebetween can be used as one of the technical means of the present invention, and a post-baking step of simultaneously curing the two encapsulating materials to simplify the MAP process step. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design. Detailed component layout may be more complicated. According to a first embodiment of the present invention, a method for processing a die-sealing array for preventing exposure of a periphery of a substrate is exemplified in a cross-sectional view of the components in the steps of FIGS. 3A to 3H and a basis after the pre-cutting step is completed in FIG. 4, 201239998 The bottom of the slats is not intended. The method of processing the module array that prevents you from being exposed from the side of the seesaw is described in detail below. First, as shown in Fig. 3A, a substrate strip 21 is provided. The substrate strip 21 has a top surface from 211 and a lower surface from 212. The upper surface 211 is provided for the bonding of the die attach material and the encapsulating material. The lower surface 212 is adapted to bond a plurality of solder balls for bonding to the outer surface. Typically, the substrate strip 210 is a printed circuit board and is provided with a single or double sided electrically conductive metal line. The substrate strip 21G may also be a __soft electric (four) film or a ceramic circuit board. As shown in Fig. 4, the substrate strip 2iq includes a plurality of substrate units 213 which are wafer carriers inside the semiconductor package structure. The size of each substrate unit 213 corresponds to a semiconductor package structure 200 (as shown in FIG. 3H ), that is, one of the substrate units 213 of FIG. 3A has the same width as the third section of the semiconductor package structure 2 . The width. All of the cut lanes 214 are defined between adjacent substrate units 213. The substrate units 213 are arranged in a matrix in the substrate strip 21, and each of the substrate units 213 can be substantially rectangular or square. In the mass production, the substrate units 213 are integrally formed integrally in the substrate strip 210, and the side edges of the substrate strip 210 may be provided with alignment holes (not shown) to enable automatic transmission of the cavities in the packaging process. With positioning. The scribe lines 214 may include transverse scribe lines and longitudinal scribe lines and are defined between adjacent substrate units 21 and 3 as internal substrate portions of the semiconductor package construction. Next, as shown in Fig. 3B, a plurality of wafers 22 are disposed on the substrate sheets το 2 1 3, for example, by using an existing die bonding operation. 201239998 And the materials of these wafers 220 were temporarily purchased from -τ·* ^ for Shi Xi, deuterated gallium or other semiconductor materials. The above-mentioned wafers 220 are mainly described as follows, and the moving surface 221 is formed with various integrated circuit elements such as DDR2, DOR3 nnD/· and dynamic random access memory such as DDR3 or DDR4 or non-volatile. Sex, yin ^ ^ lL _ t dry goods king. The electrodes 222 are interconnected with the outer ends of the integrated circuits. Generally, the electrodes 222 are aluminum or copper pads, or may be conductive protrusions protruding from the active surfaces 221 . Piece. The electrodes 222 can be disposed on the single-side, the two corresponding sides, the sides, or the center of the active surfaces 22 1 of the plurality of crystals 22 . Usually, the wafers 22 are disposed at a central position within the corresponding substrate unit 213. In this embodiment, a wafer 220 is disposed on each of the substrate units, but is not limited thereto, and may be applied to a multi-wafer stack, and a plurality of wafers may be stacked on each of the substrate units 213. Can use a double-sided PI tape, liquid epoxy, pre-form, B-stage adhesive or wafer attachment material (Die Auach
Material，DAM)，以黏接該些晶片22〇至該些基板單元 213上。此外，本實施例係運用窗口型球格陣列封裝的 應用例’該些晶片220之主動面22丨係貼附於該基板條 210之該上表面211;並且，該基板條21〇在每一基板單 元213内可另形成有一中央槽孔217，該中央槽孔217 係貫穿該基板條210並位於每一基板單元213之一中央 位置。在本實施例中，該些電極222係分佈排列於該些 晶片220主動面221之中央，並對準於該些中央槽孔 217。在設置該些晶片220之步驟之後，該些晶片220 之複數個電極222係顯露在該中央槽孔217内。 10 201239998 4 之後，如第3C圖所示，電性連接該些晶片220至對 應之該些基板單元213。所述的電性連接該些晶片220 與該些基板單元213之步驟係可包含以打線方式形成複 數個銲線250，該些銲線250係經由該些中央槽孔217 連接該些晶片220之電極222與該些基板單元213内部 線路之接指。該些銲線250係可利用打線製程所形成之 金屬細線’其材質可為金、或是採用類似的高導電性的 金屬材料（例如銅或銘），可利用該些銲線250係作為該 些晶片220至該些基板單元213之間的訊號傳遞與接地/ 電源的連接。然不受限地，該些晶片22〇除了可以打線 電性連接之外，亦可以覆晶接合（flip chip b〇nding)、引 腳接合（lead bond)或是其它已知電性連接方式完成該些 晶片220與該些基板單元2 1 3之電性互連。 之後，如第3D圖所示，模封形成一第一封裝材料23〇 於該基板條210之該上表面211，以連續地覆蓋該些基 板單元213以及該些切割道214,即該第一封裝材料23〇 之覆蓋面積係相當於或大於組成該些基板單元213的矩 陣面積。較佳地，該第一封裝材料23〇更可覆蓋該些晶 片220，使其不受到外界污染物的污染。但不受限定地， 該些晶片220亦可為裸晶型態而顯露出該些晶片22〇之 背^以利散熱。具體而言，該第一封農材料23〇係可為 % 氧模封化合物（ep〇xy m〇lding compound，，通 常具有絕緣性與熱固性。該第—封裝材料23g係能以轉 移成型（transfer m〇ldi⑻或稱壓模的技術加以形成或 201239998 :該第-封裝材肖23。亦可使用其他已知的模封製程形 佳地，縮模封、使用一模具之印刷或噴塗等等。較 在模封形成該第一封裝材料23〇之步 訂裝材# 230係可更形成於該些中央槽孔217内以 密：該些銲線25〇，故在後續的預切割步驟中切割碎屑 二：入該些中央槽孔217内’便不會造成該些銲線250 ^、。並且，該第一封裝材料23〇係可突出於 面 212。 ,如第3E與4圖所示，在該第一封裝材料23〇形成之 後，進行—預切割步驟，其係在該些切割道上形成 複數個貫穿該基板條210之切割槽215，但未貫穿該第 一封裝材料230。雖該基板條210被切穿，但利用該第 一封裝材料23〇仍可結合該些晶片22〇與該些基板單元 213不致散離。特別如第4圖所示，在預切割步驟之後， 每一切割槽215之寬度W1係大於對應切割道214之寬 度W2,以使該些基板單元213具有顯露在該些切割道 2 14之外之周邊2 1 6。具體而言，該些切割槽2丨5係沿著 切割道2 1 4而呈縱向或/與橫向直線排列，但切割槽2 i $ 之寬度wi應大於對應切割道214之寬度W2，換古之， 所移除部分除了包含有切割道214更包含該些基板單元 213之邊緣，以更大之開口槽的型態使該些基板單元 之該些周邊216不與該些切割道214重疊。詳細而士， 該些切割槽2 1 5之寬度約為對應切割道2 1 4之寬度之丄2 倍至2倍。再如第3E圖所示，該些切割槽2丨5之切割深 12 201239998 度係應足以切穿該基板條210但可不超過該第一封裝材 料230之厚度，形成之切割槽215係呈溝渠（trench)狀。 一般而言，該基板條210的厚度約為0.08 mm至0.3 mm， 在一實施例中，該些切割槽215的高度可實質上與該基 板條2 10的厚度相同。更細部而言，該些切割槽215係 可由任何方法製成，例如是雷射鑽孔或機械加工。舉例 來說’該些切割槽2丨5係可利用一大於切割道2丨4寬度 之刀具，由該下表面212往該上表面211方向切割，以 形成該些切割槽215。該些切割槽215之截面形狀可為 矩形v形、曲線形、錐形、漏斗形或是底部逐漸縮小 之梯形。 禾與3F圖所示Material, DAM), to bond the wafers 22 to the substrate units 213. In addition, in this embodiment, an application example of the window type ball grid array package is used, and the active surface 22 of the wafers 220 is attached to the upper surface 211 of the substrate strip 210; and the substrate strip 21 is disposed in each A central slot 217 may be formed in the substrate unit 213. The central slot 217 extends through the substrate strip 210 and is located at a central position of each of the substrate units 213. In this embodiment, the electrodes 222 are distributed in the center of the active surface 221 of the wafer 220 and aligned with the central slots 217. After the steps of disposing the wafers 220, a plurality of electrodes 222 of the wafers 220 are exposed in the central slot 217. 10 201239998 4 Then, as shown in FIG. 3C, the wafers 220 are electrically connected to the corresponding substrate units 213. The step of electrically connecting the wafers 220 and the substrate units 213 may include forming a plurality of bonding wires 250 by wire bonding, and connecting the bonding wires 250 to the transistors 220 via the central slots 217. The electrode 222 is connected to the internal lines of the substrate units 213. The bonding wires 250 are metal thin wires formed by a wire bonding process, which may be made of gold or a similar highly conductive metal material (for example, copper or metal), and the bonding wires 250 may be used as the wire. The signal transfer between the wafers 220 and the substrate units 213 is connected to the ground/power source. However, the wafers 22 can be electrically connected by flip-chip bonding, lead bonding, or other known electrical connections. The wafers 220 are electrically interconnected with the substrate units 213. Then, as shown in FIG. 3D, a first encapsulation material 23 is formed on the upper surface 211 of the substrate strip 210 to continuously cover the substrate units 213 and the dicing streets 214, that is, the first The coverage area of the encapsulation material 23 is equivalent to or larger than the area of the matrix constituting the substrate units 213. Preferably, the first encapsulating material 23 覆盖 covers the wafers 220 so as not to be contaminated by external pollutants. However, without limitation, the wafers 220 may also be in a bare crystalline form to expose the backs of the wafers 22 for heat dissipation. Specifically, the first agricultural material 23 can be an oxy oxime compound (ep〇xy m〇lding compound, usually having insulation and thermosetting property. The first packaging material 23g can be transferred by transfer (transfer) The technology of m〇ldi (8) or stamper is formed or 201239998: the first package material is 23. Other known mold-molding methods can be used, shrink-sealing, printing or spraying using a mold, and the like. The step of forming the first encapsulating material 23 in the form of the first encapsulating material 23 is more formed in the central slots 217 to be dense: the bonding wires 25 are cut, so that the cutting is performed in the subsequent pre-cutting step. Debris 2: into the central slots 217 'will not cause the wire 250 ^, and the first encapsulating material 23 can protrude from the face 212. As shown in Figures 3E and 4 After the first encapsulating material 23 is formed, a pre-cutting step is performed on the dicing streets to form a plurality of dicing grooves 215 extending through the substrate strip 210, but not through the first encapsulating material 230. The substrate strip 210 is cut through, but the first encapsulating material 23 can still be used. The wafers 22 are not separated from the substrate units 213. In particular, as shown in FIG. 4, after the pre-cutting step, the width W1 of each of the cutting grooves 215 is greater than the width W2 of the corresponding cutting path 214, so that The substrate unit 213 has a periphery 2 16 which is exposed outside the scribe lines 2 14 . Specifically, the cutting grooves 2 丨 5 are arranged longitudinally or/and horizontally along the scribe line 2 1 4 . However, the width wi of the cutting groove 2 i $ should be greater than the width W2 of the corresponding cutting channel 214. In other words, the removed portion includes the cutting channel 214 and the edge of the substrate unit 213, and the larger opening slot. The shape of the substrate 216 of the substrate unit does not overlap with the scribe lines 214. In detail, the width of the cutting grooves 2 15 is about 2 times the width of the corresponding scribe line 2 1 4 to Further, as shown in FIG. 3E, the cutting depths of the cutting grooves 2丨5 12 201239998 should be sufficient to cut through the substrate strip 210 but may not exceed the thickness of the first encapsulating material 230 to form the cutting groove 215. The structure is in the form of a trench. Generally, the thickness of the substrate strip 210 is about 0.08 mm. Up to 0.3 mm, in an embodiment, the height of the cutting grooves 215 may be substantially the same as the thickness of the substrate strips 2 10 . In more detail, the cutting grooves 215 may be made by any method, such as a thunder. Drilling or machining. For example, the cutting grooves 2丨5 can be cut by the lower surface 212 toward the upper surface 211 by using a cutter larger than the width of the cutting lane 2丨4 to form the cutting. The groove 215. The cross-sectional shape of the cutting grooves 215 may be a rectangular v-shape, a curved shape, a tapered shape, a funnel shape or a trapezoidal shape with a tapered bottom portion. Wo and 3F diagram
15L 一岡η丨小，爪肷一弟二對裝材 240於該些切割槽& J槽215内，以包覆該些基板單元213 周邊216。且體而+ ’、 5 ’該第二封裝材料240係填滿該 切割槽215以使誃此田土 二周邊216不外露。詳細而言，該 二封裝材料240之耔w於 230,或為不相同之/質係可…該第-封裝材 高於該第-封裝材料、之= 緣性熱固性樹脂，例如流動 轉移成形）方法形成1 P填充膠。除了傳統模封（或 點塗方法形成該第1不同實施例中’或可利用印刷 ―封裝材料240。插p t 形成該第二封裝材 寸一 k的是， 步驟，以固化該第― ㈣之後可另進行一後烘 240，使其材料安定封裝材料230與該第二封裝材 在map製程中 成形。因此，可藉由兩種封裝材 成以及其間的預切割操作作 13 201239998 明之其中一技術手段，配合一同時固化兩種封裝材料之 後烘烤步驟，以簡化MAP製程步驟。 更具體地’如第3G圖所示，在形成該第二封裝材料 240之步驟之後與單體化分離步驟之前，可形成複數個 銲球2 5 0於該基板條2 1 0之該下表面2 1 2，以供對外表 面接合至外部之印刷電路板。該些銲球250係可呈柵狀 陣列排列，使相同單位面積之基板單元21 3可以容納更 多輸入/輸出連接端（I/O Connection)以符合高度集積化 (Integration)之半導體晶片所需。然而不受限定地，在不 同的實施例中’該些銲球250亦可替換為錫膏、接觸墊 或接觸針。 最後，如第3G與3H圖所示，以切割方式移除在該 些切割道214上之該第一封裝材料23〇與在該些切割道 214内之第二封裝材料24〇，以單體化分離該些基板單元 213為個別的半導體封裝構造2〇〇,並且在切割後該些基 板單το 213之周邊216係仍被該第二封裝材料24〇所包 覆。故在單體化分離步驟時，只會切穿該第二封裝材料 240 ’不會切到該基板單元2丨3結構，解決習知模封陣列 處理方法中基板側邊外露的問冑，如此可避免位在該些 基板單το 213周邊215之金屬線路與核心層外露，進而 使封袭產品達到抗氧化、抗濕氣及對抗其它環境侵害的 作用’以提升半導體封裝產品料用度。此彳，在模封 :列處理之單體化分離步驟中不會切到基板結構，避免 早體化分離步驟的厚切割應力作用於該基板條21〇而造 14 201239998 成内部線路變形或位移。 具體而。，如第3E圖所示，由於該些切割道214之 寬度應小於該此你电丨福 二切割槽215之寬度，當該第一封裝材料 230與該第二封桊 可裝材枓240所切割移除之間隙寬度S係 可相同於該4b切宝，丨、长1 , λ 一 〇 〜 …道心14之寬度W2(如第3G與圖所 )在單體化分離步驟中便可確保不會切到該些切割槽 215之兩側（即基板單元之側邊216)，故在每-獨立的半 導體封裝構造中兮笛_ 〇〇 τ通第一封裝材料240仍可覆蓋住該些基 板早元213之oiz：— <周邊216’可避免位在該些基板單元213 周邊1 5之金屬線路與核心、層外露，進而使封裝產品達 到抗氧化、抗濕氣及對抗其它環境侵害的作用，以提升 半導體封裝產品的耐用度。 本發明之第二具體實施例揭示另一種防止基板周邊 外露之模封陣列處理方法’圖例說明於第5A至5h圖各 步驟中元件之截面示意圖。其中與第一實施例相同功能 的主次要元件以相同符號標示，細部不再予以贅述。 首先’如第5A與6圖所示，提供一基板條21〇。在 本實施例中’除了内部線路結構，該基板條2 1 G係可更 包3複數個内引線319。該些内引線319係可為該基板 條2 1 0内部金屬線路層之延伸部份或由外附加的懸空内 引線（lead)，通常係為表面有電鍍層之銅線，可利用蝕刻 銅泊等的金屬箔或導電箔再經電鍍而形成，故真有可撓 曲性。在未電性連接之前’該些内引線319係可通過上 述之該些中央槽孔217而為騰空。 15 201239998 接著，如第5B圖所示，設置複數個晶片22〇至該些 基板單元213上，並且可使該些晶片220之該些電極222 係顯露在該中央槽孔217内。之後，如第5C圖所示， 電性連接該些晶片220與該些基板單元213，其係以該 基板條210之該些内引線319通過該些中央槽孔2ι 7接 合至該些晶片220之該些電極222。可利用内引腳壓合 治具（ILB bonding head)打斷該些内引線319的預斷點並 使該些内引線319壓合接觸至該些晶片22〇之該些電極 222，而與該些晶片220達到訊號溝通之電性連接。相較 於打線接合電性連接之方式，利用内弓丨線319壓合接觸 之電性連接方式’不會有線弧以使訊號路徑得以縮短， 並且不會有銲線兩端的金屬焊接界面，能適用於高頻積 體電路封裝。 之後，如第5D圖所示，模封形成一第一封裝材料23〇 於該基板# 2H)之該上表面211，以連續地覆蓋該些基 板單元2U以及該些切割道214，更可覆蓋該些晶片 220，使其不受到外界污染物的污染。 之後如第5E與7圖所示，進行—預切割步驟，其 係在該些切割道214上形成複數個貫穿該基板條2H)之 切割槽215，但未貫穿該第一封裝材料23〇,每一切割槽 2 1 5之寬度W1係大於對庠切宝丨言 丁愿切割道214之寬度W2，以使15L 冈 丨 丨 small, 肷 肷 一 一 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二And the second encapsulating material 240 fills the cutting groove 215 so that the second perimeter 216 of the field is not exposed. In detail, the two encapsulating materials 240 are at 230 or different from each other. The first encapsulating material is higher than the first encapsulating material, the edge thermosetting resin, such as flow transfer molding. The method forms a 1 P filler. In addition to the conventional molding (or the dot coating method is formed in the first different embodiment) or the printing-encapsulating material 240 can be utilized. Inserting pt to form the second packaging material is a step, to cure the first (four) A post-baking 240 may be further performed to form the material-stabilizing encapsulating material 230 and the second encapsulating material in a map process. Therefore, one of the techniques of the two encapsulating materials and the pre-cutting operation therebetween may be used as one of 13 201239998. Means, in conjunction with a simultaneous baking process of the two encapsulating materials to simplify the MAP process step. More specifically, as shown in FIG. 3G, after the step of forming the second encapsulating material 240 and before the singulation separation step a plurality of solder balls 250 may be formed on the lower surface 2 1 2 of the substrate strip 2 1 0 for bonding the external surface to the external printed circuit board. The solder balls 250 may be arranged in a grid array. The substrate unit 21 3 of the same unit area can accommodate more input/output connections (I/O Connections) to meet the requirements of a highly integrated semiconductor wafer. However, without limitation, in different In the embodiment, the solder balls 250 may also be replaced by solder pastes, contact pads or contact pins. Finally, as shown in FIGS. 3G and 3H, the first package on the scribe lines 214 is removed by cutting. The material 23〇 and the second encapsulating material 24〇 in the dicing streets 214 are singulated to separate the substrate units 213 into individual semiconductor package structures 2 〇〇, and after dicing the substrates το 213 The periphery 216 is still covered by the second encapsulating material 24, so in the singulation separation step, only the second encapsulating material 240' is cut through, and the substrate unit 2丨3 structure is not cut, and the conventional mode is solved. In the array array processing method, the side of the substrate is exposed, so that the metal lines and the core layer located at the periphery 215 of the substrate το 213 can be prevented from being exposed, thereby making the sealed product resistant to oxidation, moisture and other environments. The role of infringement is to improve the material content of the semiconductor package product. In this case, the substrate structure is not cut in the singulation separation step of the mold: column treatment, and the thick cutting stress of the early separation step is prevented from acting on the substrate. Article 21 and made 14 201239998 is deformed or displaced into the internal line. Specifically, as shown in FIG. 3E, since the width of the cutting lanes 214 should be smaller than the width of the electric cutting groove 215, when the first encapsulating material 230 is The gap width S of the second sealable material 枓 240 can be the same as that of the 4b cut, 丨, length 1, λ 〇 ... ... the width W2 of the center 14 (such as the 3G and the map In the singulation separation step, it can be ensured that the two sides of the cutting grooves 215 (ie, the side edges 216 of the substrate unit) are not cut, so that in each-independent semiconductor package structure, the flute _ 〇〇 通The first encapsulating material 240 can still cover the oiz of the substrate 213: - < periphery 216' can avoid the metal lines and cores and layers located at the periphery of the substrate unit 213, thereby exposing the package product Anti-oxidation, moisture resistance and other environmental protection to enhance the durability of semiconductor packaging products. A second embodiment of the present invention discloses another method of processing a package array for preventing peripheral exposure of a substrate. The illustration illustrates a schematic cross-sectional view of elements in the steps of Figs. 5A to 5h. The primary and secondary components having the same functions as those of the first embodiment are denoted by the same reference numerals, and the detailed description thereof will not be repeated. First, as shown in Figs. 5A and 6, a substrate strip 21 is provided. In the present embodiment, in addition to the internal wiring structure, the substrate strip 2 1 G can further include a plurality of inner leads 319. The inner leads 319 may be extensions of the inner metal circuit layer of the substrate strip 210 or externally attached leads, usually copper wires with a plating layer on the surface, which can be etched with copper The metal foil or the conductive foil is formed by electroplating, so that it is really flexible. The inner leads 319 can be emptied by the central slots 217 as described above prior to the electrical connection. 15 201239998 Next, as shown in FIG. 5B, a plurality of wafers 22 are disposed on the substrate units 213, and the electrodes 222 of the wafers 220 are exposed in the central slots 217. Then, as shown in FIG. 5C, the wafers 220 and the substrate units 213 are electrically connected to the wafers 220 through the central slots 2 117 through the inner leads 319 of the substrate strips 210. The electrodes 222. The pre-break points of the inner leads 319 can be interrupted by using an inner lead bonding fixture (ILB bonding head), and the inner leads 319 are press-contacted to the electrodes 222 of the wafers 22, and The wafer 220 is electrically connected to the signal communication. Compared with the way of wire bonding electrical connection, the electrical connection method of pressing the contact with the inner bow line 319 'will not be wired arc to shorten the signal path, and there is no metal welding interface at both ends of the wire. Suitable for high frequency integrated circuit packages. Then, as shown in FIG. 5D, a first encapsulation material 23 is formed on the upper surface 211 of the substrate #2H) to continuously cover the substrate units 2U and the dicing streets 214, and is covered. The wafers 220 are free from contamination by external contaminants. Thereafter, as shown in FIGS. 5E and 7 , a pre-cutting step is performed on the plurality of dicing streets 214 to form a plurality of dicing grooves 215 extending through the substrate strip 2H), but not through the first encapsulating material 23 〇, The width W1 of each of the cutting grooves 2 1 5 is greater than the width W2 of the cutting channel 214 of the cutting plaque, so that
s亥些基板單元213具有海霞户斗a L ，顯露在該些切割道214之外之周 邊216。具體而言，如第7圖路-斗 圖所不’該些切割槽2丨5係 沿著切割道2 14而呈縱向或（盥 Μ興）k向直線排列，但切割【 16 201239998 槽215之寬度應W1大於對應切割道2i4之寬度w2，以 使該些基板單元213之該些周邊216不位在該些切割道 214上，而是具有更大之開口。在本實施例中，如第5E 圖所不，該些切割槽215的深度係可與該基板條21〇的 厚度相同，可不需要切割到該第—封裝材料。該些 切槽215之截面形狀係可為矩形。此外，如第7圖所 不較佳地，在所述的預切割步驟中，該些中央槽孔217 係可藉由形成在該基板條21〇之該下表面212之凹槽 318而與該些切割槽215連通。該些凹槽Big係不貫穿 該基板條210,其切割深度可不大於該些切割槽215。 之後，如第5E與5F圖所示，形成一第二封裝材料 240於該些切割槽215内，以包覆該些基板單元213之 周邊2丨6。於此步驟中，該第二封裝材料24〇係可更形 成於該些中央槽孔内217,較佳地可利用與該些切割槽 215連通之凹槽318將該第二封裝材料24〇導流至該些 中央槽孔内2丨7’故該些凹槽318亦可佈滿該第二封裝 材料240’以密封該些内引線319。在一具體結構中該 第二封裝材料240之填充高度係可不超過該基板條21〇 之該下表面212。 之後，如第5G圖所示，在形成該第二封裝材料2 之步驟之後與單體化分離步驟之前，可形成複數個銲 250於該基板條210之該下表面212，以供對外表面接 至外部之印刷電路板。 最後，如第5G肖5H圖所示，以切割方式移除在 17 201239998 些切割道214上之該第—封裝材料23〇與在該些切割道 214内之第二封裝材料24〇，以單體化分離該些基板單元 213為個別的半導體封裝構造3〇〇,並且在切割後該些基 板單元213之周邊216係仍被該第二封裝材料鳩所包 覆。因此’本發明在模封陣列處理中可避免基板單元周 邊之金屬線路與核心層外露’進而使封裝產品達到抗氧 化、抗濕氣及對抗其它環境侵害的作用，以提升半導體 封裝產品的耐用度。 以上所述，僅是本發明的較佳實施例而已，並非對本 ，月作任何形式上的限制’雖然本發明已以較佳實施例 揭露如上1而並非用以限定本發明，任何熟悉本項技 術者’在不脫離本發明之枯 交月之技術範圍内，所作的任何簡輩 修改、等效性變化與修飾，均屈 【圖式簡單說明】Φ屬於本發明的技術範圍内。 第W :、-種以習知模封陣列處理製造之半導體封裝構 造之截面示意圖。 第2圖：一種基板條之局部俯視示意圖。 第3Α至3Η圖：依據本發明之第—具體實施例的一種防 止基板周邊外露之模封陣列處理方法各步驟中 之元件截面示意圖。 第4圖：依據本發明之第-具體實施例的模封陣列處理 =在元成預切割步驟之後之基板條之底視示 第W:依據本發明之第二具體實 18 201239998 防止基板周邊外露之模封陣列處理方法各步驟 中之元件截面示意圖。 依據本發明之第二具體實施例的模封陣列處理 方法中在提供基板條步驟中之基板條之底視示 意圖。 第7圖.依據本發明之第二具體實施例的模封陣列處理 方法中在完成預切割步驟後之基板條之底視示 意圖。 【主要元件符號說明】 s 間隙寬度 W 1 切割槽之寬度 W2 切割道之寬度 100半導體封裝 11 0基板條 113基板單元 11 6側邊 120晶片 1 3 0封裝材料 150銲線 2〇〇半導體封裝 2 1 0基板條 2 13基板單元 216周邊 220晶片 構造 111上表面 11 4切割道 117中央槽孔 1 2 1主動面 160銲球 構造 211上表面 2 1 4切割道 2 1 7中央槽孔 2 2 1主動面 11 2下表面 122電極 212下表面 2 1 5切割槽 222 電極 19 201239998 230第一封裝材料 240第二封裝材料 250銲線 260銲球 3 00半導體封裝構造 318 凹槽 3 19 内引線 20The substrate unit 213 has a Haixia household bucket a L and is exposed on the periphery 216 outside the cutting lanes 214. Specifically, as shown in FIG. 7 , the cutting grooves 2 丨 5 are longitudinally arranged along the cutting path 2 14 or in a straight line, but are cut [16 201239998 slot 215 The width W1 is greater than the width w2 of the corresponding scribe line 2i4, so that the peripheral portions 216 of the substrate units 213 are not located on the scribe lines 214, but have larger openings. In the present embodiment, as shown in Fig. 5E, the depth of the cutting grooves 215 may be the same as the thickness of the substrate strip 21, and it is not necessary to cut into the first packaging material. The cross-sectional shapes of the slits 215 may be rectangular. In addition, as shown in FIG. 7, in the pre-cutting step, the central slots 217 can be formed by the recesses 318 formed on the lower surface 212 of the substrate strip 21 The cutting grooves 215 are in communication. The grooves Big do not penetrate the substrate strip 210, and the cutting depth may not be larger than the cutting grooves 215. Then, as shown in FIGS. 5E and 5F, a second encapsulating material 240 is formed in the cutting grooves 215 to cover the periphery 2丨6 of the substrate units 213. In this step, the second encapsulating material 24 can be further formed in the central slots 217. Preferably, the second encapsulating material 24 can be guided by the recesses 318 communicating with the cutting slots 215. The recesses 318 may also flow through the second encapsulation material 240' to seal the inner leads 319. In a specific structure, the filling height of the second encapsulating material 240 may not exceed the lower surface 212 of the substrate strip 21〇. Thereafter, as shown in FIG. 5G, after the step of forming the second encapsulating material 2 and before the singulation separation step, a plurality of solders 250 may be formed on the lower surface 212 of the substrate strip 210 for external surface connection. To the external printed circuit board. Finally, as shown in FIG. 5G, FIG. 5H, the first encapsulating material 23〇 on the cutting lanes 214 of 17 201239998 and the second encapsulating material 24〇 in the cutting lanes 214 are removed by cutting. The substrate units 213 are separated into individual semiconductor package structures 3, and the perimeters 216 of the substrate units 213 are still covered by the second package material after the dicing. Therefore, the present invention can prevent the metal circuit and the core layer from being exposed around the substrate unit in the process of the package array, thereby preventing the packaged product from resisting oxidation, moisture and other environmental damage, thereby improving the durability of the semiconductor package product. . The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. However, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. Any minor modification, equivalence change, and modification made by the skilled person within the technical scope of the present invention without departing from the present invention are all within the technical scope of the present invention. W:, a schematic cross-sectional view of a semiconductor package structure fabricated by conventional die-sealed array processing. Figure 2: A partial top view of a substrate strip. 3 to 3 are schematic cross-sectional views showing elements in respective steps of a method of processing a package array for preventing exposure of a periphery of a substrate in accordance with a first embodiment of the present invention. Figure 4: Molded array processing according to the first embodiment of the present invention = bottom view of the substrate strip after the pre-cutting step of the element: W: according to the second embodiment of the present invention 18 201239998 Preventing the periphery of the substrate from being exposed A schematic cross-sectional view of the components in each step of the mold-sealing array processing method. The bottom view of the substrate strip in the step of providing the substrate strip in the method of processing the package array according to the second embodiment of the present invention. Fig. 7 is a view showing the bottom of a substrate strip after completion of the pre-cutting step in the method of processing the package array according to the second embodiment of the present invention. [Main component symbol description] s gap width W 1 width of the cutting groove W2 width of the cutting channel 100 semiconductor package 11 0 substrate strip 113 substrate unit 11 6 side 120 wafer 1 3 0 packaging material 150 bonding wire 2 semiconductor package 2 10 0 substrate strip 2 13 substrate unit 216 perimeter 220 wafer structure 111 upper surface 11 4 cutting channel 117 central slot 1 2 1 active surface 160 solder ball structure 211 upper surface 2 1 4 cutting lane 2 1 7 central slot 2 2 1 Active surface 11 2 lower surface 122 electrode 212 lower surface 2 1 5 cutting groove 222 electrode 19 201239998 230 first encapsulating material 240 second encapsulating material 250 bonding wire 260 solder ball 3 00 semiconductor package construction 318 groove 3 19 inner lead 20