TW201434096A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The purpose of the present invention is to provide a lamination type semiconductor device that is thin and easy to be manufactured. The present invention is characterized by comprising: a chip laminated body 1 composed of a plurality of semiconductor chips 1a-1h; a support 20, which is laminated on the top semiconductor chip 1h of the chip laminated body 1; and a resin package 30, which seals the chip laminated body 1 to make one main surface 20A of the support 20 to be exposed entirely and enclosing a lateral side 20S adjacent to the main surface 20A.

Description

Semiconductor device and method of manufacturing same [related application]

This application claims priority from the application based on Japanese Patent Application No. 2013-39217 (filed on Feb. 28, 2013). This application contains the entire contents of the basic application by reference to the basic application.

Embodiments of the present invention relate to a semiconductor device and a method of fabricating the same.

Conventionally, there has been disclosed a laminated semiconductor device technology in which a plurality of thin-processed semiconductor wafers are laminated and resin-sealed when forming a high-capacitance element such as a NAND-type flash memory. In such a semiconductor device, high capacitance, high functionality, and thinning are required. It is important to not only reduce the thickness of the semiconductor device, but also to further reduce the distance from the uppermost semiconductor wafer to the surface of the semiconductor device (hereinafter, the resin thickness on the wafer).

However, in the prior art, there is a problem of "circuit destruction of a semiconductor wafer caused by laser when marking the surface of a semiconductor device" or "filling resin filling property on a semiconductor wafer". Further, as one of the representative molding methods of the thermosetting resin (plastic), there is a compression molding method. The compression molding method is a molding method in which a metered molding material is placed in a concave portion (cavity) of a heated mold and pressed by a compression molding machine to harden it. The resin thickness limit on the semiconductor wafer during compression molding was 100 μm. Moreover, the limitation of the filling property by the resin thickness on the semiconductor wafer is also caused by the resin filling method, and the limit is 220 to 230 μm in the inexpensive manufacturing method, that is, the transfer molding. Therefore, it is difficult to achieve further thinning in the prior construction.

An object of one embodiment of the present invention is to provide a laminated semiconductor device which is easy to manufacture and thin.

According to an embodiment of the present invention, a laminate comprising: a plurality of semiconductor wafers; a support layer laminated on a semiconductor wafer of an uppermost layer of the laminate; and a resin for one of the supports The main surface is entirely exposed, and the laminated body is sealed so as to surround the side surface adjacent to the main surface.

1‧‧‧ Wafer laminate

1a‧‧‧Semiconductor wafer

1b‧‧‧Semiconductor wafer

1c‧‧‧Semiconductor wafer

1d‧‧‧Semiconductor wafer

1e‧‧‧Semiconductor wafer

1f‧‧‧Semiconductor wafer

1g‧‧‧Semiconductor wafer

1h‧‧‧Semiconductor wafer

1E‧‧‧矽through electrode

2‧‧‧Binder

2P‧‧‧Next resin pattern (photosensitive adhesive)

3‧‧‧Bump electrode

5‧‧‧Rewiring

5a‧‧‧Insulation film

5b‧‧‧Wiring layer

5c‧‧‧Protective film

10‧‧‧Wiring substrate

11‧‧‧Resin substrate

11A‧‧‧1st

11B‧‧‧2nd

12‧‧‧External connection terminal

13‧‧‧Internal connection terminals

20‧‧‧Support

20A‧‧‧Main surface

20S‧‧‧ side

21‧‧‧Binder

23‧‧‧film adhesive

25‧‧ ‧ step

26‧‧‧Support substrate

26A‧‧‧Main surface

26S‧‧‧ side

30‧‧‧ Sealing resin

31‧‧‧ sealing resin

40‧‧‧bonding line

H‧‧‧through hole

P‧‧‧electrode pad

P1‧‧‧electrode pad

BA‧‧‧ joint area

F1‧‧‧ side

M‧‧‧ mark

Fig. 1 is a view schematically showing the configuration of a semiconductor device according to a first embodiment, wherein (a) is a cross-sectional view, (b) is a plan view, and (c) is an enlarged cross-sectional view of a main portion.

2 is a cross-sectional view showing a step of manufacturing a semiconductor device according to the first embodiment, and (a) to (c) are diagrams showing respective steps.

3 is a cross-sectional view showing the steps of manufacturing a semiconductor device according to the first embodiment, and (a) to (c) are diagrams showing the steps subsequent to FIG. 2(c).

4 is a cross-sectional view showing a step of manufacturing a semiconductor device according to the first embodiment, and (a) to (b) are views showing steps subsequent to FIG. 3(c).

Fig. 5 is a view schematically showing the configuration of a semiconductor device according to a second embodiment, wherein (a) is a cross-sectional view and (b) is a plan view.

Fig. 6 is a view schematically showing the configuration of a semiconductor device according to a third embodiment, wherein (a) is a cross-sectional view and (b) is a plan view.

Fig. 7 is a view schematically showing the configuration of a semiconductor device according to a fourth embodiment, wherein (a) is a cross-sectional view and (b) is a plan view.

Fig. 8 is a cross-sectional view showing the steps of manufacturing a semiconductor device according to a fourth embodiment, and (a) to (d) are diagrams showing respective steps.

Fig. 9 is a view schematically showing the configuration of a semiconductor device according to a fifth embodiment, and (a) is a cross-sectional view In the plan view, (b) is a plan view, and (c) is a main part enlarged cross-sectional view.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the embodiment will be described in detail with reference to the accompanying drawings. This embodiment is a semiconductor device in which a plate-shaped material (such as a crucible, a resin sheet, a metal piece, a bonding material, or the like) is laminated on the semiconductor wafer of the uppermost layer in a state in which the bonding wires (wires) or embedded are avoided. The resin is sealed in such a manner that the plate-like material is exposed from the surface of the semiconductor device. Furthermore, in the present embodiment, a memory chip using a non-volatile memory such as a NAND flash memory as a semiconductor memory device of a semiconductor wafer will be described. However, the present invention is not limited to the embodiments. invention. Further, in the drawings shown below, in order to facilitate understanding, there is a case where the scale of each member is different from the actual one.

(First embodiment)

1(a) and 1(b) are a cross-sectional view and a plan view schematically showing a semiconductor device according to a first embodiment. Fig. 1 (c) is an enlarged cross-sectional view showing a main part of a wiring board of the same semiconductor device. The semiconductor device of the present embodiment includes a wiring substrate 10, a wafer laminate 1 in which eight semiconductor wafers 1a to 1h are sequentially laminated on the wiring substrate 10, and a support 20 laminated on the wafer laminate 1. The uppermost semiconductor wafer 1h; and the sealing resin 30. The sealing resin 30 seals the wafer laminate 1 so as to expose the entire main surface 20A of the support 20 and surround the four side faces 20S adjacent to the main surface 20A. The support 20 is smaller than the size of the sealing resin 30. Further, the support 20 covers at least one side other than the side F1 where the bonding region BA of the semiconductor wafer 1h of the uppermost layer is bonded. Moreover, the size of the wiring substrate 10 is the same as that of the sealing resin 30.

The support 20 has a metal plate having a mark M of 30 μm formed thereon, and is attached to the uppermost semiconductor wafer 1h by the adhesive 21 . The film thickness of the support 20 is preferably determined so as not to cause warpage according to the physical properties of the wafer laminate 1. The adhesive 21 may be any of a liquid material and a film material, and the thickness is preferably 60 μm or less. Furthermore, by forming the mark M with copper foil or the like in advance, it is possible to avoid the electric power generated by the thinning of the resin on the wafer. Damage to the road.

As shown in FIG. 1(c), the wiring board 10 includes a resin substrate 11 having a through hole h, and an external connection terminal 12 is formed on the first surface 11A of the resin substrate 11. When the semiconductor device is packaged and used as a BGA (Ball Grid Array), the external connection terminal 12 is provided with bump terminals such as solder balls, solder plating, and Au plating. When the semiconductor memory device is used as an LGA (Land Grid Array) package, a metal land is provided as the external connection terminal 12. The internal connection terminal 13 is provided on the second surface 11B of the resin substrate 11, and is connected to the electrode pad p1 of the semiconductor wafer 1a constituting the lowermost layer of the wafer laminate 1 via the bonding wires 40. The internal connection terminal 13 functions as a connection portion (connection pad) when connected to the wafer laminate 1 and is electrically connected to the external connection terminal 12 via a wiring net (not shown) including a through hole of the wiring substrate 10. Sexual connection.

On the second surface 11B of the resin substrate 11, the wafer laminate 1 having a plurality of semiconductor wafers 1a to 1h is sequentially fixed via the adhesive 2. Each of the semiconductor wafers 1a to 1h leaves the bonding region BA in which the electrode pads p1 are formed, and the layers are sequentially shifted. In this example, the semiconductor wafers 1a to 1h are staggered in the opposite direction to the folded portion.

Moreover, not only the semiconductor wafers 1a to 1h but also the bonding wires 40 are electrically connected to each other between the wiring substrate 10 and the lowermost semiconductor wafer 1a. The electrode pads p1 are also provided in the semiconductor wafers 1b to 1h of the second layer or more, and the semiconductor wafers 1a to 1h are electrically connected to each other by wire bonding between the electrode pads p1. Furthermore, in FIG. 1(b), the electrode pad p1 is omitted.

Further, the wiring substrate 10 and the support 20 are provided with a sealing resin for sealing the wafer laminate 1 so as to expose the entire main surface 20A of the support 20 and surround the four side faces 20S adjacent to the main surface 20A. 30.

According to this configuration, since the sealing resin 30 is formed so as to expose the main surface 20A of the support 20 and to cover the periphery with the sealing resin, the resin thickness on the wafer can be eliminated, and the resin package can be made thinner. Moreover, by adjusting the physical properties of the constituent materials of the support 20 The warpage of the semiconductor package is also easy. Further, even in the case of resin sealing, it is necessary to consider that the area of the resin on the wafer is extremely small, so that a thin semiconductor package can be realized by a more inexpensive resin sealing method, that is, a transfer method, without using a compression method.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. 2(a) to 2(c), Figs. 3(a) to 3(c), and Figs. 4(a) to 4(b) are cross-sectional views showing the steps of manufacturing the semiconductor device. First, as the wiring substrate 10, a through hole h is formed in the heat-resistant resin substrate 11 such as a glass epoxy substrate, and a wiring mesh is formed on the front and back surfaces on the first and second faces 11A and 11B. At this time, the electrode pad 13 is formed on the second surface 11B.

At a specific position on the wiring board 10, the semiconductor wafer 1a which is the first layer of the laminated body is bonded to the adhesive 2 . The semiconductor wafer 1a of the first layer is mounted on the second surface 11B of the wiring substrate 10 in a plurality of rows at a predetermined interval (Fig. 2(a)). In fact, a pattern of copper foil or the like is formed on the wiring substrate 10 in advance, and a semiconductor wafer is mounted as a mark. This pattern can also be used when cutting.

Thereafter, a specific number of semiconductor wafers (1b to 1d) are sequentially stacked on each of the semiconductor wafers 1a. At this time, the semiconductor wafers 1a to 1d are sequentially arranged in a staggered manner so as to avoid the joint regions BA for connecting them. Further, on the back surface side of the electrode pad p1 side of the laminated semiconductor wafers 1a to 1d, the adhesive 2 is formed on a portion other than the bonding region BA for electrical connection, and the semiconductor wafers 1a to 1d are laminated. The surface corresponding to the semiconductor wafer on the other side is then fixed (Fig. 2(b)).

Thereafter, the semiconductor wafers 1a to 1d are sequentially bonded between the wiring substrate 10 and the lowermost semiconductor wafer 1a, and are electrically connected by the bonding wires 40 (Fig. 2(c)). The electrode pads p1 are also provided on the semiconductor wafers 1a to 1d of the second layer or more, and the semiconductor wafers 1a to 1d are electrically connected to each other by wire bonding between the electrode pads p1.

Thereafter, a semiconductor wafer (1e to 1h) having a predetermined number of layers shifted in the opposite direction on the semiconductor wafer 1d is sequentially laminated to form each wafer laminate 1. At this time, the semiconductor crystal The sheets 1e to 1h are arranged in such a manner as to avoid the joint regions BA between the two layers so as to be shifted from the lower layer in the reverse direction. Further, on the back surface side of the electrode pad p1 on the laminated semiconductor wafers 1e to 1h, the adhesive 2 is formed on a portion other than the bonding region BA for electrical connection, and the semiconductor wafer 1e to 1h is laminated. The surface corresponding to the semiconductor wafer on the other side is then fixed (Fig. 3(a)).

Thereafter, the semiconductor wafers 1e to 1h are sequentially bonded between the wiring substrate 10 and the lowermost semiconductor wafer 1a, and are electrically connected by the bonding wires 40 (Fig. 3(b)). The electrode pads p1 are also provided on the semiconductor wafers 1e to 1h of the fifth layer or more, and the semiconductor wafers 1e to 1h are electrically connected to each other by wire bonding between the electrode pads p1.

Next, a member in which the mark M (see FIG. 1(b)) is formed on the surface of the metal plate is prepared as the support 20. Then, the support 20 on which the adhesive 21 is formed is fixed to the uppermost memory chip (semiconductor wafer 1h) of the wafer laminate 1 (Fig. 3(c)).

Then, the wiring board 10 is placed in a mold (not shown) provided with a cavity, and the sealing resin 30 is formed by transfer molding using an epoxy resin (Fig. 4(a)). At this time, by providing the main surface 20A of the support 20 in close contact with the bottom surface of the cavity of the mold, the sealing resin 30 can be formed so as to surround the side surface 20S with almost no resin bypass on the main surface 20A.

Then, the wiring substrate 10 after the transfer molding is attached to a dicing tape (not shown). On the side of the support 20, the alignment is performed on the basis of the identification mark formed on the wiring board 10 in advance, and the wiring board 10 is cut by the blade cutting method using a blade to perform singulation (Fig. 4(b)). The method of cutting is not limited to the method of cutting by a blade, and the method of using a mold, the method of using a cutter, or the like may be used. A shape in which a slit or the like is provided may be prepared in advance at a specific position of the wiring substrate 10, and may be cut at this position.

When the blade is cut at this time, the wiring board 10 is attached to the dicing tape in advance so as not to be dispersed. By cutting the sealing resin 30 and the wiring board 10 at the same time, it is possible to obtain a structure in which the size is minimized and the cut surface is uniform. Then, self-cut The dicing tape is sewn into a single-layer laminated semiconductor device by a chuck (not shown) or the like, and is peeled off from the dicing tape. The semiconductor device shown in FIGS. 1(a) to 1(c) is thus completed.

According to the above method, a metal plate is used for the support 20. Further, on the semiconductor wafer 1h constituting the uppermost layer of the wafer laminate 1, the bonding wire 40 is adhered to the bonding wire 40, and the support 20 is attached via the adhesive 21, and is exposed from the surface of the sealing resin 30. Therefore, a thin structure in which the sealing resin 30 is not present can be easily formed on the support 20, and the resin sealing can be performed extremely efficiently and easily by a cheaper resin sealing method, that is, transfer molding.

Further, in the semiconductor device of the present embodiment, the support 20 is not smaller than the size of the sealing resin 30, and covers at least one side of the semiconductor wafer, the semiconductor wafer, the wiring substrate 10, and the like by the bonding wire 40. The configuration can be.

Further, in the semiconductor device of the present embodiment, the support 20 is not limited to a metal plate, and any form such as tantalum, a metal, a resin sheet, or a semi-hardened resin may be used. Moreover, the adhesive 21 which fixes the support body 20 to the uppermost semiconductor wafer 1h can be either a liquid material or a film material. The thickness of the subsequent agent 21 is preferably 60 μm or less. The reason for this is that if the thickness of the adhesive 21 exceeds 60 μm, the thickness of the laminated semiconductor device becomes large. Further, the total thickness of the adhesive 21 and the support 20 is preferably 200 μm or less. This is the lower limit of the resin thickness on the wafer in the case where the resin is sealed by transfer molding, and as described in the present embodiment, the thickness can be completed in order to eliminate the resin thickness on the wafer.

Further, the resin thickness on the wafer can be eliminated in most areas, and the thickness of the semiconductor package can be reduced, and the warpage of the semiconductor device can be easily controlled by adjusting the physical properties of the plate material.

(Second embodiment)

5(a) and 5(b) are a cross-sectional view and a plan view schematically showing a configuration of a semiconductor device according to a second embodiment. The semiconductor device-based support 20 of the present embodiment is larger than the wafer size. The support 20 is disposed so as to cover the uppermost semiconductor wafer 1h. The bonding wires 40 connected to the uppermost semiconductor wafer 1h are buried in the adhesive 21. In addition to this point, Both of them are formed in the same manner as the semiconductor device of the first embodiment. In the present embodiment, it is necessary to use the insulator 21 as the adhesive.

In the present embodiment, the bonding wire 40 is buried in the adhesive 21 and protected by the support 20, so that electrical connection is ensured and reliability is improved. Further, since the bonding wire 40 is protected by the adhesive 21, the thickness of the support 20 can be reduced, and the thickness of the entire sealing resin 30 can be substantially reduced.

(Third embodiment)

6(a) and 6(b) are a cross-sectional view and a plan view schematically showing a configuration of a semiconductor device according to a third embodiment. The semiconductor device of the present embodiment is formed by replacing the semiconductor wafer 1h of the uppermost layer with the film adhesive 23 larger than the wafer size instead of the support 20 and the adhesive 21 using the metal plate used in the second embodiment. Configuration. The bonding wires 40 connected to the uppermost semiconductor wafer 1h are buried in the film adhesive 23, thereby hardening the film adhesive 23. Except for this point, it is the same as the semiconductor device of the above-described second embodiment. In the present embodiment, it is also necessary to use a film adhesive 23 as a film having a higher insulating property.

In the present embodiment, the bonding wire 40 is buried in the adhesive 23 and protected by the cured film adhesive 23, the electrical connection is ensured, and the reliability is improved. Moreover, since the bonding wire 40 is protected by only one layer of the film adhesive 23, the thickness of the entire sealing resin 30 can be substantially reduced. Further, before the transfer molding step of forming the sealing resin 30, since the bonding wire 40 of the uppermost layer which is more susceptible to the flow resistance of the transfer molding resin is fixed, the manufacturing yield of the resin sealing step is improved.

(Fourth embodiment)

7(a) and 7(b) are a cross-sectional view and a plan view schematically showing a configuration of a semiconductor device according to a fourth embodiment. The semiconductor device of the present embodiment includes a support substrate 26 instead of the support 20 using a metal plate used in the second embodiment. In the support substrate 26, a tantalum substrate which is cut to be larger than the wafer size and has a step 25 of about 3 μm in the peripheral portion is used. Except for this point, it is the same as the laminated semiconductor device of the above-described second embodiment. In this example, the support substrate 26 is also disposed so as to cover the uppermost semiconductor wafer 1h. The bonding agent 21 is hardened in a state in which the bonding wires 40 connected to the uppermost semiconductor wafer 1h are buried in the adhesive 21 for connecting the supporting substrates 26.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. 8(a) to 8(d) are cross-sectional views showing the steps of the manufacturing steps of the semiconductor device. The manufacturing steps of the multilayer semiconductor device according to the first embodiment shown in FIGS. 2(a) to 4(b) are substantially the same, but in the present embodiment, the support substrate 26 is first prepared.

As shown in FIG. 8(a), a germanium substrate which is a material for forming the support substrate 26 is prepared. Then, as shown in FIG. 8(b), a step 25 is formed on the peripheral portion of the support substrate 26 by photolithography.

Then, by the steps of FIGS. 2(a) to 3(b) of the first embodiment, a predetermined number of semiconductor wafers (1b to 1h) and a support substrate 26 are sequentially stacked on each semiconductor wafer 1a, and borrowed. It is electrically connected by the bonding wires 40 (Fig. 8(c)). Here, the electrode pads p1 are also provided on the semiconductor wafers 1b to 1h of the second layer or more, and the semiconductor wafers 1a to 1h are electrically connected to each other by wire bonding between the electrode pads p1. Further, the support substrate 26 is fixed to the uppermost semiconductor wafer 1h by the adhesive 21 .

Then, the wiring board 10 is placed in a mold (not shown) provided with a cavity, and the sealing resin 30 is formed by transfer molding using an epoxy resin (Fig. 8(d)). At this time, by providing the main surface 26A of the support substrate 26 in close contact with the bottom surface of the cavity of the mold, the sealing resin 30 can be formed so as to surround the side surface 26S with almost no bypass of the resin on the main surface 26A. Since the step 25 is provided on the peripheral portion of the support substrate 26 in this example, the filler material contained in the resin is hooked on the step 25 in the transfer molding, and the immersion of the molten resin becomes slow due to the intercepting effect. Thereby, resin leakage to the main surface 26A of the support substrate 26 can be reduced. Therefore, it is possible to minimize the resin burr and obtain a laminated semiconductor device having a good appearance.

Further, the step may be any shape or a tapered surface, but the step is preferably set to 30 μm or less. The reason is that if it exceeds 30 μm, the effect of the flow of the molten resin is slowed down. Will be weak.

(Fifth Embodiment)

9(a) and 9(b) are a cross-sectional view and a plan view schematically showing a configuration of a semiconductor device according to a fifth embodiment. Fig. 9(c) is an enlarged cross-sectional view showing the main part. In the first to fourth embodiments, an example in which the semiconductor wafers are electrically connected to each other by wire bonding and the bonding regions BA are stacked and laminated is described. However, the semiconductor device of the present embodiment uses a through electrode. Then, the through-wafer connection (TSV, Through Silicon Via) is performed by flip-chip bonding, and the semiconductor wafer is laminated without being largely staggered, and further downsizing and thinning can be achieved.

The semiconductor device of the present embodiment is disposed to face the wiring substrate 10, and a support 20 of a metal plate having the same size as the semiconductor wafer 1 is used. The wafer laminate 1 having the plurality of semiconductor wafers 1a to 1h is connected to each other by flip chip bonding. As shown in the enlarged cross-sectional view of the main portion of FIG. 9(c), the plurality of semiconductor wafers 1a to 1h are electrically connected to each other by the through electrode 1E having the electrode pad p and the surface of each of the semiconductor wafers 1a to 1h. The wiring 5 and the bump electrode 3 connected to the rewiring 5 are realized. On the other hand, the physical connection is realized by the pattern of the photosensitive adhesive 2P. The rewiring 5 includes an insulating film 5a, a wiring layer 5b connected to an opening formed in the insulating film 5a, and a protective film 5c that protects the wiring layer 5b. Therefore, the electrical and physical connections can be completed by stacking the layers in a good bonding line. Further, in this example, the physical connection between the semiconductor wafers 1a to 1h is realized by the pattern of the photosensitive adhesive 2P, and the sealing resin 31 using the liquid resin is filled between the layers after lamination. Then, the outer side of the sealing resin 30 is further covered by transfer molding.

Therefore, in the semiconductor device of the present embodiment, the wafer laminate 1 and the support 20 are laminated on the wiring substrate 10, and the sealing resin 30 is sealed in a state where electrical and physical connection is completed. The sealing resin 30 is formed so as to expose the main surface of the support surface 20 and surround the four side faces 20S adjacent to the main surface 20A, and seal the support 20 and the wiring substrate 10 therebetween. The semiconductor wafer 1a to 1h constituting the wafer laminate 1 and the support 20, the wiring substrate 10, and the wafer laminate 1 are interposed. The outer edge of the sealing resin 30 perpendicularly intersects the outer edge of the wiring substrate 10.

In the present embodiment, a resin substrate or the like which is easily cut is used as the support 20, and a laminate of the semiconductor wafers 1a to 1h is laminated on the wiring substrate 10. A liquid resin is supplied between the patterns 2P of the resin. Thereafter, the support 20 is laminated on the uppermost semiconductor wafer 1h. In this manner, the semiconductor wafers 1a to 1h and the wafer laminate 1 and the wiring substrate 10 are resin-sealed, and then cut by a dicing blade to be singulated.

The wiring substrate 10 is a resin substrate 11, and the second surface 11B of the resin substrate 11 is provided with an internal connection terminal 13 which is connected to the electrode pad of the lowermost semiconductor wafer 1a. The internal connection terminal 13 functions as a connection portion (connection pad) when connected to the wafer laminate 1 and is electrically connected to the external connection terminal 12 via a wiring net (not shown) of the wiring substrate 10.

In addition, in the fifth embodiment, the support member 20 is not limited to the metal plate, and an insulating substrate such as a resin or a semiconductor substrate such as a tantalum substrate may be used. Further, as shown in the fourth embodiment, the step 25 may be provided on the peripheral portion of the support body 20. Further, the germanium substrate having the germanium through electrode may be used as a support, and may be connected to the uppermost semiconductor wafer 1h, and external connection terminals such as BGA or LGA may be connected to the germanium substrate, even on the side of the support 20 The external removal of the signal is still possible.

Further, in the first to fifth embodiments, since the semiconductor wafer constituting the wafer laminate is thin, the resin is used as the support 20 and the support substrate from the viewpoint of erroneous operation due to the bypass of the light from the back surface. In the case of 26, it is preferred to use a light-shielding resin.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be carried out in various other forms, and various omissions, substitutions and changes can be made without departing from the spirit of the invention. more. Such embodiments and variations thereof are included within the scope of the invention and the scope of the invention as disclosed in the appended claims.

1‧‧‧ Wafer laminate

1a‧‧‧Semiconductor wafer

1b‧‧‧Semiconductor wafer

1c‧‧‧Semiconductor wafer

1d‧‧‧Semiconductor wafer

1e‧‧‧Semiconductor wafer

1f‧‧‧Semiconductor wafer

1g‧‧‧Semiconductor wafer

1h‧‧‧Semiconductor wafer

2‧‧‧Binder

10‧‧‧Wiring substrate

11‧‧‧Resin substrate

11A‧‧‧1st

11B‧‧‧2nd

12‧‧‧External connection terminal

13‧‧‧Internal connection terminals

20‧‧‧Support

20A‧‧‧Main surface

20S‧‧‧ side

21‧‧‧Binder

30‧‧‧ Sealing resin

40‧‧‧bonding line

H‧‧‧through hole

P1‧‧‧electrode pad

BA‧‧‧ joint area

F1‧‧‧ side

M‧‧‧ mark

Claims (9)

A semiconductor device comprising: a laminate body in which a plurality of semiconductor wafers are sequentially laminated; a support layer laminated on a semiconductor wafer of an uppermost layer of the laminate; and a resin for causing the support body a main surface is exposed and surrounding the side surface adjacent to the main surface to seal the laminated body; and the supporting system has a step on the end surface of the main surface side, and is smaller than the size of the resin, and is covered to form a wire bonding At least one side other than the side of the bonding region of the semiconductor wafer of the uppermost layer. A semiconductor device comprising: a laminate body in which a plurality of semiconductor wafers are sequentially laminated; a support layer laminated on a semiconductor wafer of an uppermost layer of the laminate; and a resin to be one of the support bodies The surface is exposed and the laminated body is sealed so as to surround the side surface adjacent to the main surface. The semiconductor device according to claim 2, wherein the support is smaller than the size of the resin, and is disposed so as to cover at least one side other than a side of a bonding region of the semiconductor wafer for bonding the uppermost layer. The semiconductor device according to claim 2, wherein the support is smaller than the size of the resin, and is laminated on the uppermost layer with the adhesive by laminating the four sides of the semiconductor wafer of the uppermost layer via an adhesive. A wire of a junction region of the above semiconductor wafer. The semiconductor device of claim 2, wherein said support system film adhesive is larger than said semiconductor wafer and buried in said uppermost layer of said semiconductor layer The wires of the bonding region of the bulk wafer are laminated so as to cover the four sides of the semiconductor wafer of the uppermost layer. The semiconductor device of claim 2, wherein the support system has a step on an end surface of the main surface side. The semiconductor device according to any one of claims 2 to 4, wherein the support has a metal substrate and an adhesive. The semiconductor device according to any one of claims 2 to 4, wherein the support has an insulating substrate and an adhesive. A method of fabricating a semiconductor device by laminating a plurality of semiconductor wafers on a substrate; laminating a support on the semiconductor wafer of an uppermost layer of the plurality of stacked semiconductor wafers; and exposing a main surface of the support And sealing the laminated body resin so as to surround the side surface adjacent to the main surface.