JP2010232471A - Method for producing semiconductor device, and semiconductor device - Google Patents

Method for producing semiconductor device, and semiconductor device Download PDF

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JP2010232471A
JP2010232471A JP2009079134A JP2009079134A JP2010232471A JP 2010232471 A JP2010232471 A JP 2010232471A JP 2009079134 A JP2009079134 A JP 2009079134A JP 2009079134 A JP2009079134 A JP 2009079134A JP 2010232471 A JP2010232471 A JP 2010232471A
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semiconductor device
manufacturing
semiconductor
substrate
resin
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Takehiko Maeda
武彦 前田
Yuko Sato
祐子 佐藤
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent burrs from being formed in cutting a structure including a heat dissipation plate, by a simple procedure. <P>SOLUTION: A package structure 110 before cutting includes a substrate 102 and a heat spreaders 106 disposed on the substrate. The heat spreaders are each formed with through holes 106a at the intersections of cutting lines 108b extending in an X direction and a cutting lines 108a extending in a Y direction, the through holes being filled with a low ductility material 104 having a lower ductility than that of the material of which the heat spreader is comprised. Such package structure before cutting is cut along each of the cutting line extending in an X direction and the cutting line extending in a Y direction to be diced into a plurality of semiconductor devices. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置の製造方法および半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

特許文献１（特開２００３−２４９５１２号公報）には、（ａ）複数の放熱体が一体化してなる集合体を、型の凹部にセットし、（ｂ）複数の半導体チップが平面的に並べて搭載されてなる基板を、複数の半導体チップを凹部内に配置するように型にセットし、（ｃ）凹部に封止材を充填することで、複数の半導体チップを封止するとともに、集合体を取り付けることを含む半導体装置の製造方法が記載されている。この後、この構造体を切断して個片化する。   In Patent Document 1 (Japanese Patent Laid-Open No. 2003-249512), (a) an assembly formed by integrating a plurality of heat dissipating bodies is set in a recess of a mold, and (b) a plurality of semiconductor chips are arranged in a plane. The mounted substrate is set in a mold so that a plurality of semiconductor chips are arranged in the recesses, and (c) the recesses are filled with a sealing material, thereby sealing the plurality of semiconductor chips and collecting the assembly. A method of manufacturing a semiconductor device including mounting is described. Thereafter, the structure is cut into pieces.

しかし、通常、放熱板は、銅等の延性が高い金属材料により構成されており、切断時に材料が延びてバリが発生するという問題があった。このようなバリが発生すると、実装時にバリが脱落し、実装不良の原因となる。   However, the heat radiating plate is usually made of a metal material having high ductility such as copper, and there is a problem in that the material extends during cutting and burrs are generated. When such a burr | flash generate | occur | produces, a burr | flash will fall | omit at the time of mounting, and will cause a mounting defect.

特許文献２（特開２００６−４１２６１号公報）には、フィルム上に複数のベアチップがパッケージ化された被加工物を、高速回転する切削ブレードによってフィルム側の面から切削加工して、少なくともフィルム部分を複数のチップに分割した後に、各チップのコーナー部分に生じたバリを除去するバリ除去方法が記載されている。当該方法において、切削ブレードと被加工物との対向位置で切削ブレードの回転方向と逆方向に被加工物を切削ブレードに対して相対移動させて、切削加工によって形成された切削溝を切削ブレードによってなぞることによって、コーナー部分に生じたバリを、なぞられた切削溝に対して直交する他の切削溝に逃がさないように、切削ブレードと各チップとの間に挟み込んで除去している。   In Patent Document 2 (Japanese Patent Laid-Open No. 2006-41261), a workpiece in which a plurality of bare chips are packaged on a film is cut from a surface on the film side by a cutting blade that rotates at high speed, and at least a film portion is obtained. Describes a method of removing burrs in which burrs generated at the corners of each chip are removed after the chip is divided into a plurality of chips. In this method, the workpiece is moved relative to the cutting blade in a direction opposite to the rotation direction of the cutting blade at a position where the cutting blade and the workpiece are opposed to each other, and a cutting groove formed by the cutting is formed by the cutting blade. By tracing, the burrs generated at the corner portions are removed by being sandwiched between the cutting blade and each chip so as not to escape to other cutting grooves orthogonal to the traced cutting grooves.

特許文献３（特開２００１−２６７４７８号公報）には、ヒートスプレッダとなる金属板の片面に上溝を設ける工程、該金属板に配線層を有する基板を接着するとともに上記の上溝に樹脂を充填する工程、金属板の別の面に下溝を設けて上下の溝を連結する工程を少なくとも有する半導体装置の製造方法が記載されている。   Patent Document 3 (Japanese Patent Laid-Open No. 2001-267478) discloses a step of providing an upper groove on one surface of a metal plate serving as a heat spreader, a step of adhering a substrate having a wiring layer to the metal plate and filling the upper groove with a resin. A method of manufacturing a semiconductor device having at least a step of providing a lower groove on another surface of a metal plate and connecting upper and lower grooves is described.

特許文献４（特開２０００−７７５７５号公報）には、ダイ上に、接地パッドに接続される支持部を有する放熱体（ヒートスプレッダ）が配置されたパッケージが記載されている。ここで、ヒートスプレッダは、平面視でダイと重なる中央部で膜厚が厚くなっている。   Patent Document 4 (Japanese Patent Application Laid-Open No. 2000-77575) describes a package in which a radiator (heat spreader) having a support portion connected to a ground pad is arranged on a die. Here, the heat spreader has a thick film thickness at the central portion overlapping the die in plan view.

特開２００３−２４９５１２号公報JP 2003-249512 A 特開２００６−４１２６１号公報JP 2006-41261 A 特開２００１−２６７４７８号公報JP 2001-267478 A 特開２０００−７７５７５号公報JP 2000-77575 A

しかし、特許文献２に記載の技術でも、完全にバリを除くのは困難だった。特許文献１や特許文献２に記載された技術において、バリの発生を防ぐのが困難であることを図２４を参照して説明する。図２４は、ヒートスプレッダ６の構成を示す平面図である。まず、ヒートスプレッダ６をダイシングライン８ａに沿って、第１の方向（図中上から下方向）に切断する（図２４（ａ））。次いで、ヒートスプレッダ６をダイシングライン８ｂに沿って、第１の方向と直交する第２の方向（図中左から右方向）に切断する（図２４（ｂ））。このとき、ダイシングライン８ａ上では、既にヒートスプレッダ６が切断・除去されている。そのため、ヒートスプレッダ６をダイシングライン８ｂに沿って横方向に切断する際に生じたバリ１０が、ダイシングライン８ａ上に残ってしまう。このような構成となった場合に、特許文献２に記載された技術のように、再度ダイシングライン８ａに沿って、第１の方向と反対側の方向（図中下から上方向）にブレードでなぞっても、バリ１０がダイシングライン８ｂ上に移動するだけで、一旦発生したバリ１０を完全に除去するのは困難である（図２４（ｃ））。   However, even with the technique described in Patent Document 2, it has been difficult to completely remove burrs. With reference to FIG. 24, it will be described that it is difficult to prevent the occurrence of burrs in the techniques described in Patent Document 1 and Patent Document 2. FIG. 24 is a plan view showing the configuration of the heat spreader 6. First, the heat spreader 6 is cut along the dicing line 8a in a first direction (from the top to the bottom in the figure) (FIG. 24A). Next, the heat spreader 6 is cut along a dicing line 8b in a second direction (left to right in the drawing) perpendicular to the first direction (FIG. 24B). At this time, the heat spreader 6 has already been cut and removed on the dicing line 8a. Therefore, burrs 10 generated when the heat spreader 6 is cut in the lateral direction along the dicing line 8b remain on the dicing line 8a. In such a configuration, as in the technique described in Patent Document 2, the blade is again moved along the dicing line 8a in the direction opposite to the first direction (from the bottom to the top in the figure). Even if it is traced, it is difficult to completely remove the burrs 10 once generated by merely moving the burrs 10 onto the dicing line 8b (FIG. 24C).

本発明によれば、
基板と、
前記基板の一面上に配置され、Ｘ方向のＸ方向切断ラインおよび前記Ｘ方向と交差するＹ方向のＹ方向切断ラインの交点にそれぞれ貫通孔が形成された放熱板であって、当該貫通孔が当該放熱板を構成する材料よりも延性の低い低延性材料で埋め込まれている放熱板と、
を含む構造体を、前記Ｘ方向切断ラインおよび前記Ｙ方向切断ラインにそれぞれ沿って切断し、複数の半導体装置に個片化する工程を含む半導体装置の製造方法が提供される。 According to the present invention,
A substrate,
A heat radiating plate disposed on one surface of the substrate and having a through hole formed at an intersection of an X direction cutting line in the X direction and a Y direction cutting line in the Y direction intersecting the X direction, A heat sink embedded with a low ductility material having a lower ductility than the material constituting the heat sink;
Is cut along each of the X-direction cutting line and the Y-direction cutting line, and a method for manufacturing a semiconductor device is provided.

本発明によれば、
基板と、
前記基板に形成された半導体素子と、
前記基板の一面を覆うように配置された放熱板と、
を含み、
前記放熱板は四隅が除かれ、前記四隅には、当該放熱板を構成する材料よりも延性の低い低延性材料が形成されている半導体装置が提供される。 According to the present invention,
A substrate,
A semiconductor element formed on the substrate;
A heat sink arranged to cover one surface of the substrate;
Including
The heat sink is provided with a semiconductor device in which four corners are removed and a low ductility material having a lower ductility than a material constituting the heat sink is formed at the four corners.

放熱板が銅等の延性の高い材料で構成されている場合、構造体を切断用ブレードで切断する際に当該材料が延びてバリが発生してしまう。しかし、本発明の構成によれば、切断ラインの交点に放熱板を構成する材料よりも延性の低い材料が充填されているため、放熱板を構成する材料の延びを抑えることができ、バリの発生を抑えることができる。これにより、実装不良を防ぐことができる。   When the heat sink is made of a highly ductile material such as copper, when the structure is cut with a cutting blade, the material extends to generate burrs. However, according to the configuration of the present invention, since the intersection of the cutting lines is filled with a material having a lower ductility than the material constituting the heat sink, the extension of the material constituting the heat sink can be suppressed. Occurrence can be suppressed. Thereby, mounting failure can be prevented.

ここで、切断ラインの交点に何も形成されていないと、放熱板を構成する材料の延びを抑えることはできない。そのため、たとえば特許文献２に記載されたように、発生したバリを除去しようとしても、たとえばＸ方向切断ラインに沿って除去作業を行った場合は、上述したように、バリがＹ方向切断ラインの方向に変形し、逆にＹ方向切断ラインに沿って除去作業を行った場合には、バリがＸ方向切断ラインの方向に変形してしまい、一旦バリが発生してしまうと、これを完全に除くのは困難である。本発明の構成によれば、バリの発生自体を防ぐことができるため、簡易な手順で、実装不良を防ぐことができる。   Here, if nothing is formed at the intersection of the cutting lines, the extension of the material constituting the heat sink cannot be suppressed. Therefore, for example, as described in Patent Document 2, even if an attempt is made to remove the generated burr, for example, when the removal operation is performed along the X-direction cutting line, the burr is formed on the Y-direction cutting line as described above. When the removal operation is performed along the Y direction cutting line, the burr is deformed in the direction of the X direction cutting line, and once the burr is generated, this is completely removed. It is difficult to remove. According to the configuration of the present invention, since the occurrence of burrs can be prevented, mounting defects can be prevented with a simple procedure.

なお、以上の構成要素の任意の組合せ、本発明の表現を方法、装置などの間で変換したものもまた、本発明の態様として有効である。   It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, and the like are also effective as an aspect of the present invention.

本発明によれば、簡易な手順で、放熱板を含む構造体を切断する際のバリの発生を防いで、実装不良を防ぐことができる。   According to the present invention, it is possible to prevent the occurrence of burrs when cutting a structure including a heat sink by a simple procedure, thereby preventing mounting defects.

本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の構成を示す平面図である。It is a top view which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態におけるヒートスプレッダの構成を示す平面図である。It is a top view which shows the structure of the heat spreader in embodiment of this invention. 本発明の実施の形態における半導体装置の製造手順を示す断面図である。It is sectional drawing which shows the manufacture procedure of the semiconductor device in embodiment of this invention. 金型から外した切断前パッケージ構造の構成を示す断面図である。It is sectional drawing which shows the structure of the package structure before cutting | disconnection removed from the metal mold | die. 金型から外した切断前パッケージ構造の構成を示す平面図である。It is a top view which shows the structure of the package structure before cutting | disconnection removed from the metal mold | die. 本発明の実施の形態におけるヒートスプレッダの構成を示す平面図である。It is a top view which shows the structure of the heat spreader in embodiment of this invention. 本発明の実施の形態における半導体装置の製造手順を示す断面図である。It is sectional drawing which shows the manufacture procedure of the semiconductor device in embodiment of this invention. 金型から外した切断前パッケージ構造の構成を示す断面図である。It is sectional drawing which shows the structure of the package structure before cutting | disconnection removed from the metal mold | die. 金型から外した切断前パッケージ構造の構成を示す平面図である。It is a top view which shows the structure of the package structure before cutting | disconnection removed from the metal mold | die. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態におけるヒートスプレッダの構成を示す平面図である。It is a top view which shows the structure of the heat spreader in embodiment of this invention. 本発明の実施の形態における半導体装置の製造手順を示す断面図である。It is sectional drawing which shows the manufacture procedure of the semiconductor device in embodiment of this invention. 金型から外した切断前パッケージ構造の構成を示す断面図である。It is sectional drawing which shows the structure of the package structure before cutting | disconnection removed from the metal mold | die. 金型から外した切断前パッケージ構造の構成を示す平面図である。It is a top view which shows the structure of the package structure before cutting | disconnection removed from the metal mold | die. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 本発明の実施の形態における切断前パッケージ構造の構成を示す断面図である。It is sectional drawing which shows the structure of the package structure before a cutting | disconnection in embodiment of this invention. 本発明の実施の形態における半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. 従来技術の問題点を説明するための図である。It is a figure for demonstrating the problem of a prior art.

以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

（第１の実施の形態）
図１は、本実施の形態における半導体装置１００の構成を示す断面図である。図２は、本実施の形態における半導体装置１００の構成を示す平面図である。図１は、図２のａ−ａ線に沿った断面構造に対応する。 (First embodiment)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 100 in the present embodiment. FIG. 2 is a plan view showing the configuration of the semiconductor device 100 according to the present embodiment. FIG. 1 corresponds to a cross-sectional structure taken along line aa in FIG.

半導体装置１００は、基板１０２と、基板１０２の一面に搭載された半導体素子１２０と、基板１０２上に形成され、半導体素子１２０を封止する封止樹脂１０４と、封止樹脂１０４上に配置されたヒートスプレッダ（放熱板）１０６とを含む。基板１０２の半導体素子１２０が搭載された一面と反対側の面には、半田ボール１２６が設けられている。また、半導体素子１２０は、ボンディングワイヤ１２２を介して基板１０２の配線と接続されている。ボンディングワイヤ１２２も封止樹脂１０４により封止されている。基板１０２は、たとえば、樹脂層と配線パターンとが積層された多層配線基板とすることができる。   The semiconductor device 100 includes a substrate 102, a semiconductor element 120 mounted on one surface of the substrate 102, a sealing resin 104 that is formed on the substrate 102 and seals the semiconductor element 120, and is disposed on the sealing resin 104. And a heat spreader (heat radiating plate) 106. A solder ball 126 is provided on the surface of the substrate 102 opposite to the surface on which the semiconductor element 120 is mounted. Further, the semiconductor element 120 is connected to the wiring of the substrate 102 through the bonding wire 122. The bonding wire 122 is also sealed with the sealing resin 104. The substrate 102 can be, for example, a multilayer wiring board in which a resin layer and a wiring pattern are laminated.

平面視において、ヒートスプレッダ１０６は、基板１０２上の四隅を除いた箇所ほぼ全面に設けられる。また、本実施の形態において、ヒートスプレッダ１０６が形成されていない四隅には、封止樹脂１０４が形成されている。封止樹脂１０４は、ヒートスプレッダ１０６を構成する材料よりも延性の低い材料とすることができる。本実施の形態において、ヒートスプレッダ１０６は、銅により構成することができる。   In plan view, the heat spreader 106 is provided on almost the entire surface of the substrate 102 except for the four corners. In the present embodiment, sealing resin 104 is formed at the four corners where the heat spreader 106 is not formed. The sealing resin 104 can be made of a material having lower ductility than the material constituting the heat spreader 106. In the present embodiment, the heat spreader 106 can be made of copper.

ここで、ヒートスプレッダ１０６の封止樹脂１０４と接する面と反対側の一面（図１中上面）とその四隅に露出した封止樹脂１０４の表面とは高さがほぼ等しく形成することができる。   Here, one surface (upper surface in FIG. 1) opposite to the surface in contact with the sealing resin 104 of the heat spreader 106 and the surface of the sealing resin 104 exposed at the four corners thereof can be formed to have substantially the same height.

次に、図３および図４を参照して、本実施の形態における半導体装置１００の製造手順を説明する。
図３は、本実施の形態におけるヒートスプレッダ１０６の構成を部分的に示す平面図である。
本実施の形態において、ヒートスプレッダ１０６には、Ｘ方向（図中横方向）のＸ方向切断ライン１０８ｂおよびＸ方向に直交するＹ方向（図中縦方向）のＹ方向切断ライン１０８ａの交点１０８にそれぞれ貫通孔１０６ａが形成されている。ここで、貫通孔１０６ａの直径は、後に切断前パッケージ構造を個片化する際のパッケージ切断用ブレードの歯の幅よりも広くなるように形成することができる。本実施の形態において、ヒートスプレッダ１０６は、平板とすることができる。ここで、たとえば、平板に形成されたヒートスプレッダ１０６の該当箇所を打ち抜く等により貫通孔１０６ａを形成することができる。また、シート状のヒートスプレッダ材料を打ち抜いて、個々のヒートスプレッダ１０６を形成する際に、同時に貫通孔１０６ａを打ち抜くこともできる。 Next, with reference to FIG. 3 and FIG. 4, the manufacturing procedure of the semiconductor device 100 in the present embodiment will be described.
FIG. 3 is a plan view partially showing the configuration of the heat spreader 106 in the present embodiment.
In the present embodiment, the heat spreader 106 has an X-direction cutting line 108b in the X direction (lateral direction in the drawing) and an intersection 108 of the Y-direction cutting line 108a in the Y direction (vertical direction in the drawing) orthogonal to the X direction. A through hole 106a is formed. Here, the diameter of the through-hole 106a can be formed so as to be wider than the width of the teeth of the package cutting blade when the package structure before cutting is separated into pieces later. In the present embodiment, the heat spreader 106 may be a flat plate. Here, for example, the through hole 106a can be formed by punching out a corresponding portion of the heat spreader 106 formed on a flat plate. Further, when the individual heat spreaders 106 are formed by punching a sheet-like heat spreader material, the through holes 106a can be punched simultaneously.

本実施の形態において、図３に示したようなヒートスプレッダ１０６を用いて、金型２００により、半導体素子１２０を封止樹脂１０４で封止する。図４（ａ）は、図３に示したヒートスプレッダ１０６のｂ−ｂ線に沿った断面構造に対応する。   In the present embodiment, the semiconductor element 120 is sealed with the sealing resin 104 by the mold 200 using the heat spreader 106 as shown in FIG. 4A corresponds to the cross-sectional structure along the line bb of the heat spreader 106 shown in FIG.

まず、基板１０２上に複数の半導体素子１２０を搭載し、ボンディングワイヤ１２２を介して基板１０２の配線と接続しておく。次いで、ワイヤボンディング済みの複数の半導体素子１２０が搭載された基板１０２を、半導体素子１２０が搭載された面が下型２０２と向かい合うようにして、金型２００の上型２０４に配置する。また、金型２００の下型２０２にヒートスプレッダ１０６を配置する。このような状態で、金型２００の導入口から封止樹脂１０４を導入する（図４（ｂ））。これにより、半導体素子１２０およびボンディングワイヤ１２２が封止樹脂１０４で封止されるとともに、ヒートスプレッダ１０６の貫通孔１０６ａ内にも封止樹脂１０４が充填される（図４（ｃ））。この時、ヒートスプレッダ１０６と下型２０２との間に、リリースフィルム（たとえば４Ｈ−４Ｆ共重合物のフィルム、不図示）を敷いておいてもよい。リリースフィルムを敷くことで、貫通孔１０６ａ内に充填された封止樹脂１０４と下型２０２とが直接接しなくなるため、金型２００からの取り外しが容易になる。   First, a plurality of semiconductor elements 120 are mounted on the substrate 102 and connected to the wiring of the substrate 102 through bonding wires 122. Next, the substrate 102 on which the plurality of wire-bonded semiconductor elements 120 are mounted is placed on the upper mold 204 of the mold 200 so that the surface on which the semiconductor elements 120 are mounted faces the lower mold 202. Further, the heat spreader 106 is disposed on the lower mold 202 of the mold 200. In such a state, the sealing resin 104 is introduced from the introduction port of the mold 200 (FIG. 4B). As a result, the semiconductor element 120 and the bonding wire 122 are sealed with the sealing resin 104, and the sealing resin 104 is also filled into the through holes 106a of the heat spreader 106 (FIG. 4C). At this time, a release film (for example, a 4H-4F copolymer film, not shown) may be laid between the heat spreader 106 and the lower mold 202. By laying the release film, the sealing resin 104 filled in the through hole 106a and the lower mold 202 are not in direct contact with each other, so that the removal from the mold 200 is facilitated.

なお、図４では、金型２００の導入口から封止樹脂１０４を導入するトランスファーモールド方式による樹脂封止を例示したが、樹脂封止は、これに限定されるものではない。たとえば、樹脂封止は、圧縮成形方式で行うこともできる。この場合も、トランスファーモールド方式と同様に、ワイヤボンディング済みの複数の半導体素子１２０が搭載された基板１０２を、半導体素子１２０が搭載された面が下型２０２と向かい合うようにして、金型２００の上型２０４に配置する。次いで、金型２００の下型２０２にヒートスプレッダ１０６を配置した状態で、封止樹脂のプリフォーム（体）をヒートスプレッダ１０６上に載置し、その後、プリフォーム（体）を加熱溶融しながら上型２０４と下型２０２とを閉じ合わせて樹脂封止する。   4 illustrates the resin sealing by the transfer mold method in which the sealing resin 104 is introduced from the inlet of the mold 200, the resin sealing is not limited to this. For example, the resin sealing can be performed by a compression molding method. Also in this case, similarly to the transfer mold method, the substrate 102 on which a plurality of wire-bonded semiconductor elements 120 are mounted is arranged so that the surface on which the semiconductor elements 120 are mounted faces the lower mold 202. Arranged in the upper mold 204. Next, in a state where the heat spreader 106 is arranged on the lower mold 202 of the mold 200, the sealing resin preform (body) is placed on the heat spreader 106, and then the upper mold is heated while melting the preform (body). 204 and the lower mold 202 are closed and sealed with resin.

図５は、金型２００から外し、基板１０２の半導体素子１２０が搭載された一面と反対側の面に外部端子（半田ボール１２６）を形成した切断前パッケージ構造１１０の構成を示す断面図である。図６は、金型２００から外した切断前パッケージ構造１１０の構成を部分的に示す平面図である。図５は、図６のｃ−ｃ線に沿った断面構造に対応する。切断前パッケージ構造１１０は、ＭＡＰ方式（多数個取り）の半導体パッケージとすることができる。   FIG. 5 is a cross-sectional view illustrating a configuration of the package structure 110 before cutting in which external terminals (solder balls 126) are formed on the surface opposite to the surface on which the semiconductor element 120 of the substrate 102 is mounted, which is removed from the mold 200. . FIG. 6 is a plan view partially showing the configuration of the package structure 110 before cutting removed from the mold 200. FIG. 5 corresponds to a cross-sectional structure taken along the line cc of FIG. The package structure 110 before cutting can be a MAP (multi-chip) semiconductor package.

このような構成の切断前パッケージ構造１１０を、パッケージ切断用ブレード（不図示）でＸ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａに沿って切断する。これにより、図１および図２を参照して説明した半導体装置１００が得られる。   The package structure 110 before cutting having such a configuration is cut along the X-direction cutting line 108b and the Y-direction cutting line 108a with a package cutting blade (not shown). Thereby, the semiconductor device 100 described with reference to FIGS. 1 and 2 is obtained.

本実施の形態において、ヒートスプレッダ１０６には、Ｘ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａの交点１０８に貫通孔１０６ａが形成されており、貫通孔１０６ａには封止樹脂１０４が埋め込まれる。ここで、封止樹脂１０４は、ヒートスプレッダ１０６を構成する材料よりも延性が低い。そのため、切断前パッケージ構造１１０をパッケージ切断用ブレードで切断する際に、パッケージ切断用ブレードによる切断部のだれやのびが発生しないようにすることができる。そのため、切断前パッケージ構造１１０をパッケージ切断用ブレードで切断する際に、交点１０８でのバリの発生を防ぐことができ、実装不良を防ぐことができる。   In the present embodiment, a through hole 106a is formed in the heat spreader 106 at the intersection 108 of the X direction cutting line 108b and the Y direction cutting line 108a, and the sealing resin 104 is embedded in the through hole 106a. Here, the sealing resin 104 has a lower ductility than the material constituting the heat spreader 106. Therefore, when the pre-cut package structure 110 is cut by the package cutting blade, it is possible to prevent the cutting portion from being drooped or stretched by the package cutting blade. Therefore, when the pre-cut package structure 110 is cut with a package cutting blade, the occurrence of burrs at the intersection 108 can be prevented, and mounting defects can be prevented.

また、ヒートスプレッダ１０６に貫通孔１０６ａを設けておくだけで、半導体素子１２０を封止樹脂１０４で封止する際に一体成型で貫通孔１０６ａ内に封止樹脂１０４を埋め込む構成とすることができ、簡易な手順で上記の効果を得ることができる。   Further, by simply providing the through hole 106a in the heat spreader 106, the sealing resin 104 can be embedded in the through hole 106a by integral molding when the semiconductor element 120 is sealed with the sealing resin 104. The above effects can be obtained with a simple procedure.

本実施の形態において、ヒートスプレッダ１０６には、Ｘ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａの交点１０８に選択的に貫通孔１０６ａを形成するので、ヒートスプレッダ１０６を貫通する貫通孔１０６ａを形成しても、複数の半導体素子１２０に対応する平板のヒートスプレッダ１０６が分離されることがない。そのため、簡易な手順で、バリの発生を防ぐことのできる構成が得られる。一方、特許文献３に記載の技術では、ヒートスプレッダを個片化する際に、切断用砥石が樹脂層のみを切断するように、切断ライン全体にわたって溝を形成している。そのため、上溝と下溝とをそれぞれ形成する必要があり、工程が複雑になる。そのため、経済性に優れないという問題がある。   In the present embodiment, the heat spreader 106 is selectively formed with the through-hole 106a at the intersection 108 of the X-direction cutting line 108b and the Y-direction cutting line 108a. Therefore, even if the through-hole 106a that penetrates the heat spreader 106 is formed. The flat plate heat spreader 106 corresponding to the plurality of semiconductor elements 120 is not separated. Therefore, the structure which can prevent generation | occurrence | production of a burr | flash with a simple procedure is obtained. On the other hand, in the technique described in Patent Document 3, when the heat spreader is separated into pieces, grooves are formed over the entire cutting line so that the cutting grindstone cuts only the resin layer. Therefore, it is necessary to form an upper groove and a lower groove, respectively, and the process becomes complicated. Therefore, there is a problem that it is not economical.

さらに、図１および図２に示した半導体装置１００において、温度サイクル等がかかって半導体装置１００に反りが生じた場合に応力が集中するコーナー部に半導体素子１２０を埋め込む封止樹脂１０４が一体形成されている。そのため、ヒートスプレッダ１０６と封止樹脂１０４との剥がれを生じさせる応力が低減されるため、品質の高いパッケージが得られる。   Further, in the semiconductor device 100 shown in FIGS. 1 and 2, the sealing resin 104 that embeds the semiconductor element 120 in the corner portion where stress is concentrated when the semiconductor device 100 is warped due to a temperature cycle or the like is integrally formed. Has been. Therefore, the stress that causes the heat spreader 106 and the sealing resin 104 to peel off is reduced, and a high-quality package can be obtained.

（第２の実施の形態）
図７は、本実施の形態におけるヒートスプレッダ１０６の構成を部分的に示す平面図である。
本実施の形態において、ヒートスプレッダ１０６の貫通孔１０６ａを予め、ヒートスプレッダ１０６を構成する材料よりも延性の低い低延性材料１３０で埋め込んでおく点で、第１の実施の形態と異なる。 (Second Embodiment)
FIG. 7 is a plan view partially showing the configuration of the heat spreader 106 in the present embodiment.
The present embodiment is different from the first embodiment in that the through hole 106a of the heat spreader 106 is previously filled with a low ductility material 130 having a lower ductility than the material constituting the heat spreader 106.

本実施の形態においても、ヒートスプレッダ１０６には、Ｘ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａの交点１０８にそれぞれ貫通孔１０６ａが形成されている。本実施の形態において、ヒートスプレッダ１０６の貫通孔１０６ａには、低延性材料１３０が埋め込まれている。低延性材料１３０は、たとえば、後に半導体素子１２０を封止する封止樹脂１０４と同様の樹脂材料により構成することができる。また、低延性材料１３０は、たとえば、銅より延性の低い金属やセラミック等により構成することもできる。   Also in the present embodiment, the heat spreader 106 is formed with through holes 106a at intersections 108 of the X-direction cutting line 108b and the Y-direction cutting line 108a. In the present embodiment, a low ductility material 130 is embedded in the through hole 106 a of the heat spreader 106. The low ductility material 130 can be made of, for example, a resin material similar to the sealing resin 104 that seals the semiconductor element 120 later. Moreover, the low ductility material 130 can also be comprised with a metal, ceramic, etc. whose ductility is lower than copper, for example.

本実施の形態において、低延性材料１３０は、たとえば、貫通孔１０６ａに対応する直径を有する棒状に形成した後、それをヒートスプレッダ１０６の膜厚に応じて切断してチップ化することができる。次いで、各チップを貫通孔１０６ａに埋め込むことにより低延性材料１３０が貫通孔１０６ａに埋め込まれたヒートスプレッダ１０６を形成することができる。また、低延性材料１３０として樹脂を用いる場合、印刷技術等を用いて、ヒートスプレッダ１０６の貫通孔１０６ａ内に低延性材料１３０を埋め込むこともできる。   In the present embodiment, for example, the low ductility material 130 can be formed into a chip by forming it into a rod shape having a diameter corresponding to the through hole 106 a and then cutting it according to the film thickness of the heat spreader 106. Then, the heat spreader 106 in which the low ductility material 130 is embedded in the through hole 106a can be formed by embedding each chip in the through hole 106a. Moreover, when using resin as the low ductility material 130, the low ductility material 130 can also be embedded in the through-hole 106a of the heat spreader 106 using a printing technique etc.

本実施の形態において、図７に示したようなヒートスプレッダ１０６を用いて、金型２００により、半導体素子１２０を封止樹脂１０４で封止する。図８（ａ）は、図７に示したヒートスプレッダ１０６のｄ−ｄ線に沿った断面構造に対応する。   In the present embodiment, the semiconductor element 120 is sealed with the sealing resin 104 by the mold 200 using the heat spreader 106 as shown in FIG. FIG. 8A corresponds to the cross-sectional structure along the dd line of the heat spreader 106 shown in FIG.

本実施の形態においても、まず、基板１０２上に複数の半導体素子１２０を搭載し、ボンディングワイヤ１２２を介して基板１０２の配線と接続しておく。次いで、ワイヤボンディング済みの複数の半導体素子１２０が搭載された基板１０２を、半導体素子１２０が搭載された面が下型２０２と向かい合うようにして、金型２００の上型２０４に配置する。また、金型２００の下型２０２にヒートスプレッダ１０６を配置する。このような状態で、金型２００の導入口から封止樹脂１０４を導入する（図８（ｂ））。これにより、半導体素子１２０およびボンディングワイヤ１２２が封止樹脂１０４で封止される（図８（ｃ））。   Also in this embodiment, first, a plurality of semiconductor elements 120 are mounted on the substrate 102 and connected to the wiring of the substrate 102 via bonding wires 122. Next, the substrate 102 on which the plurality of wire-bonded semiconductor elements 120 are mounted is placed on the upper mold 204 of the mold 200 so that the surface on which the semiconductor elements 120 are mounted faces the lower mold 202. Further, the heat spreader 106 is disposed on the lower mold 202 of the mold 200. In such a state, the sealing resin 104 is introduced from the introduction port of the mold 200 (FIG. 8B). Thereby, the semiconductor element 120 and the bonding wire 122 are sealed with the sealing resin 104 (FIG. 8C).

図９は、金型２００から外し、基板１０２の半導体素子１２０が搭載された一面と反対側の面に外部端子（半田ボール１２６）を形成した切断前パッケージ構造１１０の構成を示す断面図である。図１０は、金型２００から外した切断前パッケージ構造１１０の構成を示す平面図である。図９は、図１０のｅ−ｅ線に沿った断面構造に対応する。   FIG. 9 is a cross-sectional view illustrating a configuration of the package structure 110 before cutting in which external terminals (solder balls 126) are formed on the surface opposite to the surface on which the semiconductor element 120 of the substrate 102 is mounted, which is removed from the mold 200. . FIG. 10 is a plan view showing the configuration of the pre-cut package structure 110 removed from the mold 200. FIG. 9 corresponds to the cross-sectional structure along the line ee in FIG.

このような構成の切断前パッケージ構造１１０を、パッケージ切断用ブレード（不図示）でＸ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａに沿って切断する。これにより、図１１に示した構成の半導体装置１００が得られる。   The package structure 110 before cutting having such a configuration is cut along the X-direction cutting line 108b and the Y-direction cutting line 108a with a package cutting blade (not shown). Thereby, the semiconductor device 100 having the configuration shown in FIG. 11 is obtained.

本実施の形態において、ヒートスプレッダ１０６には、Ｘ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａの交点１０８に貫通孔１０６ａが形成されており、貫通孔１０６ａには低延性材料１３０が埋め込まれる。ここで、低延性材料１３０は、ヒートスプレッダ１０６を構成する材料よりも延性が低い。そのため、切断前パッケージ構造１１０をパッケージ切断用ブレードで切断する際に、パッケージ切断用ブレードによる切断部のだれやのびが発生しないようにすることができる。そのため、切断前パッケージ構造１１０をパッケージ切断用ブレードで切断する際に、交点１０８でのバリの発生を防ぐことができる。   In the present embodiment, the heat spreader 106 is formed with a through hole 106a at the intersection 108 of the X direction cutting line 108b and the Y direction cutting line 108a, and the low ductility material 130 is embedded in the through hole 106a. Here, the low ductility material 130 has lower ductility than the material constituting the heat spreader 106. Therefore, when the pre-cut package structure 110 is cut by the package cutting blade, it is possible to prevent the cutting portion from being drooped or stretched by the package cutting blade. Therefore, when the pre-cutting package structure 110 is cut with a package cutting blade, the occurrence of burrs at the intersection 108 can be prevented.

（第３の実施の形態）
図１２は、本実施の形態におけるヒートスプレッダ１０６の構成を示す平面図である。
本実施の形態において、ヒートスプレッダ１０６に、平面視で半導体素子１２０と重なる箇所に、半導体素子１２０の方向に突出する凹部１０６ｂが形成されている点で第１の実施の形態と異なる。 (Third embodiment)
FIG. 12 is a plan view showing the configuration of the heat spreader 106 in the present embodiment.
In the present embodiment, the heat spreader 106 is different from the first embodiment in that a concave portion 106 b that protrudes in the direction of the semiconductor element 120 is formed at a location overlapping the semiconductor element 120 in plan view.

本実施の形態においても、ヒートスプレッダ１０６には、Ｘ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａの交点１０８にそれぞれ貫通孔１０６ａが形成されている。また、本実施の形態において、ヒートスプレッダ１０６には、ヒートスプレッダ１０６を基板１０２上に配置したときに半導体素子１２０と重なる箇所に、凹部１０６ｂが形成されている。   Also in the present embodiment, the heat spreader 106 is formed with through holes 106a at intersections 108 of the X-direction cutting line 108b and the Y-direction cutting line 108a. Further, in the present embodiment, the heat spreader 106 is formed with a recess 106 b at a location overlapping the semiconductor element 120 when the heat spreader 106 is disposed on the substrate 102.

本実施の形態において、図１２に示したようなヒートスプレッダ１０６を用いて、金型２００により、半導体素子１２０を封止樹脂１０４で封止する。図１３（ａ）は、図１２に示したヒートスプレッダ１０６のｆ−ｆ線に沿った断面構造に対応する。本実施の形態において、ヒートスプレッダ１０６は、凹部１０６ｂが設けられた箇所およびその外周部の全面にわたって、略等しい厚みを有する構成とすることができる。また、凹部１０６ｂの形状は、円形状、矩形状、または多角形状等とすることができる。いずれの場合も、凹部１０６ｂは、たとえば、プレス加工により形成することができる。   In the present embodiment, the semiconductor element 120 is sealed with the sealing resin 104 by the mold 200 using the heat spreader 106 as shown in FIG. FIG. 13A corresponds to the cross-sectional structure along the line ff of the heat spreader 106 shown in FIG. In the present embodiment, the heat spreader 106 can be configured to have substantially the same thickness over the portion where the recess 106b is provided and the entire outer periphery thereof. In addition, the shape of the recess 106b can be a circular shape, a rectangular shape, a polygonal shape, or the like. In any case, the recess 106b can be formed by, for example, press working.

本実施の形態においても、まず、基板１０２上に複数の半導体素子１２０を搭載し、ボンディングワイヤ１２２を介して基板１０２の配線と接続しておく。次いで、ワイヤボンディング済みの複数の半導体素子１２０が搭載された基板１０２を、半導体素子１２０が搭載された面が下型２０２と向かい合うようにして、金型２００の上型２０４に配置する。また、金型２００の下型２０２にヒートスプレッダ１０６を配置する。このとき、ヒートスプレッダ１０６は、凹部１０６ｂが半導体素子１２０の方向に突出するように配置する。このような状態で、金型２００の導入口から封止樹脂１０４を導入する（図１３（ｂ））。これにより、半導体素子１２０およびボンディングワイヤ１２２が封止樹脂１０４で封止されるとともに、ヒートスプレッダ１０６の貫通孔１０６ａ内にも封止樹脂１０４が充填される（図１３（ｃ））。   Also in this embodiment, first, a plurality of semiconductor elements 120 are mounted on the substrate 102 and connected to the wiring of the substrate 102 via bonding wires 122. Next, the substrate 102 on which the plurality of wire-bonded semiconductor elements 120 are mounted is placed on the upper mold 204 of the mold 200 so that the surface on which the semiconductor elements 120 are mounted faces the lower mold 202. Further, the heat spreader 106 is disposed on the lower mold 202 of the mold 200. At this time, the heat spreader 106 is disposed so that the recess 106 b protrudes in the direction of the semiconductor element 120. In such a state, the sealing resin 104 is introduced from the introduction port of the mold 200 (FIG. 13B). As a result, the semiconductor element 120 and the bonding wire 122 are sealed with the sealing resin 104, and the sealing resin 104 is also filled into the through hole 106a of the heat spreader 106 (FIG. 13C).

図１４は、金型２００から外し、基板１０２の半導体素子１２０が搭載された一面と反対側の面に外部端子（半田ボール１２６）を形成した切断前パッケージ構造１１０の構成を示す断面図である。図１５は、金型２００から外した切断前パッケージ構造１１０の構成を示す平面図である。図１４は、図１５のｇ−ｇ線に沿った断面構造に対応する。   FIG. 14 is a cross-sectional view illustrating a configuration of the package structure 110 before cutting in which external terminals (solder balls 126) are formed on the surface opposite to the surface on which the semiconductor element 120 of the substrate 102 is mounted, which is removed from the mold 200. . FIG. 15 is a plan view showing the configuration of the pre-cut package structure 110 removed from the mold 200. FIG. 14 corresponds to a cross-sectional structure taken along the line gg of FIG.

このような構成の切断前パッケージ構造１１０を、パッケージ切断用ブレード（不図示）でＸ方向切断ライン１０８ｂおよびＹ方向切断ライン１０８ａに沿って切断する。これにより、図１６に示した構成の半導体装置１００が得られる。   The package structure 110 before cutting having such a configuration is cut along the X-direction cutting line 108b and the Y-direction cutting line 108a with a package cutting blade (not shown). Thereby, the semiconductor device 100 having the configuration shown in FIG. 16 is obtained.

本実施の形態においても、第１の実施の形態と同様の効果が得られる。また、本実施の形態において、ヒートスプレッダ１０６に凹部１０６ｂを設けておくことにより、ヒートスプレッダ１０６と半導体素子１２０との距離を近くすることができ、ヒートスプレッダ１０６による放熱性能を向上することができる。   Also in this embodiment, the same effect as that of the first embodiment can be obtained. In the present embodiment, by providing the heat spreader 106 with the recess 106b, the distance between the heat spreader 106 and the semiconductor element 120 can be reduced, and the heat dissipation performance of the heat spreader 106 can be improved.

本実施の形態において、ヒートスプレッダ１０６の凹部１０６ｂは、プレス加工で形成することができるため、コストアップすることなく、簡易な手順で上記の効果を得ることができる。ヒートスプレッダ１０６の凹部１０６ｂと貫通孔１０６ａとは、同時に形成することもできる。特許文献４（特開２０００−７７５７５号公報）に記載の技術では、ヒートスプレッダの中央部のみ膜厚が厚くなる構成となっており、エッチング工程や曲げ加工等加工工程が多く、コストが著しく増大するという問題があった。本実施の形態においては、コストを増大することなく、放熱性能を向上できる半導体装置を提供することができる。   In the present embodiment, since the recess 106b of the heat spreader 106 can be formed by press working, the above-described effects can be obtained with a simple procedure without increasing the cost. The recess 106b and the through hole 106a of the heat spreader 106 can be formed simultaneously. In the technique described in Patent Document 4 (Japanese Patent Laid-Open No. 2000-77575), only the central portion of the heat spreader has a thick film thickness, and there are many processing steps such as an etching step and a bending step, and the cost is remarkably increased. There was a problem. In this embodiment, a semiconductor device that can improve heat dissipation performance without increasing costs can be provided.

また、図１７に示すように、半導体素子１２０とヒートスプレッダ１０６の凹部１０６ｂとの間に、放熱ペースト１３２を設けることもできる。放熱ペースト１３２は、たとえばヒートスプレッダ１０６および基板１０２を金型２００にセットする前に、基板１０２上に搭載された各半導体素子１２０の上面に塗布しておくことができる。このような構成により、半導体素子１２０からヒートスプレッダ１０６への放熱が向上するため、パッケージの放熱性能を向上することができる。   In addition, as shown in FIG. 17, a heat radiation paste 132 can be provided between the semiconductor element 120 and the recess 106 b of the heat spreader 106. For example, the heat dissipating paste 132 can be applied to the upper surface of each semiconductor element 120 mounted on the substrate 102 before the heat spreader 106 and the substrate 102 are set in the mold 200. With such a configuration, heat dissipation from the semiconductor element 120 to the heat spreader 106 is improved, so that the heat dissipation performance of the package can be improved.

また、本実施の形態で説明した凹部１０６ｂを有するヒートスプレッダ１０６を用いた場合も、第２の実施の形態で説明したように、ヒートスプレッダ１０６の貫通孔１０６ａを予め、ヒートスプレッダ１０６を構成する材料よりも延性の低い低延性材料１３０で埋め込んでおく構成とすることもできる。   In addition, when the heat spreader 106 having the recess 106b described in the present embodiment is used, as described in the second embodiment, the through hole 106a of the heat spreader 106 is made in advance of the material constituting the heat spreader 106. It can also be set as the structure filled with the low ductility material 130 with low ductility.

なお、以上の第１から第３の実施の形態においては、半導体素子１２０が、ボンディングワイヤ１２２を介して基板１０２と接続される構成を示したが、半導体素子１２０は、基板１０２とフリップチップ接続された構成とすることもできる。   In the first to third embodiments described above, the configuration in which the semiconductor element 120 is connected to the substrate 102 via the bonding wire 122 is shown. However, the semiconductor element 120 is connected to the substrate 102 in a flip chip manner. It can also be set as the structure made.

図１８から図２０にこのような構成の半導体装置１００の断面図を示す。図１８（ａ）に示したように、半導体素子１２０は、その素子形成面が基板１０２の一面と対向するように、基板１０２の一面上に形成され、端子１４２を介して基板１０２に形成された配線等と接続される。また、半導体素子１２０と基板１０２との間には、アンダーフィル１４０が形成されている。図１８（ａ）に示した半導体装置１００は、半導体素子１２０がフリップチップ接続で基板１０２と接続されている点を除き、図１に示した半導体装置１００と同様の構成を有する。同様に、１８（ｂ）に示した半導体装置１００は、半導体素子１２０がフリップチップ接続で基板１０２と接続されている点を除き、図１１に示した半導体装置１００と同様の構成を有する。   18 to 20 are sectional views of the semiconductor device 100 having such a configuration. As shown in FIG. 18A, the semiconductor element 120 is formed on one surface of the substrate 102 so that its element formation surface faces one surface of the substrate 102, and is formed on the substrate 102 via the terminals 142. Connected to other wiring. An underfill 140 is formed between the semiconductor element 120 and the substrate 102. The semiconductor device 100 shown in FIG. 18A has the same configuration as the semiconductor device 100 shown in FIG. 1 except that the semiconductor element 120 is connected to the substrate 102 by flip chip connection. Similarly, the semiconductor device 100 shown in FIG. 18B has the same configuration as the semiconductor device 100 shown in FIG. 11 except that the semiconductor element 120 is connected to the substrate 102 by flip chip connection.

また、半導体素子１２０をフリップチップ接続で基板１０２と接続した構成においては、図１９に示したように、半導体素子１２０は、封止樹脂１０４で封止されていない構成とすることもできる。図１９（ａ）に示した半導体装置１００において、ヒートスプレッダ１０６は、半導体素子１２０の素子形成面とは反対側の面上に、当該面と接して設けられている。また、図１９（ｂ）に示した半導体装置１００において、ヒートスプレッダ１０６は、半導体素子１２０の素子形成面とは反対側の面上に、放熱ペースト１３２を介して設けられている。このような場合、ヒートスプレッダ１０６の貫通孔１０６ａは、低延性材料１３０で埋め込んだ構成とすることができる。   Further, in the configuration in which the semiconductor element 120 is connected to the substrate 102 by flip-chip connection, the semiconductor element 120 may be configured not to be sealed with the sealing resin 104 as shown in FIG. In the semiconductor device 100 shown in FIG. 19A, the heat spreader 106 is provided on the surface opposite to the element formation surface of the semiconductor element 120 in contact with the surface. In the semiconductor device 100 shown in FIG. 19B, the heat spreader 106 is provided on the surface of the semiconductor element 120 opposite to the element formation surface via the heat radiation paste 132. In such a case, the through hole 106 a of the heat spreader 106 can be configured to be embedded with the low ductility material 130.

また、半導体素子１２０をフリップチップ接続で基板１０２と接続した構成においても、以上の第３の実施の形態で説明したように、ヒートスプレッダ１０６に、平面視で半導体素子１２０と重なる箇所に、半導体素子１２０の方向に突出する凹部１０６ｂが形成された構成とすることができる。図２０（ａ）、図２０（ｂ）、および図２０（ｃ）に、このような構成の半導体装置１００の断面図を示す。   Even in the configuration in which the semiconductor element 120 is connected to the substrate 102 by flip-chip connection, as described in the third embodiment, the semiconductor element 120 is placed on the heat spreader 106 so as to overlap the semiconductor element 120 in plan view. A recess 106 b protruding in the direction 120 can be formed. 20A, 20B, and 20C are cross-sectional views of the semiconductor device 100 having such a configuration.

さらに、以上の第１から第３の実施の形態においては、各半導体装置１００に、それぞれ一つの半導体素子１２０が設けられた構成を示したが、各半導体装置１００には、複数の半導体素子が設けられた構成とすることもできる。たとえば、図２１（ａ）に示したように、基板１０２の一面に、半導体素子１２０ａと半導体素子１２０ｂとが並置された構成とすることができる。この場合、切断前パッケージ構造１１０において、Ｘ方向切断ラインおよびＹ方向切断ラインでそれぞれ囲まれた領域に、半導体素子１２０ａと半導体素子１２０ｂとが並置された構成とすることができる。   Furthermore, in the above first to third embodiments, the configuration in which each semiconductor device 100 is provided with one semiconductor element 120 is shown. However, each semiconductor device 100 includes a plurality of semiconductor elements. It can also be set as the provided structure. For example, as illustrated in FIG. 21A, the semiconductor element 120 a and the semiconductor element 120 b may be arranged in parallel on one surface of the substrate 102. In this case, in the package structure 110 before cutting, the semiconductor element 120a and the semiconductor element 120b can be arranged in parallel in regions surrounded by the X-direction cutting line and the Y-direction cutting line, respectively.

また、たとえば、図２１（ｂ）に示したように、基板１０２の一面に、半導体素子１２０ａと半導体素子１２０ｂとが積層された構成とすることもできる。この場合も、切断前パッケージ構造１１０において、Ｘ方向切断ラインおよびＹ方向切断ラインでそれぞれ囲まれた領域に、半導体素子１２０ａと半導体素子１２０ｂとが積層された構成とすることができる。   Further, for example, as illustrated in FIG. 21B, the semiconductor element 120 a and the semiconductor element 120 b may be stacked on one surface of the substrate 102. Also in this case, in the pre-cut package structure 110, the semiconductor element 120a and the semiconductor element 120b can be stacked in regions surrounded by the X-direction cut line and the Y-direction cut line, respectively.

（第４の実施の形態）
以上の実施の形態では、複数の半導体素子１２０が搭載された基板１０２上にヒートスプレッダ１０６を配置するとともに、封止樹脂１０４で複数の半導体素子１２０を封止する例を示したが、本発明のヒートスプレッダは、半導体ウェハ上で再配線や保護膜や端子の形成を行い、その後に個片化するウェハレベルパッケージに適用することもできる。 (Fourth embodiment)
In the above embodiment, an example in which the heat spreader 106 is arranged on the substrate 102 on which the plurality of semiconductor elements 120 are mounted and the plurality of semiconductor elements 120 is sealed with the sealing resin 104 has been described. The heat spreader can also be applied to a wafer level package in which rewiring, a protective film, and terminals are formed on a semiconductor wafer and then separated into individual pieces.

図２２は、ウェハレベルパッケージの切断前パッケージ構造３１０の構成を示す断面図である。
本実施の形態において、基板３０２は、シリコンウェハ等の半導体ウェハとすることができる。基板３０２の一面には、接着剤（不図示）を介してヒートスプレッダ３０６が貼り付けられている。ここで、本実施の形態において、ヒートスプレッダ３０６は、以上の実施の形態で説明したヒートスプレッダ１０６と同様の構成を有する。ヒートスプレッダ３０６には、貫通孔３０６ａが設けられている。図２２（ａ）に示したように、たとえば、貫通孔３０６ａは、低延性材料１３０と同様の材料である低延性材料３３０により埋め込まれた構成とすることができる。基板３０２の一面とは反対側の他面には、再配線のための配線や保護膜等を含む配線層３０４が形成されている。配線層３０４により、複数の半導体素子が構成される。また、配線層３０４が基板３０２と接する面と反対側の面には、外部端子３２０が形成されている。 FIG. 22 is a cross-sectional view showing the configuration of the pre-cut package structure 310 of the wafer level package.
In the present embodiment, the substrate 302 can be a semiconductor wafer such as a silicon wafer. A heat spreader 306 is attached to one surface of the substrate 302 via an adhesive (not shown). Here, in the present embodiment, the heat spreader 306 has the same configuration as the heat spreader 106 described in the above embodiments. The heat spreader 306 is provided with a through hole 306a. As shown in FIG. 22A, for example, the through hole 306 a can be configured to be embedded with a low ductility material 330 that is the same material as the low ductility material 130. A wiring layer 304 including wiring for rewiring, a protective film, and the like is formed on the other surface opposite to the one surface of the substrate 302. The wiring layer 304 forms a plurality of semiconductor elements. An external terminal 320 is formed on the surface opposite to the surface where the wiring layer 304 is in contact with the substrate 302.

さらに、本実施の形態において、図２２（ｂ）に示したように、基板３０２とヒートスプレッダ３０６との間には、封止樹脂３３４が形成されていてもよく、貫通孔３０６ａが封止樹脂３３４により埋め込まれていてもよい。また、図２２（ｃ）に示したように、貫通孔３０６ａ内は、封止樹脂３３４とは別体の低延性材料３３０で埋め込まれた構成とすることもできる。   Further, in the present embodiment, as shown in FIG. 22B, a sealing resin 334 may be formed between the substrate 302 and the heat spreader 306, and the through hole 306a serves as the sealing resin 334. May be embedded. Further, as shown in FIG. 22C, the through hole 306 a may be embedded with a low ductility material 330 that is separate from the sealing resin 334.

本実施の形態においても、Ｘ方向切断ライン（不図示）およびＹ方向切断ライン（不図示）の交点３０８に貫通孔３０６ａが形成されており、貫通孔３０６ａには封止樹脂３３４または低延性材料３３０が埋め込まれる。ここで、封止樹脂３３４および低延性材料３３０は、いずれもヒートスプレッダ３０６を構成する材料よりも延性が低い。そのため、切断前パッケージ構造３１０をパッケージ切断用ブレードで切断する際に、パッケージ切断用ブレードによる切断部のだれやのびが発生しないようにすることができる。そのため、切断前パッケージ構造３１０をパッケージ切断用ブレードで切断する際に、交点３０８でのバリの発生を防ぐことができる。   Also in this embodiment, a through hole 306a is formed at an intersection 308 of an X direction cutting line (not shown) and a Y direction cutting line (not shown), and a sealing resin 334 or a low ductility material is formed in the through hole 306a. 330 is embedded. Here, both the sealing resin 334 and the low ductility material 330 have lower ductility than the material constituting the heat spreader 306. Therefore, when the pre-cutting package structure 310 is cut by the package cutting blade, it is possible to prevent the cutting portion from being drooped or stretched by the package cutting blade. Therefore, when the pre-cutting package structure 310 is cut by the package cutting blade, the occurrence of burrs at the intersection 308 can be prevented.

図２３（ａ）、図２３（ｂ）、および図２３（ｃ）は、それぞれ、図２２（ａ）、図２２（ｂ）、および図２２（ｃ）の切断前パッケージ構造３１０を切断ラインに沿って切断して個片化した半導体装置３００の構成を示す断面図である。   23 (a), FIG. 23 (b), and FIG. 23 (c) use the pre-cut package structure 310 of FIG. 22 (a), FIG. 22 (b), and FIG. 22 (c) as a cutting line, respectively. It is sectional drawing which shows the structure of the semiconductor device 300 cut | disconnected along with and separated into pieces.

以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。   As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

以上の実施の形態で説明した構成に加えて、たとえば、ヒートスプレッダの貫通孔の内壁を粗化させた構成とすることもできる。これにより、ヒートスプレッダと封止樹脂や低延性材料との密着性を良好にすることができ、剥がれの可能性を低減させることができる。また、ヒートスプレッダと基板との間に封止樹脂を設ける構成の場合、ヒートスプレッダの封止樹脂との接着面を粗化させた構成とすることもできる。これにより、ヒートスプレッダと封止樹脂との密着性を良好にすることができ、剥がれの可能性を低減させることができる。   In addition to the configuration described in the above embodiment, for example, the inner wall of the through hole of the heat spreader may be roughened. Thereby, the adhesiveness of a heat spreader, sealing resin, and a low ductility material can be made favorable, and the possibility of peeling can be reduced. Further, in the case where the sealing resin is provided between the heat spreader and the substrate, the adhesive surface of the heat spreader with the sealing resin may be roughened. Thereby, the adhesiveness of a heat spreader and sealing resin can be made favorable, and the possibility of peeling can be reduced.

また、ヒートスプレッダの貫通孔の内壁面に凹凸形状や段差を設けた構成とすることもできる。また、ヒートスプレッダの貫通孔の内壁面に凹凸形状や段差を設けるとともに、内壁を粗化させた構成とすることもできる。このような構成により、ヒートスプレッダと封止樹脂や低延性材料との密着性を良好にすることができ、剥がれの可能性を低減させることができる。   Moreover, it can also be set as the structure which provided uneven | corrugated shape and the level | step difference in the inner wall face of the through-hole of a heat spreader. Moreover, while providing an uneven | corrugated shape and a level | step difference in the inner wall face of the through-hole of a heat spreader, it can also be set as the structure which roughened the inner wall. With such a configuration, the adhesion between the heat spreader and the sealing resin or the low ductility material can be improved, and the possibility of peeling can be reduced.

１００ 半導体装置
１０２ 基板
１０４ 封止樹脂
１０６ ヒートスプレッダ
１０６ａ 貫通孔
１０６ｂ 凹部
１０８ 交点
１０８ａ Ｙ方向切断ライン
１０８ｂ Ｘ方向切断ライン
１１０ 切断前パッケージ構造
１２０ 半導体素子
１２０ａ 半導体素子
１２０ｂ 半導体素子
１２２ ボンディングワイヤ
１２６ 半田ボール
１３０ 低延性材料
１３２ 放熱ペースト
１４０ アンダーフィル
１４２ 端子
２００ 金型
２０２ 下型
２０４ 上型
３００ 半導体装置
３０２ 基板
３０４ 配線層
３０６ ヒートスプレッダ
３０６ａ 貫通孔
３０８ 交点
３１０ 切断前パッケージ構造
３２０ 外部端子
３３０ 低延性材料
３３４ 封止樹脂 DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Board | substrate 104 Sealing resin 106 Heat spreader 106a Through-hole 106b Recessed part 108 Intersection 108a Y direction cutting line 108b X direction cutting line 110 Package structure 120 before cutting 120 Semiconductor element 120a Semiconductor element 120b Semiconductor element 122 Bonding wire 126 Solder ball 130 Low Ductile material 132 Heat radiation paste 140 Underfill 142 Terminal 200 Mold 202 Lower mold 204 Upper mold 300 Semiconductor device 302 Substrate 304 Wiring layer 306 Heat spreader 306a Through hole 308 Intersection 310 Package structure before cutting 320 External terminal 330 Low ductility material 334 Sealing resin

Claims (24)

基板と、
前記基板の一面上に配置され、Ｘ方向のＸ方向切断ラインおよび前記Ｘ方向と交差するＹ方向のＹ方向切断ラインの交点にそれぞれ貫通孔が形成された放熱板であって、当該貫通孔が当該放熱板を構成する材料よりも延性の低い低延性材料で埋め込まれている放熱板と、
を含む構造体を、前記Ｘ方向切断ラインおよび前記Ｙ方向切断ラインにそれぞれ沿って切断し、複数の半導体装置に個片化する工程を含む半導体装置の製造方法。 A substrate,
A heat radiating plate disposed on one surface of the substrate and having a through hole formed at an intersection of an X direction cutting line in the X direction and a Y direction cutting line in the Y direction intersecting the X direction, A heat sink embedded with a low ductility material having a lower ductility than the material constituting the heat sink;
A method of manufacturing a semiconductor device including a step of cutting a structure including a plurality of semiconductor devices along the X-direction cutting line and the Y-direction cutting line. 請求項１に記載の半導体装置の製造方法において、
前記複数の半導体装置に個片化する工程において、前記貫通孔の幅よりも幅の狭い切断用ブレードを用いて前記構造体を切断する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein in the step of dividing into a plurality of semiconductor devices, the structure is cut using a cutting blade having a width smaller than that of the through hole. 請求項１または２に記載の半導体装置の製造方法において、
前記放熱板は、銅により構成された半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 or 2,
The said heat sink is a manufacturing method of the semiconductor device comprised with copper. 請求項３に記載の半導体装置の製造方法において、
前記放熱板表面には、金属めっきが施されている半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 3,
A method for manufacturing a semiconductor device, wherein a metal plating is applied to a surface of the heat sink. 請求項１から４いずれかに記載の半導体装置の製造方法において、
前記低延性材料は樹脂である半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claim 1 to 4,
The method for manufacturing a semiconductor device, wherein the low ductility material is a resin. 請求項１から５いずれかに記載の半導体装置の製造方法において、
前記構造体は、前記基板の前記一面上に形成された複数の半導体素子と、前記基板の前記一面と前記放熱板の間に形成された樹脂と、をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claim 1 to 5,
The structure is a method for manufacturing a semiconductor device, further comprising: a plurality of semiconductor elements formed on the one surface of the substrate; and a resin formed between the one surface of the substrate and the heat dissipation plate. 請求項１から５いずれかに記載の半導体装置の製造方法において、
前記構造体は、素子形成面が前記基板の前記一面と対向するように、当該基板の前記一面上に形成された複数の半導体素子をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claim 1 to 5,
The method of manufacturing a semiconductor device, wherein the structure further includes a plurality of semiconductor elements formed on the one surface of the substrate such that an element formation surface faces the one surface of the substrate. 請求項７に記載の半導体装置の製造方法において、
前記構造体は、各前記半導体素子の前記素子形成面と反対の面と、前記放熱板との間に形成された樹脂をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7,
The said structure is a manufacturing method of the semiconductor device which further contains resin formed between the surface opposite to the said element formation surface of each said semiconductor element, and the said heat sink. 請求項６または８に記載の半導体装置の製造方法において、
前記複数の半導体装置に個片化する工程の前に、
前記貫通孔が形成された前記放熱板と、前記複数の半導体素子が搭載された前記基板とを、前記複数の半導体素子が前記放熱板と対向するように間隔を隔てて配置し、前記放熱板と前記基板との間に前記樹脂を形成して前記複数の半導体素子を前記樹脂で封止する工程をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 6 or 8,
Before the step of dividing into the plurality of semiconductor devices,
The heat radiating plate in which the through-holes are formed and the substrate on which the plurality of semiconductor elements are mounted are arranged at an interval so that the plurality of semiconductor elements face the heat radiating plate, and the heat radiating plate Forming the resin between the substrate and the substrate, and further sealing the plurality of semiconductor elements with the resin. 請求項９に記載の半導体装置の製造方法において、
前記低延性材料は、前記樹脂であって、
前記複数の半導体素子を前記樹脂で封止する工程において、前記樹脂を形成する前には、前記放熱板の前記貫通孔には前記低延性材料が埋め込まれておらず、前記複数の半導体素子を前記樹脂で封止する際に、前記貫通孔にも前記樹脂を埋め込む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 9,
The low ductility material is the resin,
In the step of sealing the plurality of semiconductor elements with the resin, before the resin is formed, the low ductility material is not embedded in the through hole of the heat sink, and the plurality of semiconductor elements are formed. A method of manufacturing a semiconductor device in which the resin is embedded in the through-hole when the resin is sealed. 請求項９に記載の半導体装置の製造方法において、
前記複数の半導体素子を前記樹脂で封止する工程の前に、前記放熱板の前記貫通孔に前記低延性材料を埋め込む工程をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, further comprising a step of embedding the low ductility material in the through hole of the heat radiating plate before the step of sealing the plurality of semiconductor elements with the resin. 請求項６から１１いずれかに記載の半導体装置の製造方法において、
前記構造体において、前記Ｘ方向切断ラインおよび前記Ｙ方向切断ラインでそれぞれ囲まれた領域に、複数の前記半導体素子が並置された構成を有する半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 6-11,
A method for manufacturing a semiconductor device, comprising: a plurality of semiconductor elements juxtaposed in regions surrounded by the X-direction cutting line and the Y-direction cutting line in the structure. 請求項６から１１いずれかに記載の半導体装置の製造方法において、
前記構造体において、前記Ｘ方向切断ラインおよび前記Ｙ方向切断ラインでそれぞれ囲まれた領域に、複数の前記半導体素子が積層された構成を有する半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 6-11,
A method for manufacturing a semiconductor device, comprising: a plurality of semiconductor elements stacked in regions surrounded by the X-direction cutting line and the Y-direction cutting line in the structure. 請求項１から５いずれかに記載の半導体装置の製造方法において、
前記基板は、前記一面とは反対側の他面に複数の半導体素子が形成された半導体ウェハであり、
前記放熱板は、前記半導体ウェハの前記一面を覆うように設けられた半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claim 1 to 5,
The substrate is a semiconductor wafer in which a plurality of semiconductor elements are formed on the other surface opposite to the one surface,
The said heat sink is a manufacturing method of the semiconductor device provided so that the said one surface of the said semiconductor wafer might be covered. 請求項１４に記載の半導体装置の製造方法において、
前記構造体は、前記半導体ウェハの前記一面と前記放熱板との間に形成された樹脂をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 14,
The structure is a method for manufacturing a semiconductor device, further comprising a resin formed between the one surface of the semiconductor wafer and the heat sink. 請求項１５に記載の半導体装置の製造方法において、
前記複数の半導体装置に個片化する工程の前に、
前記貫通孔が形成された前記放熱板と、前記半導体ウェハの前記一面とを、対向するように間隔を隔てて配置し、前記放熱板と前記半導体ウェハとの間に前記樹脂を形成して前記半導体ウェハを前記樹脂で封止する工程をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 15,
Before the step of dividing into the plurality of semiconductor devices,
The heat radiating plate in which the through-hole is formed and the one surface of the semiconductor wafer are arranged so as to oppose each other, and the resin is formed between the heat radiating plate and the semiconductor wafer. The manufacturing method of the semiconductor device which further includes the process of sealing a semiconductor wafer with the said resin. 請求項６から１３いずれかに記載の半導体装置の製造方法において、
前記放熱板には、平面視で各前記半導体素子と重なる箇所に、当該半導体素子に近づく方向に突出した凹部が形成された半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 6-13,
The manufacturing method of the semiconductor device by which the recessed part which protruded in the direction which approaches the said semiconductor element in the location which overlaps with each said semiconductor element by planar view was formed in the said heat sink. 基板と、
前記基板に形成された半導体素子と、
前記基板の一面を覆うように配置された放熱板と、
を含み、
前記放熱板は四隅が除かれ、前記四隅には、当該放熱板を構成する材料よりも延性の低い低延性材料が形成されている半導体装置。 A substrate,
A semiconductor element formed on the substrate;
A heat sink arranged to cover one surface of the substrate;
Including
A semiconductor device in which the corners of the heat radiating plate are removed, and a low ductility material having a lower ductility than the material constituting the heat radiating plate is formed in the four corners. 請求項１８に記載の半導体装置において、
前記半導体素子が、前記基板の前記一面に形成された半導体装置。 The semiconductor device according to claim 18.
A semiconductor device in which the semiconductor element is formed on the one surface of the substrate. 請求項１９に記載の半導体装置において、
前記基板の前記一面上に形成され、前記半導体素子を封止する樹脂をさらに含む半導体装置。 The semiconductor device according to claim 19,
A semiconductor device further comprising a resin formed on the one surface of the substrate and encapsulating the semiconductor element. 請求項２０に記載の半導体装置において、
前記低延性材料は、前記樹脂である半導体装置。 The semiconductor device according to claim 20, wherein
The semiconductor device in which the low ductility material is the resin. 請求項１９から２１いずれかに記載の半導体装置において、
前記基板の前記一面には、複数の前記半導体素子が並置された構成を有する半導体装置。 The semiconductor device according to any one of claims 19 to 21,
A semiconductor device having a configuration in which a plurality of the semiconductor elements are juxtaposed on the one surface of the substrate. 請求項１９から２１いずれかに記載の半導体装置において、
前記基板の前記一面には、複数の前記半導体素子が積層された構成を有する半導体装置。 The semiconductor device according to any one of claims 19 to 21,
A semiconductor device having a configuration in which a plurality of the semiconductor elements are stacked on the one surface of the substrate. 請求項１９から２３いずれかに記載の半導体装置において、
前記放熱板には、平面視で前記半導体素子と重なる箇所に、当該半導体素子に近づく方向に突出した凹部が形成された半導体装置。 24. The semiconductor device according to claim 19, wherein
The semiconductor device in which the heat sink has a recess protruding in a direction approaching the semiconductor element at a location overlapping the semiconductor element in plan view.
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