WO2019221406A1

WO2019221406A1 - Semiconductor package

Info

Publication number: WO2019221406A1
Application number: PCT/KR2019/004688
Authority: WO
Inventors: 김남철; 김종헌; 이응주; 여용운; 이창우
Original assignee: 주식회사 네패스
Priority date: 2018-05-15
Filing date: 2019-04-18
Publication date: 2019-11-21

Abstract

A semiconductor package according to an exemplary embodiment of the present disclosure may comprise: a semiconductor chip comprising a chip pad; a redistribution layer electrically connected to the chip pad of the semiconductor chip; an external connection terminal electrically connected to the redistribution layer; a sealing material covering the semiconductor chip and configured to fix the semiconductor and the redistribution layer; an adhesive film positioned on the upper surface of the sealing material; and a heat sink formed on the upper surface of the adhesive film and having a stepped portion at the periphery thereof.

Description

Semiconductor package

The technical idea of the present disclosure relates to a semiconductor package equipped with a heat sink, and more particularly, to a semiconductor package equipped with a heat sink capable of effectively dissipating heat generated from a semiconductor chip.

At the same time that semiconductor memory storage capacities are increased, electronic devices including semiconductor memory devices are required to be thin and light. Since the high-capacity miniaturized semiconductor package generates a large amount of heat from the semiconductor chip located inside the semiconductor package, heat dissipation to the outside of the semiconductor package is essential for securing operational stability and product reliability of the semiconductor package and the electronic device including the same. to be.

One of the technical problems to be solved by the technical idea of the present disclosure is to provide a semiconductor package capable of effectively dissipating heat generated from a semiconductor chip.

One of the technical problems to be solved by the technical idea of the present disclosure is to provide a semiconductor package that provides flexibility of cutting in a cutting process of separating a plurality of semiconductor packages into individual semiconductor packages.

One of the technical problems to be solved by the technical idea of the present disclosure is to provide a semiconductor package capable of visually providing information of the semiconductor package.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An external connection terminal electrically connected to the redistribution layer; An encapsulant configured to cover the semiconductor chip and to fix the semiconductor chip and the redistribution layer; An adhesive film positioned on an upper surface of the encapsulant; And a heat sink formed on an upper surface of the adhesive film and having a step at an edge thereof.

In example embodiments, the heat sink of the semiconductor package may include a first heat dissipation layer formed on an upper surface of the adhesive film; A second heat dissipation layer formed on an upper surface of the first heat dissipation layer; And a protrusion formed at a side of the first heat dissipation layer.

In example embodiments, the protrusion of the semiconductor package may be self-aligned with a side surface of the semiconductor package.

In example embodiments, the footprint of the first heat dissipation layer of the semiconductor package may be larger than the footprint of the second heat dissipation layer.

In an exemplary embodiment, the step of the heat sink of the semiconductor package may include a first step formed between the adhesive film and the first heat dissipation layer; And a second step formed between the first heat dissipation layer and the second heat dissipation layer.

In example embodiments, the semiconductor package further includes a heat dissipation molding part, wherein the heat dissipation molding part is formed on an upper surface of the adhesive film to cover an upper surface and a side surface of the first heat dissipation layer, and a side surface of the second heat dissipation layer. It covers, the upper surface is exposed, characterized in that covering the upper surface of the protrusion.

In example embodiments, the heat dissipation molding part of the semiconductor package exposes a side surface of the protrusion that is self-aligned with the side surface of the semiconductor package, and a footprint formed by the heat sink and the heat dissipation molding part is formed. It is characterized in that the same as the footprint (footprint) of the semiconductor package.

In example embodiments, the material of the heat dissipation molding part of the semiconductor package may be less rigid than the material of the protrusion part.

In example embodiments, the material of the heat dissipation molding part of the semiconductor package is characterized in that the epoxy molding compound (Epoxy Molding Compound).

In example embodiments, the height of the first step of the semiconductor package may be smaller than the height of the second step.

In example embodiments, the sum of the heights of the first step and the second step of the semiconductor package is about 25 percent to about 40 percent of the thickness of the semiconductor package.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An external connection terminal electrically connected to the redistribution layer; An encapsulant configured to cover the semiconductor chip and to fix the semiconductor chip and the redistribution layer; An adhesive film positioned on an upper surface of the encapsulant; A heat sink positioned on an upper surface of the adhesive film; And a heat dissipation molding part surrounding a side surface of the heat sink, wherein the height of the heat dissipation molding part is equal to the height of the heat sink, and an upper surface of the heat dissipation molding part is self-aligned with an upper surface of the heat sink to move the upper surface of the heat sink to the outside. A semiconductor package characterized by exposing is provided.

In example embodiments, a side surface of the heat dissipation molding part of the semiconductor package is self-aligned with a side surface of the semiconductor package, and a footprint formed by the heat dissipation molding part and the heat sink is a footprint of the semiconductor package. It is characterized by the same as (footprint).

In example embodiments, the heat sink of the semiconductor package may have a rectangular parallelepiped shape, and the footprint of the heat sink may be the same as the footprint of the semiconductor chip.

In example embodiments, the thickness of the heat sink of the semiconductor package is characterized in that from about 25 percent to about 40 percent of the thickness of the semiconductor package.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An external connection terminal electrically connected to the redistribution layer; An encapsulant configured to cover the semiconductor chip and to fix the semiconductor chip and the redistribution layer; An adhesive film positioned on an upper surface of the encapsulant; And a heat sink formed on an upper surface of the adhesive film, wherein the adhesive film extends to a side surface of the heat sink to cover a side surface of the heat sink, and the adhesive film is self-aligned with an upper surface of the heat sink. An upper surface of the heat sink is provided to provide a semiconductor package.

In example embodiments, the footprint formed by the heat sink of the semiconductor package and the adhesive film extending to the side surface of the heat sink may be the same as the footprint of the semiconductor package. .

In example embodiments, the footprint of the heat sink of the semiconductor package may be the same as the footprint of the semiconductor chip.

In example embodiments, the thickness of the heat sink and the adhesive film may be about 25 percent to about 40 percent of the thickness of the semiconductor package.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An external connection terminal electrically connected to the redistribution layer; A metal frame positioned on an upper surface of the redistribution layer; An encapsulant configured to fix the semiconductor chip and the metal frame; And a heat sink formed on the encapsulant, wherein the metal frame includes a cavity therein, and the semiconductor chip is positioned in a cavity inside the metal frame and surrounded by the metal frame. An inner wall of the frame and the semiconductor chip are spaced apart from each other by a predetermined distance, and the predetermined distance is 50 to 150 micrometers.

In example embodiments, the metal frame of the semiconductor package may include copper or aluminum.

In example embodiments, the outer wall of the metal frame of the semiconductor package may be disposed on the same plane as the side surface of the semiconductor package and exposed to the outside.

In example embodiments, the metal frame of the semiconductor package may have a rectangular parallelepiped shape having a cavity therein.

In example embodiments, the height of the metal frame of the semiconductor package may be the same as that of the semiconductor chip.

In example embodiments, an upper surface of the metal frame of the semiconductor package, an upper surface of the semiconductor chip, and an upper surface of the encapsulant may be positioned on the same plane.

In example embodiments, the height of the metal frame of the semiconductor package may be smaller than the height of the semiconductor chip.

In example embodiments, the metal frame of the semiconductor package may include a first region having an inner wall spaced apart from the semiconductor chip by a predetermined distance; And a second area formed in contact with the outer wall of the first area, wherein the maximum height of the first area is greater than the maximum height of the second area and the outer wall of the second area is exposed to the outside. .

In example embodiments, the material of the second region of the metal frame of the semiconductor package may be less rigid than the material of the first region.

In example embodiments, the maximum height of the first region of the metal frame of the semiconductor package may be equal to the maximum height of the semiconductor chip.

In example embodiments, the maximum height of the first region of the metal frame of the semiconductor package may be smaller than the maximum height of the semiconductor chip.

In an exemplary embodiment, the predetermined distance between the inner wall of the metal frame of the semiconductor package and the semiconductor chip is 100 micrometers.

In order to achieve the above object, in one embodiment of the present disclosure forming a metal frame having a cavity formed on the glass substrate; Mounting a semiconductor chip including a chip pad in a cavity of the metal frame on the glass substrate at a predetermined distance from an inner wall of the metal frame; Fixing and sealing the metal frame and the semiconductor chip through an encapsulant using a vacuum compression mold technique; Attaching a heat sink to an upper surface of the encapsulant; Removing the glass substrate; And forming a redistribution layer and an external connection terminal to be electrically connected to the chip pad of the semiconductor chip.

In example embodiments, the mounting of the semiconductor chip of the semiconductor package manufacturing method on the glass substrate may include mounting an inner wall of the semiconductor chip and the metal frame at a distance of 50 to 150 micrometers. Characterized in that.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A metal frame surrounding the semiconductor chip; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And a heat sink having an uneven structure formed on the encapsulant.

In example embodiments, the heat sink of the concave-convex structure of the semiconductor package may include a bottom portion of the encapsulant; And a plurality of protrusions protruding from the upper surface of the base and spaced apart from each other, wherein the protrusions are spaced apart from each other by 100 micrometers to 300 micrometers.

In example embodiments, the protrusion of the heat sink of the semiconductor package may have a convex shape.

In example embodiments, the protrusion of the semiconductor package may have a thickness between 40 and 60 percent of the thickness of the heat sink.

In example embodiments, the thickness of the base portion and the protrusion portion of the semiconductor package may be the same.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A metal frame surrounding the semiconductor chip; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And a heat sink formed on the encapsulant, wherein the heat sink comprises: a base portion of an upper portion of the encapsulant; A protrusion region including a plurality of protrusions protruding from the base portion; And a marking area provided on the base part, wherein the marking area in which information of the semiconductor chip is expressed.

In example embodiments, the marking area of the semiconductor package may form a plane, and the marking area may be dug into the marking area by a laser device to form information on the semiconductor chip.

In example embodiments, the plane of the marking area of the semiconductor package may be part of an upper surface of the base portion.

In example embodiments, the marking region of the semiconductor package may protrude from an upper surface of the base portion, and the upper surface of the marking region may be coplanar with an upper surface of the protrusions of the protrusion region.

In example embodiments, the height of the marking region of the semiconductor package protruding from the base and the height of the protrusion protruding from the base may be between 40 and 60 percent of the thickness of the heat sink.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A metal frame surrounding the semiconductor chip; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And a heat sink formed on the encapsulant, wherein the heat sink comprises: a base portion of an upper portion of the encapsulant; A first region including a plurality of first protrusions protruding from the base portion; And a second region including a plurality of second protrusions having a height greater than that of the first protrusions protruding from the base portion, wherein the first region includes a portion of the base portion and a portion of the first protrusion portion. It provides a semiconductor package characterized in that the information of the semiconductor chip is marked.

In example embodiments, the height of the first protrusions of the heat sink of the semiconductor package may be between 1/4 and 1/2 of the height of the second protrusions.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An external connection terminal electrically connected to the redistribution layer; An encapsulant covering the semiconductor chip and configured to fix the semiconductor chip and the redistribution layer; An adhesive film on the encapsulant; And a heat sink fixed on the encapsulant by the adhesive film, wherein the width of the heat sink is smaller than the width of the adhesive film.

In an exemplary embodiment, the upper surface of the semiconductor chip is exposed by the encapsulant, and the upper surface of the semiconductor chip and the upper surface of the encapsulant contact with the adhesive film.

In an exemplary embodiment, the upper surface of the semiconductor chip is covered by the encapsulant, and the upper surface of the encapsulant is in contact with the adhesive film.

In an exemplary embodiment, the footprint of the heat sink is greater than or equal to the footprint of the semiconductor chip.

In an exemplary embodiment, the thickness of the semiconductor chip is greater than or equal to the thickness of the heat sink.

In an exemplary embodiment, a protrusion extending from a side of the heat sink is included, and an outer side of the protrusion is self-aligned with a side of the semiconductor package.

In an exemplary embodiment, the material of the protrusion is different from the material of the heat sink.

In an exemplary embodiment, the material of the protrusion is characterized in that the rigidity is weaker than the material of the heat sink.

In an exemplary embodiment, the graining of the side surfaces of the heat sink is different as a result of the outer surface of the protrusion.

In an exemplary embodiment, when looking down the semiconductor package from above, at least one of the adhesive film and the encapsulant is exposed to the outside.

In an exemplary embodiment, the exposed area of the adhesive film and the encapsulant is 5% to 40% of the total area of the upper surface of the semiconductor package.

In an exemplary embodiment, the heat sink and the protrusion are enclosed to cover at least a portion of the side surface of the heat sink and at least a portion of the inner surface of the protrusion on the encapsulant, and an upper surface of the heat sink and the protrusion of the heat sink. And a heat dissipation molding part configured to expose an upper surface to the outside, wherein an outer surface of the heat dissipation molding part is self-aligned with a side surface of the semiconductor package.

In an exemplary embodiment, the sum of the footprints of the heat dissipation molding part, the heat sink, and the protrusion may be the same as the footprint of the semiconductor package.

In an exemplary embodiment, the heat dissipation molding part may cover only a portion of the side surface of the heat sink, and a step may be formed between the top surface of the heat sink and the top surface of the heat dissipation molding part.

In an exemplary embodiment, the heat dissipation molding part may cover all of the side surfaces of the heat sink and be configured to not expose the side surface of the heat sink to the outside.

In an exemplary embodiment, the heat sink may include a first heat dissipation layer; And a second heat dissipation layer on the first heat dissipation layer, wherein the footprint of the second heat dissipation layer is smaller than the footprint of the first heat dissipation layer.

In an exemplary embodiment, the protrusion may extend from a side surface of the first heat dissipation layer, and an outer side surface of the protrusion may be self-aligned with the side surface of the semiconductor package.

In an exemplary embodiment, the material of the first heat dissipation layer and the material of the second heat dissipation layer are different.

In an exemplary embodiment, the thickness of the first heat radiation layer is greater than the thickness of the second heat radiation layer.

In an exemplary embodiment, a heat dissipation molding configured to surround the side of the second heat dissipation layer to cover the side of the second heat dissipation layer on the top surface of the first heat dissipation layer, and to expose the top surface of the second heat dissipation layer. It characterized in that it further comprises a.

In an exemplary embodiment, the top surface of the first heat dissipation layer, the top surface of the second heat dissipation layer, and the second heat dissipation layer surround the side surface of the first heat dissipation layer to cover the side of the first heat dissipation layer. Characterized in that it further comprises; heat dissipation molding unit configured to expose the side of the.

In an exemplary embodiment, the adhesive film extends upwardly to the side surface of the heat sink and covers at least a portion of the side surface of the heat sink.

In an exemplary embodiment, the material of the adhesive film is characterized in that it comprises at least one of silver, aluminum, silicon dioxide, aluminum nitride, boron nitride.

In an exemplary embodiment, the adhesive film covers all of the side surfaces of the heat sink, and is configured to expose only the upper surface of the heat sink to the outside.

In an exemplary embodiment, the adhesive film covers only a portion of the side surface of the heat sink, and is configured to expose the upper surface of the heat sink and a portion of the side surface to the outside.

In an exemplary embodiment, the footprint of the adhesive film is smaller than the footprint of the semiconductor package.

In an exemplary embodiment, the sum of the footprint of the adhesive film and the heat sink is the same as the footprint of the semiconductor package, and the side of the adhesive film is self-aligned with the side of the semiconductor package.

In an exemplary embodiment, the heat sink is characterized in that the first metal is plated with a second metal different from the first metal.

In an exemplary embodiment, the first metal may include any one of copper and aluminum, and the second metal may include nickel.

In an exemplary embodiment, the second metal covers the top and bottom surfaces of the first metal, and when the heat sink is viewed from the side, the first metal and the second metal are exposed to the outside.

In an exemplary embodiment, the heat sink is formed after the second metal is plated on the first metal, and then formed separately.

In an exemplary embodiment, the second metal covers the top, bottom, and side surfaces of the first metal, and only the second metal is exposed to the outside when the heat sink is viewed from the side.

In an exemplary embodiment, the heat sink is formed by plating the second metal on the first metal after the first metal is individualized.

In an exemplary embodiment, the thickness of the first metal is 10 to 1000 times the thickness of the second metal.

In an exemplary embodiment, the heat sink comprises: a base; It is characterized in that the heat sink of the concave-convex structure shape including a; protruding upwardly projecting on the base.

In an exemplary embodiment, the distance between the protrusions may be 100 micrometers to 300 micrometers, and the thickness of the protrusions may be 100 micrometers to 300 micrometers.

In an exemplary embodiment, the thickness of the base is greater than the thickness of the protrusion.

The display device may include a marking area configured to display information of the semiconductor package on at least one of the base part and the protrusion part.

In order to achieve the above object, an embodiment of the present disclosure, a semiconductor chip including a chip pad; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An external connection terminal electrically connected to the redistribution layer; A metal frame on the redistribution layer; An encapsulant configured to fix the semiconductor chip and the metal frame onto the redistribution layer; An adhesive film on the encapsulant; And a heat sink fixed on the encapsulant by the adhesive film, wherein the metal frame includes a cavity formed by an inner wall of the metal frame, and the semiconductor chip is positioned in the cavity of the metal frame. Surrounded by the inner wall of the metal frame, wherein the semiconductor chip is spaced apart from the inner wall of the metal frame by 50 micrometers to 150 micrometers, and the encapsulant is provided in a space between the semiconductor chip and the inner wall of the metal frame. The width of the heat sink is smaller than the width of the adhesive film to provide a semiconductor package.

In an exemplary embodiment, the separation distance between the semiconductor chip and the inner wall of the metal frame is 100 micrometers.

In an exemplary embodiment, the metal frame may include a first area forming the inner wall of the metal frame; And a second region extending outwardly from the first region to form an outer surface of the metal frame, wherein the thickness of the first region is different from the thickness of the second region, and the first region is externally formed. Without exposure, the outer surface of the second region is characterized in that it is exposed to the outside.

In an exemplary embodiment, the thickness of the first region is greater than the thickness of the second region.

In an exemplary embodiment, the thickness of the first region is the same as the thickness of the semiconductor chip, and the upper surface of the semiconductor chip and the upper surface of the first region are in contact with the encapsulant.

In an exemplary embodiment, the thickness of the first region is the same as the thickness of the semiconductor chip, and the upper surface of the semiconductor chip and the upper surface of the first region are in contact with the adhesive film.

In an exemplary embodiment, the thickness of the first region is greater than the thickness of the semiconductor chip, and the thickness of the second region is the same as the thickness of the semiconductor chip.

In an exemplary embodiment, the thickness of the first region is greater than the thickness of the semiconductor chip, and the thickness of the second region is smaller than the thickness of the semiconductor chip.

In an exemplary embodiment, the material of the first area and the material of the second area are different.

In an exemplary embodiment, the material of the first region is less rigid than the material of the second region.

In an exemplary embodiment, the sum of the exposed areas of the adhesive film and the encapsulant is 5% to 40% of the area of the upper surface of the semiconductor package.

In an exemplary embodiment, the first heat dissipation layer and the second heat dissipation layer are covered to cover the top surface, the side surface of the first heat dissipation layer, and the side surface of the second heat dissipation layer, and to expose the top surface of the second heat dissipation layer. The heat dissipation molding unit; characterized in that it further comprises.

In an exemplary embodiment, the adhesive film is extended upward to the side of the heat sink, characterized in that to cover at least a portion of the side of the heat sink.

In an exemplary embodiment, the adhesive film is characterized in that it comprises at least one of silver, aluminum, silicon dioxide, aluminum nitride, boron nitride.

In an exemplary embodiment, the adhesive film is configured to cover only a portion of the side of the heat sink, and to expose the upper surface and a portion of the side of the heat sink to the outside.

According to the embodiments of the present disclosure, it is possible to provide a semiconductor package having excellent heat dissipation performance that effectively discharges heat generated from a semiconductor chip to the outside.

According to embodiments of the present disclosure, it is possible to provide ease of cutting in a process of cutting semiconductor packages into individual semiconductor packages.

According to embodiments of the present disclosure, due to a narrow separation distance between the metal frame and the semiconductor chip in the semiconductor package, not only the heat dissipation performance may be improved, but also the productivity may be increased by narrowing the intervals between the semiconductor chips in the semiconductor package manufacturing process. .

According to embodiments of the present disclosure, information of a semiconductor chip in a semiconductor package may be visually provided due to marking of a heat sink mounted on the semiconductor package.

1A and 1B are cross-sectional views illustrating a basic structure of a semiconductor package according to an embodiment of the present disclosure.

2A is a plan view illustrating a group of heat sinks in which a plurality of heat sinks are connected at a predetermined distance, according to an embodiment of the present disclosure.

2B and 2C are side cross-sectional views when the population of heat sinks of FIG. 2A, which is an embodiment of the present disclosure, is cut along a straight line a_I and a straight line b_I, respectively.

3A and 3B are side cross-sectional views when a plurality of semiconductor packages mounted with the heat sink of FIG. 2A, which is an embodiment of the present disclosure, are cut along the straight lines a_I and b_I of FIG. 2A, respectively.

FIG. 4A is a perspective view of an individual semiconductor package generated by cutting a plurality of semiconductor packages on which the population of the heat sinks of FIG. 2A, which is an embodiment of the present disclosure, is mounted.

4B and 4C are side cross-sectional views when the semiconductor package according to the exemplary embodiment of the present disclosure is cut along the straight lines c_I and the straight lines d_I of FIG. 4A, respectively.

5A is a plan view illustrating a group of heat sinks in which a plurality of heat sinks are connected at a predetermined distance, according to an embodiment of the present disclosure.

5B and 5C are side cross-sectional views when the population of heat sinks of FIG. 5A, which is an embodiment of the present disclosure, is cut along the straight lines c_I and d_I of FIG. 5A, respectively.

6A and 6B are side cross-sectional views of a plurality of semiconductor packages on which the population of heat sinks mounted according to an embodiment of the present disclosure are cut along the straight lines c_I and d_I of FIG. 5A, respectively.

FIG. 7A is a perspective view of an individual semiconductor package generated by cutting a plurality of semiconductor packages on which the population of heat sinks of FIG. 5A, which is an embodiment of the present disclosure, is mounted.

7B and 7C are cross-sectional side views when a semiconductor package according to an exemplary embodiment of the present disclosure is cut along a straight line e_I and a straight line f_I of FIG. 7A, respectively.

FIG. 8A is a plan view illustrating a group of heat sinks in which a heat dissipation molding part is filled in the group of heat sinks of FIG. 2A.

8B and 8C are side cross-sectional views when a plurality of semiconductor packages on which the population of heat sinks of FIG. 8A mounted according to an embodiment of the present disclosure are cut along the straight lines g_I and h_I of FIG. 8A, respectively.

FIG. 9A is a perspective view of an individual semiconductor package generated by cutting a plurality of semiconductor packages on which the population of heat sinks of FIG. 8A, which is an embodiment of the present disclosure, is mounted.

9B and 9C are cross-sectional side views when a semiconductor package according to an exemplary embodiment of the present disclosure is cut along a straight line i_I and a straight line j_I of FIG. 9A, respectively.

10A is a perspective view illustrating a plurality of heat sinks according to an embodiment of the present disclosure.

FIG. 10B is a plan view illustrating a group of heat sinks filled with heat dissipation molding parts of the heat sinks of FIG. 10A according to an embodiment of the present disclosure.

FIG. 11A is a perspective view of an individual semiconductor package generated by cutting a plurality of semiconductor packages on which the population of the heat sinks of FIG. 10B, which is an embodiment of the present disclosure, is mounted.

FIG. 11B is a side cross-sectional view when the semiconductor package according to the exemplary embodiment is cut along the straight line k_I of FIG. 11A.

12A is a plan view illustrating a group of heat sinks according to an embodiment of the present disclosure.

12B is a side cross-sectional view when the population of heat sinks of FIG. 12A, which is an embodiment of the present disclosure, is cut along the straight line l_I of FIG. 12A.

FIG. 13 is a side cross-sectional view when the semiconductor package according to the exemplary embodiment of the present disclosure is cut along the straight line l_I of FIG. 12A, respectively.

14 is a flowchart illustrating a method of manufacturing a semiconductor package according to one embodiment of the present disclosure.

15 is a block diagram schematically illustrating an electronic system including a semiconductor package according to an embodiment of the present disclosure.

16 is a cross-sectional view illustrating a basic structure of a semiconductor package according to an embodiment of the present disclosure.

FIG. 17 is a plan view of a semiconductor package according to another exemplary embodiment, taken along the straight line a of FIG. 16.

18 is a cross-sectional view illustrating a structure of a semiconductor package according to another embodiment of the present disclosure.

19 is a cross-sectional view illustrating a structure of a semiconductor package according to another embodiment of the present disclosure.

20 is a cross-sectional view illustrating a structure of a semiconductor package according to another embodiment of the present disclosure.

21 is a cross-sectional view illustrating a structure of a semiconductor package according to another embodiment of the present disclosure.

FIG. 22 is a view for explaining one step of a method of manufacturing a semiconductor package for attaching a metal frame onto a glass substrate according to one embodiment of the present disclosure.

FIG. 23 is a plan view of a plurality of metal frames attached on a glass substrate as an embodiment of the present disclosure. FIG.

24 is a view for explaining one step of a method for manufacturing a semiconductor package for mounting a semiconductor chip on a glass substrate, which is an embodiment of the present disclosure.

FIG. 25 is a view illustrating one step of a method of manufacturing a semiconductor package for covering and sealing a semiconductor chip and a metal frame with an encapsulant according to an embodiment of the present disclosure.

FIG. 26 is a view for explaining one step of a method of manufacturing a semiconductor package for mounting an encapsulant on a glass substrate using a vacuum crimp mold technique, which is an embodiment of the present disclosure.

FIG. 27 is a view illustrating one step of a method of manufacturing a semiconductor package for attaching a heat sink to a semiconductor package according to an embodiment of the present disclosure.

28 is a view illustrating a shape of a heat sink according to an embodiment of the present disclosure.

FIG. 29 is a diagram illustrating one step of a method of manufacturing a semiconductor package for removing a glass substrate and inverting the semiconductor package according to one embodiment of the present disclosure.

30 is a view for explaining a step of manufacturing a semiconductor package for forming a redistribution layer and an external connection terminal according to an exemplary embodiment of the present disclosure.

31 and 32 are diagrams illustrating one step of a semiconductor package manufacturing method of cutting a plurality of semiconductor packages into individual packages according to one embodiment of the present disclosure.

33 is a block diagram schematically illustrating an electronic system including a semiconductor package according to an embodiment of the present disclosure.

34 is a cross-sectional view illustrating a basic structure of a semiconductor package according to an embodiment of the present disclosure.

35 is a cross-sectional view illustrating a structure of a semiconductor package according to another embodiment of the present disclosure.

36 and 37 are cross-sectional views illustrating a structure of a heat sink of a semiconductor package according to an embodiment of the present disclosure.

38 is a plan view illustrating a structure of a heat sink of a semiconductor package according to an embodiment of the present disclosure.

39 and 40 are plan views illustrating heat sinks in which information of a semiconductor chip is marked according to an exemplary embodiment of the present disclosure.

41 is a plan view illustrating a heat sink in which information of a semiconductor chip is marked according to another embodiment of the present disclosure.

42 is a plan view illustrating a heat sink in which information of a semiconductor chip is marked according to another embodiment of the present disclosure.

FIG. 43 is a view illustrating one step of a method of manufacturing a semiconductor package for attaching a metal frame onto a glass substrate according to one embodiment of the present disclosure.

44 is a view for explaining one step of a semiconductor package manufacturing method for mounting a semiconductor chip on a glass substrate according to one embodiment of the present disclosure.

FIG. 45 is a view illustrating one step of a method of manufacturing a semiconductor package for covering and sealing a semiconductor chip and a metal frame with an encapsulant according to an embodiment of the present disclosure.

FIG. 46 is a view illustrating one step of a method of manufacturing a semiconductor package for attaching a heat sink to a semiconductor package according to an embodiment of the present disclosure.

FIG. 47 is a diagram for describing one step of a semiconductor package manufacturing method of removing a glass substrate and inverting the semiconductor package according to one embodiment of the present disclosure.

48 is a view illustrating one step of a method of manufacturing a semiconductor package for forming a redistribution layer and an external connection terminal according to an embodiment of the present disclosure.

FIG. 49 illustrates a step of a method of manufacturing a semiconductor package for cutting a plurality of semiconductor packages into individual packages according to an embodiment of the present disclosure.

50 is a block diagram schematically illustrating an electronic system including a semiconductor package according to an embodiment of the present disclosure.

51 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

52 and 53 are cross-sectional views of semiconductor packages according to an embodiment of the present disclosure.

54 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

55 and 56 are cross-sectional views of semiconductor packages according to an embodiment of the present disclosure.

57 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

58 is a plan view of a group of heat sinks in which a plurality of heat sinks are connected, which is an embodiment of the present disclosure.

FIG. 59 is a cross sectional view at A_IV-A_IV in FIG. 58 of a population of heatsinks that is one embodiment of the present disclosure.

60 is a cross-sectional view at B_IV-B_IV of FIG. 58 of a population of heatsinks that is one embodiment of the present disclosure.

FIG. 61 is a cross-sectional view of the semiconductor packages of A_IV-A_IV of FIG. 58, in which a group of heat sinks is mounted, which is an embodiment of the present disclosure.

FIG. 62 is a cross-sectional view taken along line B-IV-B_IV of FIG. 58 of a plurality of semiconductor packages mounted with a group of heat sinks according to an embodiment of the present disclosure.

63 is an enlarged view of a side of a semiconductor package according to an embodiment of the present disclosure.

64 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

65 and 66 are perspective views of semiconductor packages according to an embodiment of the present disclosure.

67 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

68 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

FIG. 69 is a plan view of a group of heat sinks to which a plurality of heat sinks are connected according to an embodiment of the present disclosure. FIG.

FIG. 70 is a cross-sectional view of C_IV-C_IV of FIG. 69 of a plurality of semiconductor packages mounted with a group of heat sinks according to an embodiment of the present disclosure.

FIG. 71 is a cross-sectional view of D_IV-D_IV of FIG. 69 of a plurality of semiconductor packages mounted with a group of heat sinks according to an embodiment of the present disclosure.

72 and 73 are perspective views of semiconductor packages according to an embodiment of the present disclosure.

74 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

75 is a sectional view of a semiconductor package according to an embodiment of the present disclosure.

76 and 77 are cross-sectional views of semiconductor packages according to an embodiment of the present disclosure.

78 illustrates a heat sink according to an embodiment of the present disclosure.

79 is a view illustrating a manufacturing process of a heat sink according to an embodiment of the present disclosure.

80 illustrates a heat sink according to an embodiment of the present disclosure.

81 is a view illustrating a manufacturing process of a heat sink according to an embodiment of the present disclosure.

82 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

83 and 84 are cross-sectional views of heat sinks according to an embodiment of the present disclosure.

85 to 87 are plan views of heat sinks having a concave-convex structure including a marking area in which information of a semiconductor package according to an exemplary embodiment of the present disclosure is displayed.

88 to 92 are views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

93 is a block diagram schematically illustrating an electronic system including a semiconductor package according to an embodiment of the present disclosure.

94 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

95 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

96 is a plan view at line a_V of FIG. 94 of a semiconductor package according to an embodiment of the present disclosure.

97 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

98 and 99 are cross-sectional views of semiconductor packages according to an embodiment of the present disclosure.

100 and 101 are cross-sectional views of semiconductor packages according to example embodiments.

102 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

103 is a plan view of a group of heat sinks in which a plurality of heat sinks are connected, which is an embodiment of the present disclosure.

FIG. 104 is a cross-sectional view at line b_V of FIG. 103 of a population of heatsinks that is one embodiment of the disclosure.

FIG. 105 is a cross-sectional view at line c_V of FIG. 103 of a population of heatsinks that is one embodiment of the disclosure.

FIG. 106 is a cross-sectional view taken along the straight line b_V of FIG. 103 of a plurality of semiconductor packages mounted with a population of heat sinks, which is an embodiment of the disclosure.

FIG. 107 is a cross-sectional view taken along the line c_V of FIG. 103 of a plurality of semiconductor packages mounted with a group of heat sinks, which is an embodiment of the present disclosure.

108 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

109 and 110 are perspective views of semiconductor packages according to an embodiment of the present disclosure.

111 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

112 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

113 is a perspective view of a semiconductor package according to an embodiment of the present disclosure.

114 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

115 is a sectional view of a semiconductor package according to an embodiment of the present disclosure.

116 is a view illustrating a heat sink according to an embodiment of the present disclosure.

117 is a view illustrating a manufacturing process of a heat sink according to an embodiment of the present disclosure.

118 is a view illustrating a heat sink according to an embodiment of the present disclosure.

119 is a view illustrating a manufacturing process of a heat sink according to an embodiment of the present disclosure.

120 and 121 are cross-sectional views of semiconductor packages according to an embodiment of the present disclosure.

122 and 123 are cross-sectional views of a heat sink according to an embodiment of the present disclosure.

124 to 126 are plan views of heat sinks having a concave-convex structure including a marking area in which information of a semiconductor package according to an exemplary embodiment of the present disclosure is displayed.

127 to 135 illustrate a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

136 is a block diagram schematically illustrating an electronic system including a semiconductor package according to an embodiment of the present disclosure.

A semiconductor package according to an embodiment of the present disclosure includes a semiconductor chip including a chip pad; A redistribution layer electrically connected to the chip pad of the semiconductor chip; An external connection terminal electrically connected to the redistribution layer; An encapsulant configured to cover the semiconductor chip and to fix the semiconductor chip and the redistribution layer; An adhesive film positioned on an upper surface of the encapsulant; And a heat sink formed on an upper surface of the adhesive film and having a step at an edge thereof.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the inventive concept may be modified in many different forms, and the scope of the inventive concept should not be construed as limited by the embodiments set forth below. Embodiments of the inventive concept are preferably interpreted as being provided to more fully explain the inventive concept to those of ordinary skill in the art. Like numbers refer to like elements all the time. Furthermore, the various elements and regions in the drawings are schematically drawn. Accordingly, the inventive concept is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the inventive concept, the first component may be referred to as the second component, and conversely, the second component may be referred to as the first component.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the expression “comprises” or “having” is intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art, including technical terms and scientific terms. Also, as used in the prior art, terms as defined in advance should be construed to have a meaning consistent with what they mean in the context of the technology concerned, and in an overly formal sense unless explicitly defined herein. It will be understood that it should not be interpreted.

1A and 1B are cross-sectional views illustrating a basic structure of a semiconductor package according to an embodiment of the present disclosure. The semiconductor package 100_I may be a fan-out wafer level package (FOWLP) or a panel level package (PLP).

1A and 1B, a semiconductor package 100_I according to an exemplary embodiment may include a semiconductor chip 101_I, an encapsulant 102_I surrounding a semiconductor chip, a redistribution layer 103_I, and an external connection terminal 104_I. ), An adhesive film 105_I, and a heat sink 106_I. The semiconductor package 100_I may be a semiconductor package having a wafer level package (WLP) structure, and specifically, may be a semiconductor package having a fan-out wafer level package structure. The overall thickness of the semiconductor package may be about 1.1 millimeters to about 1.4 millimeters. However, the present invention is not limited to the above thickness and may have various thicknesses.

The semiconductor chip 101_I illustrated in FIG. 1A may include a plurality of individual devices of various types. For example, the plurality of individual devices may be a variety of microelectronic devices, for example a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale (LSI). image sensors such as integration (CIS), CMOS imaging sensors (CIS), and the like, micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.

In example embodiments, the semiconductor chip 101_I may be a memory semiconductor chip. The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a phase-change random access memory (PRAM), or a magneto-resistive random access memory (MRAM). ), Or a nonvolatile memory semiconductor chip such as ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM).

Alternatively, in example embodiments, the semiconductor chip 101_I may be a logic chip. For example, the semiconductor chip 101_I may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

1A and 1B, the semiconductor package 100_I is illustrated as including one semiconductor chip 101_I, but the semiconductor package 100_I may include two or more semiconductor chips 101_I. Two or more semiconductor chips 101_I included in the semiconductor package 100_I may be the same kind of semiconductor chip or different types of semiconductor chips. In some embodiments, the semiconductor package 100_I may be a system in package (SIP) in which different types of semiconductor chips are electrically connected to each other and operate as one system.

In example embodiments, the semiconductor chip 101_I may include a lower surface 111_I and an upper surface 112_I facing the lower surface 111_I. The semiconductor chip 101_I may include a chip pad 113_I on the bottom surface 111_I. The chip pad 113_I may be electrically connected to a plurality of individual elements of various kinds formed on the semiconductor chip 101_I. The chip pad 113_I may have a thickness between about 0.5 micrometers and about 1.5 micrometers. In addition, although not illustrated in FIG. 1A, the semiconductor chip 101_I may include a passivation layer covering the lower surface 111_I.

1A and 1B, the encapsulant 102_I may serve to surround and protect the semiconductor chip 101_I. In addition, the encapsulant 102_I may fix the semiconductor chip 101_I and the redistribution layer 103_I described later. The encapsulant 102_I may be formed of, for example, a silicone-based material, a thermosetting material, a thermoplastic material, a UV treatment material, or the like. For example, the encapsulant 102_I may be formed of a polymer such as resin, for example, epoxy. It may be formed of an molding compound (Epoxy Molding Compound, EMC).

The encapsulant 102_I may cover at least a portion of the semiconductor chip 101_I. As illustrated in FIG. 1A, the encapsulant 102_I may cover the upper surface 112_I and the side surface of the semiconductor chip 101_I. In this case, a height difference between the top surface 112_I of the semiconductor chip 101_I and the top surface of the encapsulant 102_I may be about 1 micrometer to about 10 micrometers.

However, in some embodiments of the present disclosure, as shown in FIG. 1B, the encapsulant 102_I covers the side surface of the semiconductor chip 101_I, but the upper surface 112_I of the semiconductor chip 101_I may be exposed. have. As the upper surface 112_I of the semiconductor chip 101_I is exposed, the size of the semiconductor package 100_I may be reduced, and heat generated from the semiconductor chip 101_I does not pass through the encapsulant 102_I. The adhesive film 105_I positioned on the top surface 112_I of the semiconductor chip 101_I to be described later and the heat sink 106_I positioned on the top surface of the adhesive film 105_I may be sequentially discharged to the outside.

1A and 1B, the semiconductor package 100_I may include an adhesive film 105_I. The adhesive film 105_I may contact the top surface 112_I of the semiconductor chip 101_I or the top surface of the encapsulant 102_I. The adhesive film 105_I may include an epoxy resin having excellent adhesion to the encapsulant 102_I and the semiconductor chip 101_I. In addition, a filler having excellent thermal conductivity may be included, for example, silver, aluminum, silicon dioxide, aluminum nitride, boron nitride, or the like, and may include aluminum oxide having thermal conductivity to maintain rigidity. The adhesive film 105_I may have adhesive properties by itself, and may also be provided by being bonded with a separate thermal conductive adhesive tape. The adhesive tape may be a double-sided adhesive tape. The thickness of the adhesive film 105_I formed on the semiconductor package 100_I may be about 5 micrometers to about 20 micrometers, and more specifically, about 10 micrometers to about 14 micrometers.

1A and 1B, the semiconductor package 100_I may include a redistribution layer 103_I. The redistribution layer 103_I may be formed on the bottom surface 111_I of the semiconductor chip 101_I to electrically connect the chip pad 113_I and the external connection terminal 104_I of the semiconductor chip 101_I. The semiconductor package 100_I may form an external connection terminal 104_I in a region outside the footprint of the bottom surface 111_I of the semiconductor chip 101_I through the redistribution layer 103_I. An efficient external connection terminal 104_I may be disposed in the semiconductor package 100_I through the redistribution layer 103_I.

Although not shown in FIGS. 1A and 1B, the redistribution layer 103_I may include a wiring pattern and an insulation pattern. The wiring pattern may be electrically connected to the chip pad 113_I formed on the bottom surface 111_I of the semiconductor chip 101_I, and may provide an electrical connection path for electrically connecting the chip pad 113_I to an external device. have. The insulating pattern serves to protect the wiring pattern electrically connected to the chip pad 113_I from external shock and to prevent a short circuit. For example, the insulating pattern may include a photosensitive material such as polyimide or epoxy. However, the present invention is not limited thereto and may be made of a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

1A and 1B, the semiconductor package may include an external connection terminal 104_I. The external connection terminal 104_I may be electrically connected to a lower surface of the redistribution layer 103_I. The semiconductor package 100_I may be electrically connected to an external device, such as a system board or a main board, by the external connection terminal 104_I. The external connection terminal 104_I may include solder balls, as shown in FIGS. 1A and 1B. The solder ball may include at least one of tin, silver, copper, and aluminum. In addition, the solder ball may have a ball shape shown in FIGS. 1A and 1B, but is not limited thereto and may have various shapes such as a cylinder, a polygonal column, and a polyhedron.

1A and 1B, the semiconductor package 100_I may include a heat sink 106_I. The heat sink 106_I may be positioned on the adhesive film 105_I and mounted on the semiconductor package 100_I. The heat sink 106_I may efficiently discharge heat generated from the semiconductor chip 101_I in the semiconductor package 100_I to the outside.

More specifically, referring to FIG. 1A, heat generated from the semiconductor chip 101_I in the semiconductor package 100_I may be formed by the top surface 112_I of the semiconductor chip 101_I, the encapsulant 102_I, and the adhesive film 105_I. ) And the heat sink 106_I may be sequentially emitted to the outside. In addition, referring to FIG. 1B, the heat generated from the semiconductor chip 101_I in the semiconductor package 100_I sequentially orders the top surface 112_I, the adhesive film 105_I, and the heat sink 106_I of the semiconductor chip 101_I. It can be emitted to the outside via. In the case of FIG. 1B, since the encapsulant 102_I is not formed between the upper surface 112_I of the semiconductor chip 101_I and the adhesive film 105_I, the heat is moved in the movement path of the heat generated in the semiconductor chip 101_I. The resistance may be smaller than in the case of FIG. 1A, whereby the effect of heat radiation may be better.

The heat sink 106_I mounted on the semiconductor package 100_I may include a metal material, a ceramic material, a carbon material, and a polymer material having various thermal conductivity.

More specifically, the metal-based heat sink 106_I includes aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and about 380 W / m. Metal-based materials such as copper (Cu) with a thermal conductivity of K, nickel (Ni) with a thermal conductivity of about 90 W / m · K, and silver (Ag) with a thermal conductivity of about 410 W / m · K. have.

The ceramic heat sink 106_I includes boron nitride (BN) having a thermal conductivity of about 1800 W / m · K, aluminum nitride (AlN) having a thermal conductivity of about 320 W / m · K, and about 30 W / m. Aluminum oxide (Al ₂ O ₃ ) with a K thermal conductivity, silicon carbide (SiC) with a thermal conductivity of about 480 W / m · K, and beryllium oxide (BeO) with a thermal conductivity of about 270 W / m · K It may include a ceramic-based material.

The carbon-based heat sink 106_I includes diamond having a thermal conductivity of about 2500 W / m · K, carbon fiber having a thermal conductivity of about 100 W / m · K, and about 5 W / m · K to about 1950 W / m. Carbon-based materials such as graphite having a thermal conductivity of K, carbon nanotubes having a thermal conductivity of about 1.5 W / m · K to about 3500 W / m · K, and graphene having a thermal conductivity of about 5000 W / m · K. It may include.

The heat sink 106_I of the polymer material may include a polymer material such as polyethylene having an ultra high molecular weight having a thermal conductivity of about 45 W / m · K to about 100 W / m · K.

However, the heat sink 106_I is not limited to the metal-based material, the cerium-based material, the carbon-based material, and the polymer-based material, and may include a combination of the materials or other materials not shown above.

1A and 1B, the heat sink 106_I mounted in the semiconductor package 100_I may be formed at various heights. In one embodiment of the present disclosure, the thickness v_I of the heat sink 106_I may account for about 25 percent to about 40 percent of the thickness of the semiconductor package. In an embodiment of the present disclosure, since the thickness of the semiconductor package 100_I may be about 1.1 millimeters to about 1.4 millimeters, the thickness v_I of the heat sink 106_I may be about 280 micrometers to about 560 micrometers. Can be.

1A and 1B, the heat sink 106_I formed in the semiconductor package 100_I may include a region D_I having a step at an edge thereof. There may be a plurality of regions D_I having a step in one semiconductor package 100_I. The area D_I having the step will be described in more detail later.

FIG. 2A is a plan view illustrating a group 200_I of heat sinks in which a plurality of heat sinks 106_I are connected at a predetermined distance. Referring to FIG. 2A, the individual heat sinks 106_I are connected to each other with the respective heat sinks 106_I having a predetermined distance t_I in four directions of the side surfaces of the individual heat sinks 106_I. The cluster 200_I of heat sinks may be formed. The individual heat sinks 106_I may be connected to each other by a connection area S_I having the predetermined distance t_I and a predetermined width w_I between the individual heat sinks 106_I shown in FIG. 2A. As illustrated in FIG. 2A, two connection regions S_I may be formed on one side of the heat sink 106_I, but the number is not limited thereto. For example, one connection area S_I may be formed on one side of the heat sink 106_I, or two or more connection areas S_I may be formed.

The group of heat sinks 200_I may be fixed to the upper surface of the adhesive film of the plurality of semiconductor packages before the plurality of semiconductor packages are cut into individual semiconductor packages. Since the heat sinks 106_I form the group 200_I of the heat sinks by the connection region S_I, the heat sinks 106_I may be easily aligned at an appropriate position on the upper surface of each semiconductor package. . After placing the plurality of heat sinks 200_I on the top surface of the adhesive film 105_I and applying heat and pressure to the adhesive film 105_I, the adhesive film 105_I is the collection of heat sinks 200_I. It may be fixed to be mounted on the plurality of the semiconductor package in a stable manner.

When the group of the plurality of heat sinks 200_I is stably mounted on the plurality of semiconductor packages, the plurality of semiconductor packages may be cut into individual semiconductor packages through a cutting process. Referring to FIG. 2A, the cutting line L_I may be formed in a straight line on the connection area S_I having the predetermined distance t_I and the predetermined width w_I of the plurality of heat sinks 200_I. Can be. Since the cutting line L_I is formed on the connection area S_I having the predetermined distance t_I and the predetermined width w_I, the smaller the thickness and width w_I of the connection area S_I are, the plurality of the plurality of connection lines S_I. A cutting process of cutting the plurality of semiconductor packages on which the group of heat sinks 200_I are mounted into individual semiconductor packages (100_I of FIG. 1A) may be easy.

2B is a side cross-sectional view when the population of the heat sinks 200_I of FIG. 2A, according to an embodiment of the present disclosure, is cut along a straight line a_I, and FIG. 2C is a collection of the heat sinks of FIG. 2A, which is an embodiment of the disclosure, It is a side cross-sectional view when 200_I) is cut along the straight line b_I.

2A to 2C, the group of heat sinks 200_I, which is an embodiment of the present disclosure, may include a first heat dissipation layer 210_I and an upper portion of the first heat dissipation layer 210_I formed on an upper surface of the adhesive film. It may include a second heat dissipation layer 220_I formed in.

The first heat dissipation layers 210_I may be connected to each other by a connection region S_I having a predetermined distance t_I and a predetermined width w_I. The connection area S_I may be made of the same material as the first heat dissipation layer 210_I. However, other materials may be included for ease of cutting process. In exemplary embodiments, the connection region S_I may include a metal material, a ceramic material, a carbon material, and a polymer material. In addition, the thickness of the connection region S_I may be substantially the same as the thickness of the first heat dissipation layer 210_I. Although the first heat dissipation layer 210_I may have a rectangular parallelepiped shape as shown in FIG. 2A, the first heat dissipation layer 210_I may have various shapes without being limited to the shape.

The second heat dissipation layer 220_I may be formed on the first heat dissipation layer 210_I. The second heat dissipation layer 220_I may be substantially the same as the heat dissipation material of the first heat dissipation layer 210_I. 2A through 2C, the footprint of the second heat dissipation layer 220_I may be smaller than the footprint of the first heat dissipation layer 210_I.

The first heat dissipation layer 210_I and the second heat dissipation layer 220_I may have substantially the same height, but are not limited thereto and may have different heights. The sum of the heights of the first heat dissipation layer 210_I and the second heat dissipation layer 220_I may be about 280 micrometers to about 560 micrometers, and may be about 25 percent to about 40 percent of the total semiconductor package thickness. .

FIG. 3A is a side cross-sectional view of a plurality of semiconductor packages on which the population of the heat sinks 200_I of FIG. 2A mounted according to an embodiment of the present disclosure are cut along the straight line a of FIG. 2A. FIG. 3B is a side cross-sectional view of a plurality of semiconductor packages on which the population of heat sinks 200_I of FIG. 2A mounted according to an embodiment of the present disclosure are cut along the straight line b of FIG. 2A.

3A and 3B, the heat sink 106_I may include a first step 310_I and a second step 320_I.

The first step 310_I is between the adhesive film 105_I and the first heat dissipation layer 210_I at a portion where the connection region (S of FIG. 2A) is not formed at the side of the first heat dissipation layer 210_I. It can be formed by the difference of the height of.

More specifically, referring to FIG. 3A, a plurality of semiconductor packages 300_I on which the heat sinks 200_I are mounted may be cut along a straight line a_I passing through a portion where the connection region S_I is not formed. The heat sinks 106_I may be spaced apart from each other by a predetermined distance t_I. The footprint of the first heat dissipation layer 210_I is smaller than the footprint of the adhesive film 105_I due to the predetermined distance t_I caused by the connection region S_I not being formed. Can be small. Therefore, due to the difference between the footprint of the first heat dissipation layer 210_I and the adhesive film 105_I and the height of the first heat dissipation layer 210_I, the adhesive film 105_I and the first heat dissipation layer The first step 310_I may be formed between 210_I.

Referring to FIG. 3B, when the plurality of semiconductor packages 300_I on which the population of heat sinks 200_I are mounted are cut along a straight line b_I (FIG. 2A) passing through a portion in which the connection region S_I is formed, the individual semiconductor packages 300_I are separated. The heat sinks may be connected to each other by the connection region S_I. Therefore, the first step 310_I may not be formed in the portion where the connection region S_I is formed.

3A and 3B, the second step 320_I is defined as a difference between the footprints of the first heat dissipation layer 210_I and the second heat dissipation layer 220_I and the height of the second heat dissipation layer 220_I. It can be formed by. The heat sink is caused by the difference between the footprint of the first heat dissipation layer 210_I and the second heat dissipation layer 220_I and the second step 320_I formed by the height of the second heat dissipation layer 220_I. 106_I may have the shape of an inverted T.

3A and 3B, the plurality of semiconductor packages 300_I on which the plurality of heat sinks 106_I are mounted may be cut in the direction of the arrow shown in FIGS. 3A and 3B. More specifically, the cutting lines of FIGS. 2A and L_I of the plurality of semiconductor packages 300_I may be formed at the center of the predetermined distance t_I of FIG. 3A and at the center of the connection region S_I of FIG. 3B. A plurality of semiconductor packages 300_I may be separated into individual semiconductor packages along the cutting line L_I.

Referring to FIG. 3A, the cutting of the plurality of semiconductor packages 300_I at the portion where the connection region S_I is not formed may be performed by using the adhesive film 105_I, the encapsulant 102_I, and the redistribution layer 103_I. It can be done sequentially. Therefore, since the cutting of the connection region S_I is not necessary, an individual package may be formed with less external force in the cutting process of the semiconductor package. In more detail, the encapsulant 102_I and the material of the redistribution layer 103_I may include an epoxy molding compound having a relatively weaker rigidity than the material of the connection region S_I. The cutting blade of the material can be selected.

Referring to FIG. 3B, the cutting of the plurality of semiconductor packages 300_I at the portion where the connection region S_I is formed may include the connection region S_I, the adhesive film 105_I, the encapsulant 102_I, and the redistribution layer. This may be done sequentially through 103_I. As the rigidity of the material of the connection region S_I is weak and the width w_I and the thickness of the connection region S_I are smaller, the connection region S_I is easily cut by the cutting blade in the cutting process of the semiconductor package. Can be.

An embodiment of the present disclosure connects the plurality of heat sinks 106_I through the connection area S_I at the side of the heat sink 106_I to form the collective 200_I of the heat sinks. Heat sinks 106_I can be produced in a single process. In addition, since the heat sinks 106_I produced in the above process are integrally coupled, the heat sinks 106_I may be more stably mounted on the top surfaces of the plurality of semiconductor packages on which the semiconductor chips are mounted. In addition, the group of heat sinks 200_I may be integrally handled, thereby providing ease of processing, transportation, and cutting of the group of heat sinks 200_I.

3A and 3B, the connection region S_I may exist only at a portion of the side surface of the heat sink 106_I. Therefore, the footprint of the first heat dissipation layer 210_I may be smaller than the footprint of the adhesive film 105_I, and the height of the first heat dissipation layer 210_I may be reduced by the height of the first heat dissipation layer 210_I. ) And a first step 310_I may be formed between the first heat dissipation layer 210_I.

FIG. 4A is a perspective view of an individual semiconductor package 400_I generated by cutting a plurality of semiconductor packages in which the population 200_I of the heat sinks of FIG. 2A are mounted by a cutting process. 4B is a side cross-sectional view when the semiconductor package 400_I, which is an embodiment of the present disclosure, is cut along the straight line c_I of FIG. 4A, and FIG. 4C is a straight line of FIG. 4A, wherein the semiconductor package 400_I is an embodiment of the present disclosure. Side cross-sectional view when cut according to d_I.

4A to 4C, the semiconductor package 400_I includes the semiconductor chip 101_I, the external connection terminal 104_I, the redistribution layer 103_I, and the encapsulant 102_I as described with reference to FIGS. 1A and 1B. , The connection film 105_I and the heat sink 106_I may be included.

The semiconductor chip 101_I, the external connection terminal 104_I, the redistribution layer 103_I, the encapsulant 102_I, and the connection film 105_I are described in FIG. 1A and 1B. Same as

The heat sink 106_I may be formed at an upper surface of the connection film 105_I. The heat sink 106_I may include a first heat dissipation layer 210_I formed on the top surface of the adhesive film 105_I and a second heat dissipation layer 220_I formed on the top surface of the first heat dissipation layer 210_I. have. In addition, the heat sink 106_I may include a protrusion S'_I formed by cutting the connection region S_I of FIG. 2A from the side surface of the first heat dissipation layer 210_I. In this case, since the plurality of semiconductor packages are cut by the cutting process after the group of the heat sinks 200_I are mounted, the protrusion S′_I may be self-aligned with the side surface of the semiconductor package 400_I.

Referring to FIG. 4A, the heat sink 106_I may include a first step formed between the adhesive film 105_I and the first heat dissipation layer 210_I in a region not including the protrusion S′_I. 310_I).

In this case, the footprint of the first heat dissipation layer 210_I may be larger than the footprint of the second heat dissipation layer 220_I. The first heat dissipation layer 210_I and the second heat dissipation due to a difference in footprint between the first heat dissipation layer 210_I and the second heat dissipation layer 220_I and the height of the second heat dissipation layer 220_I. The second step 320_I may be formed between the heat dissipation layer 220_I.

The height of the first step 310_I may be substantially the same as the height of the first heat dissipation layer 210_I, and the height of the second step 320_I is substantially the same as the height of the second heat dissipation layer 220_I. can do.

The height of the first step 310_I may be smaller than the height of the second step 320_I. In addition, the height of the protrusion S'_I may be substantially the same as the height of the first step 310_I. When the height of the protrusion S'_I, which may be formed to be substantially the same as the height of the first step 310_I, becomes smaller, the external force required for cutting may be less required in the cutting process, thereby increasing the flexibility of the cutting process. You can. However, the height of the first step 310_I and the second step 320_I may be variously formed, and the height of the first step 310_I may be smaller than the height of the second step 320_I. The heights of the first step 310_I and the second step 320_I may be substantially the same.

In addition, the sum of the heights of the first step 310_I and the second step 320_I may be about 25 percent to about 40 percent of the total thickness of the semiconductor package 400_I. Therefore, since the total thickness of the semiconductor package 400_I may be about 1.1 millimeters to about 1.4 millimeters, the sum of the heights of the first step 310_I and the second step 320_I is about 280 micrometers to about 560 micrometers. It can be meters.

In addition, the heat sink 106_I including the first heat dissipation layer 210_I and the second heat dissipation layer 220_I may be formed of a metal material, ceramic material, and carbon having various thermal conductivity as described with reference to FIGS. 1A and 1B. And a polymer material, and the like.

The heat sink 106_I sequentially heats the semiconductor chip 101_I, the encapsulant 102_I, the adhesive film 105_I, and the heat sink 106_I generated by the semiconductor chip 101_I in the semiconductor package 400_I. It can be efficiently discharged to the outside via.

FIG. 5A is a plan view illustrating a group 500_I of heat sinks in which a plurality of heat sinks are connected at a predetermined distance. FIG. 5B is a side cross-sectional view when the population 500_I of the heatsink 500_I of FIG. 5A, which is an embodiment of the present disclosure, is cut along the straight line c_I of FIG. 5A, and FIG. 5C is the population of the FIG. 5A heatsinks that is an embodiment of the disclosure. It is a side sectional view when 500_I) is cut along the straight line d_I of FIG.

Referring to FIGS. 5A-5C, a population 500_I of heat sinks, which is one embodiment of the present disclosure, may include a first heat dissipation layer 210_I, unlike the population 200_I of heat sinks disclosed in FIGS. 2A-2C. However, the second heat dissipation layer 220_I formed on the upper surface of the first heat dissipation layer 210_I shown in FIGS. 2A to 2C is not included. Therefore, the height of the first heat dissipation layer 210_I may be substantially the same as the height of the heat sink 106_I. The height of the first heat dissipation layer 210_I may be about 280 micrometers to about 560 micrometers, and may be about 25 percent to about 40 percent of the total semiconductor package thickness.

Other contents of the group of heat sinks 500_I disclosed in FIGS. 5A to 5C except for the above description are the same as those of the group 200_I of the heat sinks disclosed in FIGS. 2A to 2C.

FIG. 6A is a side cross-sectional view of a plurality of semiconductor packages mounted with the population 500_I of the heat sinks according to the straight line c of FIG. 5A, which is an embodiment of the present disclosure. FIG. 6B is a side cross-sectional view of a plurality of semiconductor packages mounted with the population 500_I of the heat sinks according to the straight line d of FIG. 5A, which is an embodiment of the present disclosure.

6A and 6B, the heat sink 601_I may include a first step 610_I. The first step 610_I is formed at the side where the connection region (S_I of FIG. 2A) is not formed at the side of the first heat dissipation layer 210_I, and the adhesive film 105_I and the first heat dissipation layer 210_I are formed. It may be formed by a difference in footprint and the height of the first heat dissipation layer 210_I.

More specifically, referring to FIG. 6A, when the population 500_I of the plurality of heat sinks is cut along a straight line c_I of FIG. 5A passing through a portion where the connection area S_I is not formed, the individual heat sinks 601_I. They may be spaced apart at a predetermined distance t_I. Due to the predetermined distance t_I, the footprint of the first heat dissipation layer 210_I may be smaller than the footprint of the adhesive film 105_I. Therefore, due to the difference between the footprint of the first heat dissipation layer 210_I and the adhesive film 105_I and the height of the first heat dissipation layer 210_I, the adhesive film 105_I and the first heat dissipation layer A first step 610_I may be formed between 210_I.

Referring to FIG. 6B, when the plurality of semiconductor packages on which the group of heat sinks 500_I are mounted are cut along a straight line d_I of FIG. 5A passing through a portion where a connection region S_I is formed, the individual heat sinks 601_I may be formed. It may be connected to each other by the connection area (S_I). Therefore, the first step 610_I may not be formed between the first heat dissipation layer 210_I and the adhesive film 105_I near the straight line d_I. Accordingly, the heat sink 601_I may include only a portion of the first step 610_I in the side surface.

FIG. 7A is a perspective view of an individual semiconductor package 700_I generated by cutting a plurality of semiconductor packages mounted with the population 500_I of the heat sinks of FIG. 5A, which is an embodiment of the present disclosure. FIG. 7B is a side cross-sectional view of the semiconductor package 700_I according to the exemplary embodiment of the present disclosure when the semiconductor package 700_I is cut along the straight line e_I of FIG. 7A, and FIG. 7C is a diagram of the semiconductor package 700_I according to the straight line f_I of FIG. 7A. Side cross section view.

Referring to FIGS. 7A through 7C, the semiconductor package 700_I may include the semiconductor chip 101_I, the external connection terminal 104_I, the redistribution layer 103_I, and the encapsulant 102_I, as described with reference to FIGS. 1A and 1B. , The connection film 105_I and the heat sink 601_I may be included.

Description of the semiconductor chip 101_I, the external connection terminal 104_I, the redistribution layer 103_I, the encapsulant 102_I, and the connection film 105_I included in the semiconductor package 700_I will be described. Same as the content described with reference to FIGS. 1A and 1B.

The heat sink 601_I may be formed at an upper surface of the connection film 105_I, and the heat sink 601_I may include a protrusion S′_I at a side surface thereof. In addition, the heat sink 601_I may include a first heat dissipation layer 210_I formed on an upper surface of the adhesive film 105_I.

The heat sink 601_I may include a first step 610_I formed between the adhesive film 105_I and the first heat dissipation layer 210_I in a region not including the protrusion S'_I. .

The height of the first step 610_I may be substantially the same as the height of the first heat dissipation layer 210_I, and may be about 25 percent to about 40 percent of the total thickness of the semiconductor package 700_I. Therefore, since the overall thickness of the semiconductor package 700_I may be about 1.1 millimeters to about 1.4 millimeters, the height of the first step 610_I may be about 280 micrometers to about 560 micrometers.

In addition, the first heat dissipation layer 210_I may include a metal-based material, a ceramic-based material, a carbon-based material, and a polymer-based material having the conductivity as described with reference to FIGS. 1A and 1B.

The heat sink 601_I illustrated in FIGS. 7A to 7C is configured to generate heat generated by the semiconductor chip 101_I in the semiconductor package 700_I, the semiconductor chip 101_I, the encapsulant 102_I, and the adhesive film 105_I. And the heat sink 601_I may be sequentially discharged to the outside.

FIG. 8A is a plan view illustrating a population 800_I of heat sinks in which a heat dissipation molding part is filled in the population 200_I of the heat sinks of FIG. 2A. FIG. 8B is a side cross-sectional view when the plurality of semiconductor packages on which the population of the heat sinks 800_I of FIG. 8A are mounted, is cut along the straight line g_I of FIG. 8A. FIG. 8C is a cross-sectional side view when the plurality of semiconductor packages in which the population of heat sinks of FIG. 8A is mounted, is cut along the straight line h_I of FIG. 8A.

8A to 8C, a first step 310_I and the first heat dissipation layer 210_I and the second heat dissipation layer formed between the adhesive film 105_I and the first heat dissipation layer 210_I. The empty space may be filled by the heat dissipation molding part 801_I by the second step 320_I formed between the 220_I.

The heat dissipation molding part 801_I may be formed on the top surface of the adhesive film 105_I to cover the top and side surfaces of the first heat dissipation layer 210_I. The heat dissipation molding part 801_I may cover the side surface of the second heat dissipation layer 220_I, but an upper surface of the second heat dissipation layer 220_I may be exposed to the outside. In addition, the heat dissipation molding part 801_I may cover the top surface of the connection area S_I.

The maximum thickness of the heat dissipation molding part 801_I may be substantially equal to the sum of the thickness of the first heat dissipation layer 210_I and the thickness of the second heat dissipation layer 220_I. The heat dissipation molding part 801_I may have a thickness of about 280 micrometers to about 560 micrometers, and may be about 25 percent to about 40 percent of the total semiconductor package thickness.

The population 800_I of the heat sinks filled with the heat dissipation molding part 801_I filled in the space vacated by the first step 310_I and the second step 320_I may have a rectangular parallelepiped shape as shown in FIG. 8A. . Due to the rectangular parallelepiped shape, the handling of the population of the heat sinks 800 — I may be easy, and the processing, transportation, and cutting of the population of the heat sinks 800 — I may be facilitated.

The heat dissipation molding part 801_I may include various materials such as a metal material, a ceramic material, a carbon material, and a polymer material. In one embodiment, the heat dissipation molding part 801_I may be an epoxy molding compound.

Referring to FIG. 8B, the cutting of the semiconductor packages in the portion where the connection region S_I is not formed may include heat dissipation molding part 801_I, adhesive film 105_I, encapsulant 102_I, and redistribution layer 103_I. Can be made through sequentially. Therefore, since the cutting of the connection region S_I is not necessary, the plurality of semiconductor packages may be divided into individual packages with less external force in the cutting process. In more detail, the heat dissipation molding part 801_I, the encapsulant 102_I, and the material of the redistribution layer 103_I may be composed of an epoxy molding compound having a relatively weak rigidity. This may eliminate the need for cutting blades of various materials with more rigidity.

Referring to FIG. 8C, the semiconductor package is cut at the portion where the connection region S_I is formed, and the heat dissipation molding part 801_I, the connection region S_I, the adhesive film 105_I, the encapsulant 102_I, and the ash It may be made through the wiring layer 103_I sequentially.

In this case, the material of the heat dissipation molding part 801_I may have a weaker rigidity than the material of the connection region S_I. As the rigidity of the connection region S_I is weak and the width w_I and the thickness of the connection region S_I are smaller, the connection region S_I is more easily cut by the cutting blade with less external force in the cutting process of the semiconductor package. Can be cut

FIG. 9A is a perspective view of an individual semiconductor package 900_I generated by cutting a plurality of semiconductor packages mounted with the population 800_I of the heat sinks of FIG. 8A, which is an embodiment of the present disclosure. FIG. 9B is a cross-sectional side view of the semiconductor package 900_I, which is an embodiment of the present disclosure, taken along a straight line i_I of FIG. 9A, and FIG. 9C is a straight line of FIG. 9A, wherein the semiconductor package 900_I is an embodiment of the present disclosure. Side cross-sectional view when cut according to j_I.

9A to 9C, the semiconductor package 900_I includes a semiconductor chip 101_I, an external connection terminal 104_I, a redistribution layer 103_I, an encapsulant 102_I, a connection film 105_I, and a heat sink. 106_I and the heat dissipation molding part 801_I.

The semiconductor chip 101_I, the external connection terminal 104_I, the redistribution layer 103_I, the encapsulant 102_I, the connection film 105_I, and the heat sink included in the semiconductor package 900_I. A description of the 106_I is the same as the content described with reference to FIGS. 7A to 7C.

9A to 9C, the heat dissipation molding part 801_I may be formed on the top surface of the adhesive film 105_I to cover the side and the top surface of the first heat dissipation layer 210_I. The heat dissipation molding part 801_I may cover the side surface of the second heat dissipation layer 220_I, but an upper portion of the second heat dissipation layer 220_I may be exposed to the outside. In addition, the heat dissipation molding part 801_I may cover the top surface of the protrusion S'_I shown in FIG. 4A, and the heat dissipation molding part 801_I is self-aligned with the side surface of the semiconductor package 900_I. The side surface of the protrusion S'_I may be exposed to the outside.

Since the top surface of the second heat dissipation layer 220_I may be exposed to the outside in the semiconductor package 900_I, the heat dissipation effect of the semiconductor package 900_I may be improved.

Since the plurality of semiconductor packages are cut by the cutting process after the group of the heat sinks 800_I are mounted, the footprint formed by the heat sink 106_I and the heat dissipation molding part 801_I is the semiconductor package. It may be substantially the same as the footprint (900_I).

As described above, the material of the heat dissipation molding part 801_I may have a weaker rigidity than the material of the protrusion S'_I formed by cutting the connection area S_I. An embodiment of the material of the heat dissipation molding part 801_I may include an epoxy molding compound.

FIG. 10A is a perspective view illustrating a plurality of heat sinks 1001_I according to an embodiment of the present disclosure, and FIG. 10B is a view illustrating a group of heat sinks 1000_I filled with heat dissipation molding parts of the heat sinks of FIG. 10A, which is an embodiment of the present disclosure. It is a top view showing.

Referring to FIG. 10A, the plurality of heat sinks 1001_I may be spaced apart by a predetermined distance x_I, and unlike the plurality of heat sinks of FIG. 2A, the plurality of heat sinks 1001_I are interconnected. It doesn't work. Therefore, an empty space 1002_I may exist between the plurality of heat sinks 1001_I.

Referring to FIG. 10B, the empty space 1002_I formed between the plurality of heat sinks 1001_I may be filled by the heat dissipation molding part 1010_I. As described above, the heat dissipation molding part 1010_I may include various materials such as a metal material, a ceramic material, a carbon material, and a polymer material. In one embodiment, the heat dissipation molding part 1010_I may be an epoxy molding compound. The heat dissipation molding part 1010_I may be filled from the empty space 1002_I to the top surface of the heat sinks 1001_I. Thus, the heat sink molding part 1000_I may have a rectangular parallelepiped shape by the heat dissipation molding part 1010_I. One unit of can be formed. Therefore, the group of the plurality of heat sinks 1000_I formed as one unit may be easily handled, and a process such as processing, transporting, and cutting the group of heat sinks 1000_I may be easy.

FIG. 11A is a perspective view of an individual semiconductor package 1100_I generated by cutting a plurality of semiconductor packages in which the population 1000_I of the heat sinks of FIG. 10B of the present disclosure are mounted. 11B is a side cross-sectional view when the semiconductor package 1100_I, which is an embodiment of the present disclosure, is cut along a straight line k_I.

11A and 11B, the semiconductor package 1100_I includes a semiconductor chip 101_I, an external connection terminal 104_I, a redistribution layer 103_I, an encapsulant 102_I, an adhesive film 105_I, and a heat sink. 1001_I and the heat dissipation molding part 1010_I.

Description of the semiconductor chip 101_I, the external connection terminal 104_I, the redistribution layer 103_I, the encapsulant 102_I, and the adhesive film 105_I included in the semiconductor package 1100_I is described above. Same as the content described with reference to FIGS. 7A to 7C.

11A and 11B, the heat sink 1001_I may be formed on the top surface of the adhesive film 105_I. In addition, in an embodiment of the present disclosure, the footprint of the heat sink 1001_I may be substantially the same as the footprint of the semiconductor chip 101_I. In addition, the heat sink 1001_I may have a rectangular parallelepiped shape. However, the present invention is not limited to the rectangular parallelepiped shape, and more various shapes can be obtained.

The footprint formed by the heat sink 1001_I may be substantially smaller than the footprint formed by the adhesive film 105_I. Therefore, a step may be formed at the edge of the heat sink 1001_I due to the difference in the footprint of the heat sink 1001_I and the adhesive film 105_I and the height of the heat sink 1001_I.

The heat dissipation molding part 1010_I may be formed on an upper surface of the adhesive film 105_I to cover the side surface of the heat sink 1001_I to fill an empty space caused by the step. In addition, the heat dissipation molding part 1010_I may self-align with the top surface of the heat sink 1001_I to expose the top surface of the heat sink 1001_I to the outside. By exposing the top surface of the heat sink 1001_I having relatively high thermal conductivity to the outside, the heat dissipation effect of the semiconductor package may be further improved.

Referring to FIG. 11B, the side surface of the heat dissipation molding part 1010_I may be self-aligned with the side surface of the semiconductor package 1100_I by the cutting process, and the heat dissipation molding part 1010_I and the heat sink ( The footprint formed by 1001_I may be substantially the same as the footprint of the semiconductor package 1100_I.

The thickness of the heat sink 1001_I may be about 25 percent to about 40 percent of the thickness of the semiconductor package 1100_I.

12A is a plan view illustrating a population 1200_I of heat sinks in accordance with one embodiment of the present disclosure. FIG. 12B is a side cross-sectional view when the population 1200_I of the heat sinks of FIG. 12A, according to one embodiment of the present disclosure, is cut along the straight line l of FIG.

12A and 12B, the plurality of heat sinks 1201_I may be spaced apart by a predetermined distance, and unlike the plurality of heat sinks 106_I of FIG. 2A, the plurality of heat sinks 1201_I Are not interconnected. Therefore, an empty space may exist between the plurality of heat sinks 1201_I.

12A and 12B, an empty space formed between the plurality of heat sinks 1201_I may be filled by the adhesive film 1202_I.

The adhesive film 1202_I may cover side surfaces of the heat sinks 1001_I, and the top surfaces of the heat sinks 1001_I may be exposed to the outside. The group of heat sinks 1200_I may be formed as one unit having a rectangular parallelepiped shape by the adhesive film 1202_I. Due to the rectangular parallelepiped shape, the collection of the heat sinks 1200_I may be easily handled, and the processing, transportation, and cutting of the populations of heat sinks 1200_I may be easy.

FIG. 13 is a side cross-sectional view when the semiconductor package 1300_I according to the exemplary embodiment of the present disclosure is cut along the straight line l_I of FIG. 12A. Referring to FIG. 13, the semiconductor package 1300_I includes a semiconductor chip 101_I, an external connection terminal 104_I, a redistribution layer 103_I, an encapsulant 102_I, an adhesive film 1202_I, and a heat sink 1201_I. ) May be included.

The semiconductor chip 101_I, the external connection terminal 104_I, the redistribution layer 103_I, and the encapsulant 102_I included in the semiconductor package 1300_I will be described with reference to FIGS. 7A through 7C. Same as the content.

As shown in FIG. 13, in one embodiment of the present disclosure, a footprint of the heat sink 1201_I may be substantially the same as that of the semiconductor chip 101_I.

In addition, the footprint of the heat sink 1201_I may be substantially smaller than the footprint of the adhesive film 1202_I disposed on the encapsulant 102_I. Therefore, a step may be formed between the adhesive film 1202_I and the heat sink 1201_I by the height of the heat sink 1201_I. The thickness formed by the heat sink 1201_I and the adhesive film may be about 25 percent to about 40 percent of the thickness of the semiconductor package 1300_I.

As shown in FIG. 13, the adhesive film 1202_I may extend to the side of the heat sink 1201_I to cover the side of the heat sink 1201_I and fill the empty space formed by the step.

In addition, the adhesive film 1202_I is self-aligned with the top surface of the heat sink 1201_I so that the top surface of the heat sink 1201_I may be exposed to the outside. By exposing the upper surface of the heat sink 1201_I having relatively high thermal conductivity to the outside, the heat dissipation effect of the semiconductor package may be further improved.

The footprint formed by the heat sink 1201_I and the adhesive film 1202_I extending to the side surfaces of the heat sink 1201_I may be substantially the same as the footprint of the semiconductor package 1300_I.

14 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

Referring to FIG. 14, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a semiconductor chip 101_I to an upper surface of a glass substrate 140_I. The semiconductor chip 101_I may be physically attached to an upper surface of the glass substrate 140_I.

Referring to FIG. 14, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include forming an encapsulant 102_I surrounding a semiconductor chip 101_I. The encapsulant 102_I may be formed by, for example, contacting a molding control film MCF to an upper surface of the semiconductor chip 101_I, and then forming the molding control film MCF and the glass substrate. 140_I) may include a method of filling the encapsulant 102_I. The encapsulant 102_I may cover both the side surface and the top surface of the semiconductor chip 101_I, and may cover only the side surface of the semiconductor chip 101_I and expose the top surface to the outside.

Referring to FIG. 14, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a heat sink 106_I. The heat sink 106_I may be attached to an upper surface of the semiconductor chip 101_I or an upper surface of the encapsulant 102_I. The method of closely placing the heat sink 106_I on the top surface of the semiconductor chip 101_I may include a thermocompression bonding method. In the thermal compression method, heat and pressure are applied to the adhesive film 105_I under the heat sink 106_I by using a compression machine. Through the thermocompression method, the adhesive film 105_I may stably attach the heat sink 106_I to the top surface of the semiconductor chip 101_I and the encapsulant 102_I.

Referring to FIG. 14, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include inverting the semiconductor package by separating the glass substrate 140_I.

Referring to FIG. 14, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include forming a redistribution layer 103_I. The redistribution layer 103_I may include an insulation pattern 141_I and a wiring pattern 142_I. In an exemplary embodiment, the insulating pattern 141_I may include a non-photosensitive material, and after the insulating pattern 141_I is formed on the bottom surface of the semiconductor chip 101_I, the insulating pattern 141_I may be a semiconductor chip 110_I. It may be partially removed to expose the chip pad 113_I. After the insulating pattern 141_I is formed, the wiring pattern 142_I may be connected to the chip pad 113_I exposed by the opening of the insulating pattern 141_I. The wiring pattern 142_I may be formed by plating, electroless plating, electroplating, or a combination thereof, and may be formed on the insulating pattern 141_I through a plating process. When the wiring pattern 142_I is formed, the wiring pattern 142_I may be formed once again on the wiring pattern 142_I. In this case, a part of the wiring pattern 142_I may be partially exposed to be connected to an external connection terminal.

Referring to FIG. 14, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching an external connection terminal 104_I. The external connection terminal may be a solder ball. The external connection terminal 104_I may be attached to the exposed wiring pattern 142_I through a soldering process.

Although not shown in FIG. 14, the method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include a cutting process for performing an individualization process. The cutting process may separate the plurality of semiconductor packages into individual semiconductor packages. In the case of the semiconductor package according to the embodiment of the present disclosure, as described above, the semiconductor has a step structure of the heat sink in the cut portion, a structure including a heat dissipation molding portion in the cut portion, and a structure including the adhesive film in the cut portion. Ease can be provided in the cutting process of the package. An embodiment of the cutting device of the cutting process may include a cutting blade, a laser device and the like.

Referring to FIG. 15, the electronic system 1500_I may include at least one of semiconductor packages of various embodiments of the inventive concept. The electronic system 1500_I may be included in a mobile device or a computer. For example, the electronic system 1500_I may include a memory system 1501_I, a microprocessor 1502_I, a RAM 1503_I, and a user interface 1504_I that performs data communication.

16 is a cross-sectional view illustrating a basic structure of a semiconductor package according to an embodiment of the present disclosure. The semiconductor package 100_II may be a fan-out wafer level package (FOWLP) or a panel level package (PLP).

Referring to FIG. 16, a semiconductor package 100_II according to an exemplary embodiment may include a semiconductor chip 101_II, a metal frame 102_II, a redistribution layer 103_II, an encapsulant 104_II, and an external connection terminal 105_II. , An adhesive film 106_II and a heat sink 107_II. The semiconductor package 100_II may be a semiconductor package having a wafer level package (WLP) structure, and specifically, may be a semiconductor package having a fan-out wafer level package structure. The overall thickness of the semiconductor package 100_II may be about 0.8 millimeters to about 1.8 millimeters. More specifically, in an embodiment of the present disclosure, the overall thickness of the semiconductor package 100_II may be about 1.1 millimeters to about 1.4 millimeters. However, the present invention is not limited to the above thickness and may have various thicknesses.

The semiconductor chip 101_II illustrated in FIG. 16 may include a plurality of individual devices of various kinds. For example, the plurality of individual devices may be a variety of microelectronic devices, for example a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale (LSI). image sensors such as integration (CIS), CMOS imaging sensors (CIS), and the like, micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.

In example embodiments, the semiconductor chip 101_II may be a memory semiconductor chip. The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a phase-change random access memory (PRAM), or a magneto-resistive random access memory (MRAM). ), Or a nonvolatile memory semiconductor chip such as ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM).

Alternatively, in example embodiments, the semiconductor chip 101_II may be a logic chip. For example, the semiconductor chip 101_II may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

In addition, although the semiconductor package 100_II is illustrated as including one semiconductor chip 101_II in FIG. 16, the semiconductor package 100_II may include two or more semiconductor chips 101_II. Two or more semiconductor chips 101_II included in the semiconductor package 100_II may be the same type of semiconductor chip or different types of semiconductor chips. In some embodiments, the semiconductor package 100_II may be a system in package (SIP) in which different types of semiconductor chips are electrically connected to each other and operate as one system.

The semiconductor chip 101_II may include a lower surface 111_II and an upper surface 112_II facing the lower surface 111_II. The semiconductor chip 101_II may include a chip pad 113_II on the bottom surface 111_II. The chip pad 113_II may be electrically connected to a plurality of individual elements of various kinds formed on the semiconductor chip 101_II. The chip pad 113_II may have a thickness between about 0.5 micrometers and about 1.5 micrometers. Although not illustrated in FIG. 16, the semiconductor chip 101_II may include a passivation layer covering the lower surface 111_II.

Referring to FIG. 16, the semiconductor package 100_II may include a metal frame 102_II. The metal frame 102_II may be made of various metal materials. For example, the metal frame 102_II may include aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and about 380 W / m · K. Metal-based materials such as copper (Cu) having thermal conductivity, nickel (Ni) having a thermal conductivity of about 90 W / m · K, and silver (Ag) having a thermal conductivity of about 410 W / m · K.

The metal frame 102_II may have a cavity 114_II therein. The semiconductor chip 101_II may be positioned in the cavity 114_II of the metal frame 102_II and may be surrounded by the metal frame 102_II. In addition, the semiconductor chip 101_II positioned in the inner wall of the metal frame 102_II and the cavity 114_II in the inside of the metal frame 102_II may be spaced apart from each other by a predetermined distance d_II.

The empty space spaced apart from the predetermined distance d_II may be filled by the encapsulant 104_II to be described later, and the encapsulant 104_II prevents an electrical short between the semiconductor chip 101_II and the metal frame 102_II. At the same time, the semiconductor chip 101_II and the metal frame 102_II may be fixed to an upper surface of the redistribution layer 103_II.

As illustrated in FIG. 16, the outer wall 102a_II of the metal frame 102_II may be disposed on the same plane as the side surface of the semiconductor package 100_II. Therefore, the outer wall 102a_II of the metal frame 102_II may be exposed to the outside.

In addition, as illustrated in FIG. 16, the height of the metal frame 102_II may be substantially the same as the height of the semiconductor chip 101_II. However, the present invention is not limited thereto, and the height of the metal frame 102_II may be smaller than or greater than the height of the semiconductor chip 101_II.

The shape of the metal frame 102_II, the length of the predetermined distance d_II, the heat dissipation effect according to the length of the predetermined distance d_II, and the like will be described in detail later.

Referring to FIG. 16, the semiconductor package 100_II may include an encapsulant 104_II. The encapsulant 104_II may serve to surround and protect the semiconductor chip 101_II. In addition, the encapsulant 104_II has a predetermined distance between the semiconductor chip 101_II and the metal frame 102_II to prevent electrical short between the semiconductor chip 101_II and the metal frame 102_II as described above. The semiconductor chip 101_II and the metal frame 102_II may be fixed to an upper surface of the redistribution layer 103_II to be described later.

The encapsulant 104_II may be formed of, for example, a silicon-based material, a thermosetting material, a thermoplastic material, a UV treatment material, or the like, and may be formed of, for example, a polymer such as resin. For example, it may be formed of an epoxy molding compound (EMC).

Referring to FIG. 16, the encapsulant 104_II may cover the side and top surfaces 112_II of the semiconductor chip 101_II and the inner wall and the top surface of the metal frame 102_II. When the heights of the semiconductor chip 101_II and the metal frame 102_II are substantially the same and the upper surfaces of the semiconductor chip 101_II and the metal frame 102_II are located on the same plane, the upper surface of the semiconductor chip 101_II and the metal frame 102_II and The height between the top surfaces of the encapsulant 104_II may be about 1 micrometer to about 10 micrometers.

Referring to FIG. 16, the semiconductor package 100_II may include an adhesive film 106_II. The adhesive film 106_II may contact the top surface 112_II of the semiconductor chip 101_II or the top surface of the encapsulant 104_II. The adhesive film 106_II may include an epoxy resin having excellent adhesion to the encapsulant 104_II and the semiconductor chip 101_II. In addition, a filler having excellent thermal conductivity may be included, for example, silver, aluminum, silicon dioxide, aluminum nitride, boron nitride, or the like, and may include aluminum oxide having thermal conductivity to maintain rigidity. The adhesive film 106_II may have an adhesive property by itself, and may also be provided by being bonded with a separate thermal conductive adhesive tape. The adhesive tape may be a double-sided adhesive tape. The adhesive film 106_II may fix the heat sink 107_II on the semiconductor package 100_II. The thickness of the adhesive film 106_II formed on the semiconductor package 100_II may be about 5 micrometers to about 20 micrometers, and more specifically, about 10 micrometers to about 14 micrometers.

Referring to FIG. 16, the semiconductor package 100_II may include a redistribution layer 103_II. The redistribution layer 103_II may be formed on the bottom surface 111_II of the semiconductor chip 101_II to electrically connect the chip pad 113_II and the external connection terminal 105_II of the semiconductor chip 101_II. The semiconductor package 100_II may form an external connection terminal 105_II in a region outside the footprint of the bottom surface 111_II of the semiconductor chip 101_II through the redistribution layer 103_II. The redistribution layer 103_II may enable an efficient arrangement of the external connection terminal 105_II in the semiconductor package 100_II.

Although not shown in FIG. 16, the redistribution layer 103_II may include a wiring pattern and an insulation pattern. The wiring pattern may be electrically connected to the chip pad 113_II formed on the bottom surface 111_II of the semiconductor chip 101_II, and may provide an electrical connection path for electrically connecting the chip pad 113_II to an external device. have. The insulating pattern serves to protect the wiring pattern electrically connected to the chip pad 113_II from external shock and to prevent a short circuit. For example, the insulating pattern may include a photosensitive material such as polyimide or epoxy. However, the present invention is not limited thereto and may be made of a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

Referring to FIG. 16, the semiconductor package may include an external connection terminal 105_II. The external connection terminal 105_II may be positioned on the bottom surface of the redistribution layer 103_II and electrically connected to the wiring pattern of the redistribution layer 103_II. The semiconductor package 100_II may be electrically connected to an external device such as a system board or a main board by the external connection terminal 105_II. The external connection terminal 105_II may include solder balls, as shown in FIG. 16. The solder ball may include at least one of tin, silver, copper, and aluminum. In addition, the solder ball may have a ball shape shown in FIG. 16, but is not limited thereto. The solder ball may have various shapes such as a cylinder, a polygonal column, and a polyhedron.

Referring to FIG. 16, the semiconductor package 100_II may include a heat sink 107_II. The heat sink 107_II may be positioned on the adhesive film 106_II and mounted on the semiconductor package 100_II. The heat sink 107_II may efficiently discharge heat generated from the semiconductor chip 101_II in the semiconductor package 100_II to the outside.

The heat sink 107_II mounted on the semiconductor package 100_II may include a metal material, a ceramic material, a carbon material, and a polymer material having various thermal conductivity.

More specifically, the heat sink 107_II of the metallic material includes aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and about 380 W / m · Metal-based materials such as copper (Cu) with a thermal conductivity of K, nickel (Ni) with a thermal conductivity of about 90 W / m · K, and silver (Ag) with a thermal conductivity of about 410 W / m · K. have.

The ceramic heat sink 107_II includes boron nitride (BN) having a thermal conductivity of about 1800 W / m · K, aluminum nitride (AlN) having a thermal conductivity of about 320 W / m · K, and about 30 W / m. Aluminum oxide (Al ₂ O ₃ ) with a K thermal conductivity, silicon carbide (SiC) with a thermal conductivity of about 480 W / m · K, and beryllium oxide (BeO) with a thermal conductivity of about 270 W / m · K It may include a ceramic-based material.

The heat sink 107_II of the carbon-based material includes diamond having a thermal conductivity of about 2500 W / m · K, carbon fiber having a thermal conductivity of about 100 W / m · K, and about 5 W / m · K to about 1950 W / m. Carbon-based materials such as graphite having a thermal conductivity of K, carbon nanotubes having a thermal conductivity of about 1.5 W / m · K to about 3500 W / m · K, and graphene having a thermal conductivity of about 5000 W / m · K. It may include.

The heat sink 107_II of the polymer material may include a polymer material such as polyethylene having an ultra high molecular weight having a thermal conductivity of about 45 W / m · K to about 100 W / m · K.

However, the heat sink 107_II is not limited to the above-described metal-based material, cerium-based material, carbon-based material, and polymer-based material, and may include a combination of the above materials or other materials not shown above.

Referring to FIG. 16, the heat sink 107_II mounted in the semiconductor package 100_II may be formed at various heights. In one embodiment of the present disclosure, the thickness v_II of the heat sink 107_II may account for about 25 percent to about 40 percent of the thickness of the semiconductor package. In an embodiment of the present disclosure, since the thickness of the semiconductor package 100_II may be about 1.1 millimeters to about 1.4 millimeters, the thickness v_II of the heat sink 107_II may be about 280 micrometers to about 560 micrometers. Can be.

Referring to FIG. 16, the semiconductor package 100_II efficiently externally generates heat generated by the semiconductor chip 101_II in the semiconductor package 100_II by the metal frame 102_II and the heat sink 107_II. Can be released.

More specifically, heat generated in the semiconductor chip 101_II may be emitted to the top surface 112_II and the side surface (not shown) of the semiconductor chip 101_II. Heat emitted to the top surface of the semiconductor chip 101_II may be sequentially released from the top surface 112_II of the semiconductor chip 101_II through the encapsulant 104_II, the adhesive film 106_II, and the heat sink 107_II. have. In addition, heat emitted to the side surface (not shown) of the semiconductor chip 101_II may be emitted to the outside through the encapsulant 104_II and the metal frame 102_II sequentially from the side surface of the semiconductor chip 101_II.

In this case, since the heat sink 107_II and the outer wall 102a_II of the metal frame 102_II are exposed to the outside, the semiconductor package 100_II of the present disclosure is exposed to the semiconductor chip due to convection. The heat generated at 101_II can be released more efficiently.

17 is a plan view of a semiconductor package 100_II in a straight line a_II of FIG. 16 according to an embodiment of the present disclosure.

Referring to FIG. 17, the metal frame 102_II of the semiconductor package 100_II may include a cavity 114_II therein. The semiconductor chip 101_II may be disposed in the cavity 114_II in the metal frame 102_II. The semiconductor chip 101_II may be spaced apart from the inner wall of the metal frame 102_II by a predetermined distance d_II to prevent an electrical short circuit with the metal frame 102_II. The encapsulant 104_II is formed in an empty space formed to be spaced apart from the predetermined distance d_II to prevent electrical short between the metal frame 102_II and the semiconductor chip 101_II, and at the same time, the metal frame 102_II and The semiconductor chip 101_II may be fixed on the redistribution layer 103_II.

As illustrated in FIG. 17, the metal frame 102_II may have a rectangular parallelepiped shape including a cavity 114_II therein. However, the present invention is not limited to the above shape, and more various shapes can be obtained. For example, the metal frame 102_II may have a cylindrical or polygonal column including a cavity 114_II therein.

As the predetermined distance d_II spaced between the semiconductor chip 101_II and the inner wall of the metal frame 102_II is shorter, the heat dissipation effect of the semiconductor package 100_II may be further improved. The thickness formed by the encapsulant 104_II having a lower thermal conductivity than the metal frame 102_II may become thinner as the predetermined distance d_II becomes shorter, so that heat generated in the semiconductor chip 101_II may be moved. This is because the heat transfer resistance in the path can be reduced.

In the related art, a space between the semiconductor chip 101_II and the metal frame 102_II is filled with the encapsulant 104_II using a printing mold technique. In the case of the printing mold technique, air may be captured in a space spaced between the semiconductor chip 101_II and the metal frame 102_II of the semiconductor package 100_II during the process, so that the captured mold A separate process was needed to vent the air. Therefore, in order to proceed with a separate process of discharging the captured air, the distance d_II between the semiconductor chip 101_II and the inner wall of the metal frame 102_II should be maintained at least 250 micrometers.

However, in an embodiment of the present disclosure, the spaced space between the semiconductor chip 101_II and the metal frame 102_II is filled with the encapsulant 104_II using a vacuum compression mold technique. The vacuum crimping mold technique vacuums the space between the semiconductor chip 101_II and the metal frame 102_II and then applies pressure to the encapsulant 104_II to the encapsulant 104_II in the space. ). Therefore, unlike the conventional printing mold technique, the vacuum crimping mold technique is extremely unlikely to trap air in the space between the semiconductor chip 101_II and the metal frame 102_II. It is not necessary. Therefore, in one embodiment of the present disclosure, the predetermined distance d_II between the inner wall of the metal frame and the semiconductor chip may be about 50 micrometers to about 150 micrometers. In one embodiment of the present disclosure, the predetermined distance may be about 100 micrometers, which is a distance reduced by about 2 times or more compared with the conventional distance d_II.

According to the exemplary embodiment of the present disclosure, while the spaced distance between the semiconductor chip 101_II and the metal frame 102_II is reduced to about 100 micrometers, the heat dissipation effect can be improved as described above. In addition, as the predetermined distance between the semiconductor chip 101_II and the metal frame 102_II is reduced, the distance between the semiconductor chips may be reduced in the process of forming the semiconductor chips on the semiconductor wafer. . Thus, more semiconductor chips can be placed on the wafer than in the prior art, so that the yield of the production of the semiconductor package can be improved.

18 is a cross-sectional view illustrating a structure of a semiconductor package 300_II according to another exemplary embodiment of the present disclosure.

Referring to FIG. 18, the semiconductor package 300_II includes a semiconductor chip 101_II, a metal frame 102_II, a redistribution layer 103_II, an encapsulant 104_II, an external connection terminal 105_II, and an adhesive film 106_II. And a heat sink 107_II. The semiconductor chip 101_II, the metal frame 102_II, the redistribution layer 103_II, the external connection terminal 105_II, the adhesive film 106_II, and the heat sink 107_II will be described with reference to FIG. 16. Reference is made to the above description.

Referring to FIG. 18, the encapsulant 104_II in the semiconductor package 300_II covers the side surface of the semiconductor chip 101_II and the inner wall of the metal frame 102_II, and the upper surface (of the semiconductor chip 101_II). 112_II and the upper surface of the metal frame 102_II may be exposed from the encapsulant 104_II. As the upper surface 112_II of the semiconductor chip 101_II and the upper surface of the metal frame 102_II are exposed, the thickness of the semiconductor package 300_II may be reduced, and heat generated from the semiconductor chip 101_II may be reduced. Instead of passing through the encapsulant 104_II, the adhesive film 106_II located on the top surface 112_II of the semiconductor chip 101_II and the heat sink 107_II located on the top surface of the adhesive film 106_II are sequentially passed through the outside. Can be released. Therefore, since the encapsulant 104_II has a relatively low thermal conductivity, the resistance may be reduced in the heat transfer path and better efficiency may be achieved in heat dissipation.

19 is a cross-sectional view illustrating a structure of a semiconductor package 400_II according to another exemplary embodiment of the present disclosure.

Referring to FIG. 19, the semiconductor package 400_II includes a semiconductor chip 101_II, a metal frame 401_II, a redistribution layer 103_II, an encapsulant 104_II, an external connection terminal 105_II, and an adhesive film 106_II. And a heat sink 107_II. The semiconductor chip 101_II, the redistribution layer 103_II, the encapsulant 104_II, the external connection terminal 105_II, the adhesive film 106_II, and the heat sink 107_II will be described with reference to FIG. 16. Reference is made to the above description.

Referring to FIG. 19, the height of the metal frame 401_II of the semiconductor package 400_II may be formed to be smaller than the height of the semiconductor chip 101_II. Therefore, the empty space formed by the height difference between the metal frame 401_II and the semiconductor chip 101_II may be filled with the encapsulant 104_II.

In the case of the semiconductor package 400_II, in the process of cutting a plurality of semiconductor packages into individual packages, the cutting process may be easy due to the low height of the metal frame 401_II having a relatively higher rigidity than the encapsulant 104_II. have. Thus, in the process of cutting a plurality of semiconductor packages into individual packages. The choice of cutting blades can be broadened and the speed of the cutting process can be ensured.

20 is a cross-sectional view illustrating a structure of a semiconductor package 500_II according to another exemplary embodiment of the present disclosure.

Referring to FIG. 20, the semiconductor package 500_II includes a semiconductor chip 101_II, a metal frame 501_II, a redistribution layer 103_II, an encapsulant 104_II, an external connection terminal 105_II, and an adhesive film 106_II. And a heat sink 107_II. The semiconductor chip 101_II, the redistribution layer 103_II, the encapsulant 104_II, the external connection terminal 105_II, the adhesive film 106_II, and the heat sink 107_II will be described with reference to FIG. 16. Same as above.

Referring to FIG. 20, the metal frame 501_II is laterally separated from the first region 501a_II and the first region 501a_II having an inner wall spaced apart from the semiconductor chip 101_II by a predetermined distance d_II. It may include an extended second region 501b_II. The outer wall of the first region 501a_II and the inner wall of the second region 501b_II may be integrated in contact with each other on the upper surface of the redistribution layer 103_II and may be separate.

The maximum height of the first region 501a_II may be greater than the maximum height of the second region 501b_II. The empty space formed by the height difference between the first region 501a_II and the second region 501b_II may be filled with the encapsulant 104_II.

In the case of the semiconductor package 500_II, in the process of cutting a plurality of semiconductor packages into individual packages, the height of the second region 501b_II of a material having a rigidity that is relatively higher than that of the encapsulant 104_II is caused. The cutting process can be easy. In addition, by selecting a material having a weaker rigidity than the material of the first region 501a_II as the material of the second region 501b_II, the choice of cutting blades can be widened and the speed of the cutting process can be ensured. have.

Referring to FIG. 20, the outer wall 502_II of the second region 501b_II of the metal frame 501_II may be coplanar with the side surface of the semiconductor package 500_II. Therefore, the outer wall 502_II of the second region 501b_II may be exposed to the outside of the semiconductor package. Heat generated in the semiconductor chip 101_II may be efficiently discharged to the outside of the semiconductor package 500_II through the outer wall 502_II of the second region 501b_II exposed to the outside.

Referring to FIG. 20, the maximum height of the first region 501a_II of the metal frame 501_II may be substantially the same as the height of the semiconductor chip. Therefore, heat generated from the side surface of the semiconductor chip 101_II may be more easily transferred to the first region 501a_II of the metal frame 501_II and finally released to the outside.

21 is a cross-sectional view illustrating a structure of a semiconductor package 600_II according to another exemplary embodiment of the present disclosure.

Referring to FIG. 21, the semiconductor package 600_II includes a semiconductor chip 101_II, a metal frame 601_II, a redistribution layer 103_II, an encapsulant 104_II, an external connection terminal 105_II, and an adhesive film 106_II. And a heat sink 107_II. The semiconductor chip 101_II, the redistribution layer 103_II, the encapsulant 104_II, the external connection terminal 105_II, the adhesive film 106_II, and the heat sink 107_II will be described with reference to FIG. 16. Reference is made to the above description.

Referring to FIG. 21, the metal frame 601_II is laterally disposed from the first region 601a_II and the first region 601a_II having an inner wall spaced apart from the semiconductor chip 101_II by a predetermined distance d_II. It may include an extended second region 601b_II. The outer wall of the first region 601a_II and the inner wall of the second region 601b_II may be integrated in contact with each other on the upper surface of the redistribution layer 103_II and may be separate.

Referring to FIG. 21, the maximum height of the first region 601a_II may be greater than the maximum height of the second region 501b_II. The empty space formed by the height difference between the first region 601a_II and the second region 601b_II may be filled with the encapsulant 104_II. In addition, the maximum height of the first region 601a_II may be smaller than the height of the semiconductor chip 101_II. By forming the maximum height of the first region 601a_II to be smaller than the height of the semiconductor chip 101_II, the first region 601a_II of the metal frame 601_II in the manufacturing process of the semiconductor package, as described later. The low height of allows the semiconductor chip 101_II to be aligned more quickly on the glass substrate.

In the case of the semiconductor package 600_II, in the process of cutting a plurality of semiconductor packages into individual packages, the height of the second region 601b_II of a material having a rigidity that is relatively higher than that of the encapsulant 104_II is caused. The cutting process can be easy. In addition, by selecting a material having a weaker rigidity than the material of the first region 601a_II as the material of the second region 601b_II, the selection of the cutting blades can be widened and the speed of the cutting process can be ensured. have.

Referring to FIG. 21, an outer wall 602_II of the second region 601b_II of the metal frame 601_II may be coplanar with a side surface of the semiconductor package 600_II. Therefore, the outer wall 602_II of the second region 601b_II may be exposed to the outside of the semiconductor package. Heat generated in the semiconductor chip 101_II through the outer wall 602_II of the second region 601b_II exposed to the outside may be efficiently discharged to the outside of the semiconductor package 600_II.

22 to 32 are diagrams for describing a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

FIG. 22 illustrates one step of a method of manufacturing a semiconductor package attaching a metal frame onto a glass substrate as an embodiment of the present disclosure. Referring to FIG. 22, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a metal frame 102_II to an upper surface of a glass substrate 701_II. An adhesive layer (not shown) may be formed on an upper surface of the glass substrate 701_II. The metal frame 102_II may be physically attached to an upper surface of the glass substrate 701_II by the adhesive layer (not shown).

FIG. 23 is a plan view of a plurality of metal frames 800_II attached on a glass substrate as an embodiment of the present disclosure. The plurality of metal frames 800_II attached to the upper surface of the glass substrate 701_II may be formed by connecting individual metal frames 102_II to each other. The plurality of metal frames 800_II may be separated into individual metal frames 102_II through a cutting process into individual semiconductor packages after the semiconductor package generation process is completed. The metal frame 102_II has a cavity 114_II therein, and a semiconductor chip may be disposed in the cavity 114_II to be spaced apart from the inner wall of the metal frame 102_II by a predetermined distance.

24 illustrates one step of a method of manufacturing a semiconductor package in which a semiconductor chip is mounted on a glass substrate as an embodiment of the present disclosure. Referring to FIG. 24, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include mounting a semiconductor chip 101_II on a glass substrate 701_II. The semiconductor chip 101_II may be located in the cavity 114_II formed in the inner wall of the metal frame 102_II attached to the glass substrate 701_II and mounted on the glass substrate 701_II. An inner wall of the semiconductor chip 101_II and the metal frame 102_II may be spaced apart from a predetermined distance d_II. The predetermined distance d_II may be about 50 micrometers to about 150 micrometers. In one embodiment, the predetermined distance d_II may be about 100 micrometers. Considering that the predetermined distance d_II between the semiconductor chip 101_II and the inner wall of the metal frame 102_II is about 250 micrometers, the embodiment of the present disclosure provides the predetermined distance d_II to about half or less. By reducing the number of semiconductor chips 101_II on the glass substrate 701_II, the productivity of the semiconductor package generation process may be improved.

In addition, as the height of the metal frame 102_II is lower, the accuracy of the process of mounting the semiconductor chip 101_II on the glass substrate 701_II may be increased and the speed of the process may be increased. Therefore, as described above, the height of the metal frame 102_II may be smaller than the height of the semiconductor chip 101_II. However, the present invention is not limited thereto and the height of the metal frame 102_II may be substantially the same as the height of the semiconductor chip 101_II.

25 illustrates a step of a method of manufacturing a semiconductor package in which the encapsulant 104_II is an embodiment of the present disclosure to cover and seal the semiconductor chip 101_II and the metal frame 102_II. Referring to FIG. 25, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include encapsulating material 104_II covering and sealing the semiconductor chip 101_II and the metal frame 102_II. Can be. The encapsulant 104_II fills a space formed by a predetermined distance d_II between the semiconductor chip 101_II and an inner wall of the metal frame 102_II to integrate the semiconductor chip 101_II and the metal frame 102_II. Can be. In addition, the encapsulant 104_II may cover top surfaces of the semiconductor chip 101_II and the metal frame 102_II. The encapsulant 104_II may cover and fix the semiconductor chip 101_II and the metal frame 102_II by using a vacuum pressing mold technique, which will be described later in detail with reference to FIG. 26.

Although not illustrated in FIG. 25, an exemplary embodiment of the present disclosure may be performed by grinding an upper portion of the encapsulant 104_II covering the top surface of the semiconductor chip 101_II and the metal frame 102_II to the semiconductor chip 101_II. Alternatively, the method may further include exposing a top surface of the metal frame 102_II.

FIG. 26 illustrates a step in a method of manufacturing a semiconductor package for mounting an encapsulant 104_II on a glass substrate 701_II using a vacuum crimp mold technique, which is an embodiment of the present disclosure. In the semiconductor package manufacturing method of the present disclosure, the semiconductor chip 101_II and the metal frame 102_II may be integrated by mounting the encapsulant 104_II on the glass substrate 701_II using the vacuum compression mold apparatus 1100_II. have.

Referring to FIG. 26, the vacuum pressing mold apparatus 1100_II may contact the lower surface of the glass substrate 701_II at the upper portion 1101_II of the vacuum pressing mold apparatus to fix the glass substrate 701_II upside down. have. The vacuum compression mold apparatus 1100_II may mount the film 1103_II on the lower portion 1102_II of the vacuum compression mold apparatus. An encapsulant 104_II may be disposed on an upper surface of the film 1103_II. The encapsulant 104_II on the upper surface of the film 1103_II may be a liquid or a solid before being mounted on the glass substrate 701_II. In addition, the encapsulant 104_II may be a polymer material such as a silicone-based material, a thermosetting material, a thermoplastic material, a UV treatment material, a resin, and the like, for example, an epoxy molding compound (EMC). It may include.

When the glass substrate 701_II is fixed to the vacuum pressing mold apparatus 1100_II and the encapsulant 104_II is disposed, the upper and lower portions 1101_II and the lower portion 1102_II of the vacuum pressing mold apparatus 1100_II are relatively disposed. It may move to form a closed space 1104_II between the semiconductor package and the lower portion 1102_II of the vacuum compression device. In this case, the compression mold apparatus 1100_II may discharge the gas in the enclosed space 1104_II to the outside to vacuum the enclosed space 1104_II. When the process of making the vacuum is finished, the vacuum compression mold apparatus 1101_II may apply pressure to the encapsulant 104_II in the direction of the glass substrate 701_II. Therefore, the encapsulant 104_II is formed on a space formed by a predetermined distance d_II between the semiconductor chip 101_II and the inner wall of the metal frame 102_II and on the upper surface of the semiconductor chip 101_II and the metal frame 102_II. Can be fixed.

In the related art, a space between the semiconductor chip 101_II and the metal frame 102_II is filled with the encapsulant 104_II using a printing mold technique. More specifically, after the encapsulant 104_II is placed on the spaced space between the semiconductor chip 101_II and the metal frame 102_II, a physical pressure is applied to the encapsulant 104_II using a pressure tool. The encapsulant 104_II may be inserted into the spaced space between the semiconductor chip 101_II and the metal frame 102_II.

In the case of the printing mold technique, a space between the semiconductor chip 101_II and the metal frame 102_II or a space inside the semiconductor package 100_II during the process of inserting the encapsulant 104_II. All of the air present in the air may not be discharged to the outside, and some air may be trapped in the semiconductor package 100_II. Therefore, conventionally, a separate process is required to discharge the trapped air to the outside. In order to proceed with a separate process to discharge the air, a predetermined distance d_II spaced between the semiconductor chip 101_II and the inner wall of the metal frame 102_II should be maintained at least 250 micrometers.

However, when using the vacuum crimping mold technique as an embodiment of the present disclosure, since the encapsulant 104_II may be fixed on the glass substrate 701_II in a vacuum state, a separate process of exhausting air is required. It may not be. Therefore, the predetermined distance d_II spaced between the semiconductor chip 101_II and the inner wall of the metal frame 102_II can be reduced to about 50 micrometers to about 150 micrometers, which is about half or less than that of the related art. Due to the reduced predetermined distance d_II, heat transfer resistance may be reduced by reducing heat transfer resistance on the semiconductor package. In addition, in the process of forming semiconductor chips on a semiconductor wafer, more semiconductor chips can be placed on the wafer, so that the productivity of semiconductor package generation can be improved.

In addition, the vacuum pressing mold technique may be applied without being restricted by the shape of the metal frame 102_II, and thus, various shapes of the metal frame 102_II may be applied as an embodiment of the present disclosure. The process time is shorter than that of the printing mold technique, so that the yield of the semiconductor package can be further increased.

27 illustrates one step of a method of manufacturing a semiconductor package for attaching a heat sink 107_II to a semiconductor package, which is an embodiment of the present disclosure. Referring to FIG. 27, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a heat sink 107_II on a semiconductor package.

Referring to FIG. 27, the heat sink 107_II may be attached to an upper surface of the semiconductor chip 101_II or an upper surface of the encapsulant 102_II. The method of closely arranging the heat sink 107_II on the top surface of the semiconductor chip 101_II may include a thermocompression bonding method. The thermal compression method is to apply heat and pressure to the adhesive film located under the heat sink 106_II using a compression machine. Through the thermal compression method, the adhesive film may stably attach the heat sink 107_II to the top surface of the semiconductor chip 101_II and the encapsulant 104_II.

28 is a view illustrating a shape of a heat sink according to an embodiment of the present disclosure. Referring to FIG. 28, a heat sink according to an embodiment of the inventive concept may have a rectangular parallelepiped shape 1301_II as shown in FIG. 28A, and a side surface in a rectangular parallelepiped shape as shown in FIG. 28B. The shape may have a shape 1302_II having a protrusion 1303_II. As will be described later, in the cutting process of the semiconductor package, the cutting line may be formed on the protruding portion 1303_II as shown by the straight line L_II shown in FIG. 28B, so that the cut portion of the heat sink is reduced. Can provide ease to the cutting process.

29 illustrates one step of a method of fabricating a semiconductor package that removes the glass substrate 701_II and inverts the semiconductor package according to one embodiment of the present disclosure. Referring to FIG. 29, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include inverting the semiconductor package by separating the glass substrate 701_II.

30 illustrates a step of a method of manufacturing a semiconductor package for forming a redistribution layer and an external connection terminal according to an exemplary embodiment of the present disclosure.

Referring to FIG. 30, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include forming a redistribution layer 103_II. The redistribution layer 103_II may include a wiring pattern 1501_II and an insulation pattern 1502_II. In an exemplary embodiment of the present disclosure, the insulating pattern 1502_II may include a non-photosensitive material, and after the insulating pattern 1502_II is formed on the bottom surface of the semiconductor chip 101_II, the insulating pattern 1502_II is a semiconductor. It may be partially removed to expose the chip pad 113_II of the chip 101_II. After the insulating pattern 1502_II is formed, the wiring pattern 1501_II may be electrically connected to the chip pad 113_II exposed by the opening of the insulating pattern 1502_II. The wiring pattern 1501_II may be formed by plating, electroless plating, electroplating, or a combination thereof, and may be formed on the insulating pattern 1502_II through a plating process. When the wiring pattern 1501_II is formed, the insulating pattern 1502_II may be formed on the wiring pattern 1501_II again. In this case, a part of the wiring pattern 1501_II may be partially exposed to be connected to the external connection terminal 105_II.

Also, referring to FIG. 30, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching an external connection terminal 105_II. The external connection terminal 105_II may be a solder ball. The external connection terminal 105_II may be attached to the exposed wiring pattern 1501_II through a soldering process.

31 and 32 illustrate one step of a semiconductor package manufacturing method of cutting a plurality of semiconductor packages into individual packages according to an embodiment of the present disclosure.

Referring to FIGS. 31 and 32, the process of cutting the plurality of semiconductor packages into individual packages may be performed by using a cutting blade. The redistribution layer 103_II, the metal frame 102_II, and the encapsulant 104_II of the semiconductor package may be cut using a cutting blade. , And the heat sink 107_II may be cut sequentially. In this case, the height of the metal frame 102_II, which is relatively harder than the encapsulant 104_II, may be adjusted to provide an easy cutting process. For example, as described above with reference to FIG. 20, as the height of the second region 501b_II of the metal frame 501_II of FIG. 20 is smaller, the cutting depth of the metal frame 501_II of the cutting blade is shorter, so that the cutting process is performed. It can be quick.

FIG. 32 illustrates a step of a semiconductor package manufacturing method of cutting a plurality of semiconductor packages on which the heat sinks (FIGS. 28 and 1302_II) shown in FIG. 28B are mounted into individual packages. Referring to FIG. 32, a region in which the protrusion 1303_II is not formed may exist in one region of the cutting line L_II illustrated in FIG. 28. Therefore, the semiconductor package cutting process may be performed by sequentially cutting the redistribution layer 103_II, the metal frame 102_II, and the encapsulant 104_II, without cutting the heat sink 107_II. Therefore, since there is no cutting of the heat sink 107_II that is relatively harder than the encapsulant 104_II, it is possible to secure the speed and ease of cutting.

Referring to FIG. 33, the electronic system 1800_II may include at least one of semiconductor packages of various embodiments of the inventive concept. The electronic system 1800_II may be included in a mobile device or a computer. For example, the electronic system 1800_II may include a memory system 1801_II, a microprocessor 1802_II, a RAM 1803_II, and a user interface 1804_II that performs data communication.

34 is a cross-sectional view illustrating a basic structure of the semiconductor package 100_III according to an embodiment of the present disclosure. The semiconductor package 100_III may be a fan-out wafer level package (FOWLP) or a panel level package (PLP).

Referring to FIG. 34, a semiconductor package 100_III according to an exemplary embodiment of the present disclosure may include a semiconductor chip 101_III, a metal frame 102_III, a redistribution layer 103_III, an encapsulant 104_III, and an external connection terminal 105_III. , An adhesive film 106_III and a heat sink 107_III may be included. The semiconductor package 100_III may be a semiconductor package having a wafer level package (WLP) structure, and specifically, may be a semiconductor package having a fan-out wafer level package structure.

The overall thickness d_III of the semiconductor package 100_III may be about 0.8 millimeters to about 1.8 millimeters. More specifically, in an embodiment of the present disclosure, the overall thickness d_III of the semiconductor package 100_III may be about 1.1 millimeters to about 1.4 millimeters. However, the semiconductor package 100_III of the present disclosure is not limited to the thickness d_III but may have a variety of thicknesses d_III.

The semiconductor chip 101_III illustrated in FIG. 34 may include a plurality of individual devices of various kinds. For example, the plurality of individual devices may be a variety of microelectronic devices, for example a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale image sensors such as integration (CIS), CMOS imaging sensors (CIS), and the like, micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.

In example embodiments, the semiconductor chip 101_III may be a memory semiconductor chip. The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a phase-change random access memory (PRAM), or a magneto-resistive random access memory (MRAM). ), Or a nonvolatile memory semiconductor chip such as ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM).

Alternatively, the semiconductor chip 101_III may be a logic chip. For example, the semiconductor chip 101_III may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

Although the semiconductor package 100_III of FIG. 34 is illustrated as including one semiconductor chip, the semiconductor package 100_III may include two or more semiconductor chips. Two or more semiconductor chips included in the semiconductor package 100_III may be the same kind of semiconductor chip or different types of semiconductor chips. In one embodiment, the semiconductor package 100_III may be a system in package (SIP) in which different types of semiconductor chips are electrically connected to each other and operate as one system.

The semiconductor chip 101_III may include a lower surface 111_III and an upper surface 112_III opposite to the lower surface 111_III. The semiconductor chip 101_III may include a chip pad 113_III on the lower surface 111_III. The chip pad 113_III may be electrically connected to a plurality of individual elements of various kinds formed on the semiconductor chip 101_III. Although not shown in FIG. 34, the semiconductor chip 101_III may include a passivation layer covering the lower surface 111_III.

The semiconductor package 100_III may include a metal frame 102_III. The metal frame 102_III may be located on the redistribution layer 103_III and include a cavity therein. The semiconductor chip 101_III is positioned in an internal cavity of the metal frame 102_III, and the semiconductor chip 101_III may be surrounded by the metal frame 102_III.

The metal frame 102_III may be made of various metal materials. For example, the metal frame 102_III may include aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and about 380 W / m · K. Metal based materials such as copper (Cu) having thermal conductivity, nickel (Ni) having a thermal conductivity of about 90 W / m · K, and silver (Ag) having a thermal conductivity of about 410 W / m · K.

Heat generated from the side surface of the semiconductor chip 101_III may be transferred to the metal frame 102_III and released to the outside. As illustrated in FIG. 34, the outer wall 102a_III of the metal frame 102_III may be disposed on the same plane as the side surface of the semiconductor package 100_III and exposed to the outside. Therefore, the heat dissipation performance of the semiconductor package 100_III may be improved by the metal frame 102_III.

The semiconductor package 100_III may include an encapsulant 104_III. The encapsulant 104_III may serve to surround and protect the semiconductor chip 101_III. In addition, the encapsulant 104_III is a space formed between the semiconductor chip 101_III and the metal frame 102_III to prevent an electrical short between the semiconductor chip 101_III and the metal frame 102_III as described above. Can be filled in. In addition, the encapsulant 104_III may cover at least a portion of the semiconductor chip 101_III and at least a portion of the metal frame 102_III. Therefore, the semiconductor chip 101_III and the metal frame 102_III may be integrated with the encapsulant 104_III to contact the upper surface of the redistribution layer 103_III to be described later.

The encapsulant 104_III may be formed of, for example, a silicone-based material, a thermosetting material, a thermoplastic material, a UV treatment material, or the like, and may be formed of, for example, a polymer such as resin. For example, it may be formed of an epoxy molding compound (EMC).

In example embodiments, the encapsulant 104_III may cover the side and top surfaces 112_III of the semiconductor chip 101_III and the side and top surfaces of the metal frame 102_III. The height formed by the semiconductor chip 101_III and the metal frame 102_III is substantially the same, so that the top surface of the semiconductor chip 101_III and the top surface of the metal frame 102_III may be on the same plane. In this case, the distance e_III between the top surface of the semiconductor chip 101_III and the metal frame 102_III and the top surface of the encapsulant 104_III may be about 1 micrometer to about 10 micrometers.

The semiconductor package 100_III may include an adhesive film 106_III. The adhesive film 106_III may contact the top surface 112_III of the semiconductor chip 101_III or the top surface of the encapsulant 104_III. The adhesive film 106_III may include an epoxy resin having excellent adhesion to the encapsulant 104_III and the semiconductor chip 101_III. In addition, a filler having excellent thermal conductivity may be included, for example, silver, aluminum, silicon dioxide, aluminum nitride, boron nitride, or the like, and may include aluminum oxide having thermal conductivity to maintain rigidity. The adhesive film 106_III may have adhesive properties by itself, and may also be provided by being bonded with a separate thermal conductive adhesive tape. The adhesive tape may be a double-sided adhesive tape. The adhesive film 106_III may be interposed between the encapsulant 104_III and the heat sink 107_III to fix the heat sink 107_III. The thickness of the adhesive film 106_III formed on the semiconductor package 100_III may be about 5 micrometers to about 20 micrometers, and more specifically, about 10 micrometers to about 14 micrometers.

The semiconductor package 100_III may include a redistribution layer 103_III. The redistribution layer 103_III may be formed on the bottom surface 111_III of the semiconductor chip 101_III to electrically connect the chip pad 113_III and the external connection terminal 105_III of the semiconductor chip 101_III. The semiconductor package 100_III may form an external connection terminal 105_III in a region outside the footprint of the bottom surface 111_III of the semiconductor chip 101_III through the redistribution layer 103_III. The redistribution layer 103_III may enable efficient placement of the external connection terminal 105_III in the semiconductor package 100_III.

The redistribution layer 103_III may include a wiring pattern 103a_III and an insulation pattern 103b_III. The wiring pattern 103a_III may be electrically connected to the chip pad 113_III formed on the bottom surface 111_III of the semiconductor chip 101_III and may provide an electrical connection path for electrically connecting the chip pad 113_III to an external device. Can provide. The insulating pattern 103b_III protects the wiring pattern electrically connected to the chip pad 113_III from external shock and prevents a short circuit. For example, the insulating pattern 103b_III may include a photosensitive material such as polyimide or epoxy. However, the present invention is not limited thereto and may be made of a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

The semiconductor package may include an external connection terminal 105_III. The external connection terminal 105_III may be located on the bottom surface of the redistribution layer 103_III and may be electrically connected to the wiring pattern of the redistribution layer 103_III. The semiconductor package 100_III may be electrically connected to an external device such as a system board or a main board by the external connection terminal 105_III. The external connection terminal 105_III may include solder balls, as shown in FIG. 34. The solder ball may include at least one of tin, silver, copper, and aluminum. In addition, the solder ball may have a ball shape shown in FIG. 34, but is not limited thereto. The solder ball may have various shapes such as a cylinder, a polygonal column, and a polyhedron.

The semiconductor package 100_III may include a heat sink 107_III. The heat sink 107_III may be disposed on the adhesive film 106_III and mounted on the semiconductor package 100_III. The heat sink 107_III may quickly release heat generated from the semiconductor chip 101_III in the semiconductor package 100_III to the outside.

The heat sink 107_III mounted on the semiconductor package 100_III may include a metal material, a ceramic material, a carbon material, and a polymer material having various thermal conductivity.

More specifically, the heat sink 107_III of the metallic material includes aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and about 380 W / m · Metal-based materials such as copper (Cu) with a thermal conductivity of K, nickel (Ni) with a thermal conductivity of about 90 W / m · K, and silver (Ag) with a thermal conductivity of about 410 W / m · K. have.

The ceramic heat sink 107_III includes boron nitride (BN) having a thermal conductivity of about 1800 W / m · K, aluminum nitride (AlN) having a thermal conductivity of about 320 W / m · K, and about 30 W / m. Aluminum oxide (Al ₂ O ₃ ) with a K thermal conductivity, silicon carbide (SiC) with a thermal conductivity of about 480 W / m · K, and beryllium oxide (BeO) with a thermal conductivity of about 270 W / m · K It may include a ceramic-based material.

The heat sink 107_III of the carbon-based material includes diamond having a thermal conductivity of about 2500 W / m · K, carbon fiber having a thermal conductivity of about 100 W / m · K, and about 5 W / m · K to about 1950 W / m. Carbon-based materials such as graphite having a thermal conductivity of K, carbon nanotubes having a thermal conductivity of about 1.5 W / m · K to about 3500 W / m · K, and graphene having a thermal conductivity of about 5000 W / m · K. It may include.

The heat sink 107_III of the polymer material may include a polymer material such as polyethylene having an ultra high molecular weight having a thermal conductivity of about 45 W / m · K to about 100 W / m · K.

However, the heat sink 107_III is not limited to the metal-based material, the cerium-based material, the carbon-based material, and the polymer-based material, and may include a combination of the materials or other materials not shown above.

The heat sink 107_III mounted on the semiconductor package 100_III may be formed in various thicknesses. In one embodiment of the present disclosure, the thickness f_III of the heat sink 107_III may occupy about 25 percent to about 40 percent of the thickness of the semiconductor package. In an embodiment of the present disclosure, since the thickness of the semiconductor package 100_III may be about 1.1 millimeters to about 1.4 millimeters, the thickness f_III of the heat sink 107_III may be about 280 micrometers to about 560 micrometers. Can be. More specifically, the thickness f_III of the heat sink 107_III of the semiconductor package 100_III may be about 400 micrometers.

The heat sink 107_III mounted on the semiconductor package 100_III may have a concave-convex structure as shown in FIG. 1. Through the shape of the uneven structure, the heat sink 107_III may have an increased cross-sectional area in contact with the outside air. Therefore, the heat dissipation effect of the semiconductor package 100_III including the heat sink 107_III of the present disclosure may be improved than that of the semiconductor package in which the heat sink without the uneven structure is formed. The shape of the uneven structure of the heat sink 107_III and the method of forming the uneven structure of the heat sink 107_III will be described later in detail with reference to FIGS. 36 to 38.

In addition, information on the semiconductor chip 101_III may be marked on a portion of the heat sink 107_III of the semiconductor package 100_III. The marking of the heat sink 107_III will be described later in detail.

The semiconductor package 100_III may quickly release heat generated from the semiconductor chip 101_III by the metal frame 102_III and the heat sink 107_III having the uneven structure.

More specifically, heat generated in the semiconductor chip 101_III may be emitted to the top surface 112_III and the side surface (not shown) of the semiconductor chip 101_III. Heat emitted from the upper surface 112_III of the semiconductor chip 101_III is sequentially transferred from the upper surface 112_III of the semiconductor chip 101_III through the encapsulant 104_III, the adhesive film 106_III, and the heat sink 107_III. Can be released. In addition, heat emitted to the side surface (not shown) of the semiconductor chip 101_III may be emitted to the outside through the encapsulant 104_III and the metal frame 102_III sequentially from the side surface of the semiconductor chip 101_III. In this case, the metal frame 102_III and the heat sink 107_III of the semiconductor package 100_III may include a material having a relatively high thermal conductivity, and the surface of the heat sink 107_III. The outer wall 102a_III of the metal frame 102_III may be exposed to the outside, so that heat generated in the semiconductor chip 101_III may be discharged to the outside more quickly.

35 is a cross-sectional view illustrating a structure of a semiconductor package 200_III according to another exemplary embodiment of the present disclosure.

Referring to FIG. 35, the semiconductor package 200_III includes a semiconductor chip 101_III, a metal frame 102_III, a redistribution layer 103_III, an encapsulant 104_III, an external connection terminal 105_III, and an adhesive film 106_III. And a heat sink 107_III. The semiconductor chip 101_III, the metal frame 102_III, the redistribution layer 103_III, the external connection terminal 105_III, the adhesive film 106_III, and the heat sink 107_III will be described with reference to FIG. 34. Reference is made to the above description.

The encapsulant 104_III of the semiconductor package 200_III covers the side surface of the semiconductor chip 101_III and the inner wall of the metal frame 102_III, and the top surface 112_III and the metal frame 102_III of the semiconductor chip 101_III. ) May be exposed from the encapsulant 104_III. The upper surface 112_III of the semiconductor chip 101_III and the upper surface of the metal frame 102_III are exposed from the encapsulant 104_III, so that the overall thickness d'_III of the semiconductor package 200_III is the semiconductor of FIG. 34. The semiconductor package 200_III may be thinner and lighter than the total thickness d_III of the package 100_III.

In addition, heat generated from the top surface 112_III of the semiconductor chip 101_III of the semiconductor package 200_III may be formed by the adhesive film 106_III and the adhesive film 106_III located on the top surface 112_III of the semiconductor chip 101_III. The heat sink 107_III located on the upper surface may be sequentially discharged to the outside. Therefore, since the heat generated in the semiconductor chip 101_III does not pass through the encapsulant 104_III having a relatively low thermal conductivity, the heat transfer resistance may be reduced in the movement path of the heat, and thus the heat dissipation performance of the semiconductor package 200_III may be reduced. This can be improved further.

36 and 37 are cross-sectional views illustrating a structure of a heat sink of a semiconductor package according to an embodiment of the present disclosure. FIG. 38 is a plan view for explaining the structure of the heat sink shown in FIGS. 36 and 37.

36 to 38, the heat sinks 300a_III and 300b_III of the semiconductor package according to the exemplary embodiments of the present disclosure may have a concave-convex structure. The dictionary meaning of the irregularities is concave and convex. The heat sinks 300a_III and 300b_III may include a base 301_III and a plurality of protrusions 302a_III and 302b_III. More specifically, the heat sinks 300a_III and 300b_III may include a plurality of protrusions 302a_III and 302b_III protruding from an upper surface of the base portion 301_III having the flat plate shape. Due to the shape in which the plurality of protrusions 302a_III and 302b_III are repeatedly spaced at a predetermined distance, the heat sinks 300a_III and 300b_III are concave and convex in the upper surface of the base 301_III. The concave-convex structure can be shaped.

The bottom surface of the bottom portion 301_III of the heat sinks 300a_III and 300b_III may be positioned on the top surface of the encapsulant of the semiconductor package and fixed by an adhesive film. The thickness f ₁ _ III of the base 301_III may account for about 40 percent to about 60 percent of the total thickness f_III of the heat sinks 300a_III and 300b_III. According to an embodiment of the present disclosure, the thickness f ₁ _ III of the base 301_III of the heat sinks 300a_III and 300b_III may be half the total thickness f_III of the heat sinks 300a_III and 300b_III. Thus, when the total thickness f_III of the heat sinks 300a_III and 300b_III is about 400 micrometers, the thickness f ₁ _III of the base 301_III of the heat sinks 300a_III and 300b_III is about 200 micrometers. Can be.

The protrusions 302a_III and 302b_III of the heat sinks 300a_III and 300b_III may be formed to be spaced apart from the neighboring protrusions 302a_III and 302b_III by a predetermined distance g_III. In an embodiment of the present disclosure, the separation distance g_III between the protrusions 302a_III and 302b_III may be about 100 micrometers to about 300 micrometers. More specifically, the separation distance g_III between the protrusions 302a_III and 302b_III may be about 200 micrometers.

The width e_III formed by the one protrusion 302a_III or 302b_III of the heat sinks 300a_III and 300b_III may be about 100 micrometers to about 300 micrometers. More specifically, the width e_III formed by the protrusions 302a_III and 302b_III may be about 200 micrometers.

The heat sink to the one of the protrusions (302a_III, 302b_III) the thickness (f ₂ _III) forming from about 40 percent to about 60 of the total thickness (f_III) of the heat sink (300a_III, 300b_III) of (300a_III, 300b_III) It can occupy a percentage. According to an embodiment of the present disclosure, the thickness f ₂ _ III of the protrusions 302a_III and 302b_III of the heat sinks 300a_III and 300b_III may be half of the total thickness f_III of the heat sinks 300a_III and 300b_III. . Thus, when the total thickness f_III of the heat sinks 300a_III and 300b_III is about 400 micrometers, the thickness f ₂ _III of the one projections 302a_III and 302b_III of the heat sinks 300a_III and 300b_III is about 200 micrometers.

The heat sink (300a_III, 300b_III) Total thickness (f_III) of the said base (301_III) thickness (f ₁ _III) and the projection sum of the thickness (f ₂ _III) of (302a_III, 302b_III) (f_III = f 1 _III of + f ₂ _III). In an embodiment of the present disclosure, when the total thickness f_III of the heat sinks 300a_III and 300b_III is about 400 micrometers, the thickness f ₁ _ III of the base portion 301_III is the heat sink 300a_III, 300b_III. ) it may be about 40 percent of about 160 microns in total thickness (f_III), in this instance, the protrusions (302a_III, 302b_III) thickness (f ₂ _III) of the thickness (f_III of the heat sink (300a_III, 300b_III) of About 240 microns, which is about 60 percent. Further, when the thickness f ₁ _ III of the base portion 301_III is about 240 micrometers which is about 60 percent of the thickness f_III of the heat sinks 300a_III and 300b_III, the thickness of the protrusions 302a_III and 302b_III ( f ₂ _III) may be about 160 micrometers, which is about 40 percent of the thickness f_III of the heat sinks 300a_III and 300b_III. The thickness f ₁ _ III of the base portion 301_III of the heat sinks 300a_III and 300b_III of the present disclosure and the thickness f ₂ _III of the protrusions 302a_III and 302b_III may be substantially the same, and in one embodiment, Each may be about 200 micrometers.

Referring to FIG. 36, the protrusion 302a_III of the heat sink 300a_III may include a plane at the top, and referring to FIG. 37, the protrusion 302b_III of the heat sink 300b_III is convex from the top. It may include a surface. The shape of the protrusions 302b_III of the heat sinks 300a_III and 300b_III is not limited to those of FIGS. 36 and 37 and may have various shapes.

The heat sink 300a_III of FIG. 36 may have a shape including the plurality of protrusions 302a_III through a process of cutting a portion of a rectangular parallelepiped heat sink having a predetermined thickness f_III through a cutting device. have. The cutting blade of the cutting device may have a cutting width having a distance g_III between the plurality of protrusions 302a_III and also have a thickness f ₂ _ III of the protrusion 302a_III as the cutting depth. have. The cutting device may cut along a cutting lane L_III shown in FIG. 38 while simultaneously cutting a portion of the heat sink, so that the heat sink 300a_III of FIG. 302a_III.

The heat sink 300b_III of FIG. 37 has the shape of a convex curved surface at the top through an additional cutting process of smoothly cutting the upper portion of the formed protrusion 302a_III after forming the protrusions 302a_III through the aforementioned cutting device. The protrusions 302b_III of FIG. 37 may be included.

In addition, the heat sinks 300a_III and 300b_III illustrated in FIGS. 36 and 37 may be formed through an injection molding process instead of the aforementioned cutting process.

More specifically, the material to be formed of the heat sinks 300a_III and 300b_III may be injected into an injection molding heating chamber. The material of the heat sinks 300a_III and 300b_III injected into the heating chamber may be melted by the high temperature of the heating chamber. The molten material may be injected into an injection molding machine including an injection space in the shape of the heat sinks 300a_III and 300b_III of FIGS. 36 and 37. The injected molten material may fill the injection space in the shape of the heat sinks 300a_III and 300b_III. Thereafter, the injection molding machine may cool the molten material in the injection space to finally form the heat sinks 300a_III and 300b_III shown in FIGS. 36 and 37. When the injection molding process is used, the shape of the concave-convex structure of the heat sinks 300a_III and 300b_III is not limited to those shown in FIGS. 36 and 37, and may have various shapes according to the shape of the injection space of the injection molding machine. Can be.

The heat sinks 300a_III and 300b_III of FIGS. 36 to 38 are not limited to the above-described cutting process and injection molding process, and may form an uneven structure through various processes. In an embodiment, the uneven structures of the heat sinks 300a_III and 300b_III may be formed through a chemical reaction. In an embodiment, the heat sinks 300a_III and 300b_III may form an uneven structure through a process of physically bonding a plurality of protrusions 301a_III and 301b_III separately formed on the base 301_III. In this case, the materials of the protrusions 301a_III and 301b_III and the base 301_III of the heat sinks 300a_III and 300b_III may be different.

The heat dissipation performance of the semiconductor packages may be improved due to the shape of the uneven structure of the heat sinks 300a_III and 300b_III. More specifically, by forming the concave-convex structure, the heat sinks 300a_III and 300b_III may have a large surface area in contact with outside air. Accordingly, the semiconductor package in which the heat sinks 300a_III and 300b_III are mounted may quickly release heat emitted from the semiconductor chip in the semiconductor package to the outside more quickly.

39 and 40 are plan views illustrating heat sinks 400a_III and 400b_III in which information of a semiconductor chip is marked according to an exemplary embodiment of the present disclosure, respectively.

39 and 40, the heat sinks 400a_III and 400b_III are positioned on the base 404_III and the base 404_III to be positioned on the top surface of the encapsulant, thereby marking the information of the semiconductor chip. It may include a marking area 402a_III and 402b_III, and a protrusion area 403_III including a plurality of protrusions 401_III protruding from the base 404_III.

As shown in FIGS. 39 and 40, the protrusions 401_III may not be formed in the marking regions 402a_III and 402b_III in which the information of the semiconductor chip is represented. In other words, the heat sinks 400a_III and 400b_III may not include a concave-convex structure at one portion, but may include a flat plane. Accordingly, the marking regions 402a_III and 402b_III may be formed at a height lower than the top surface of the protrusion 401_III. In one embodiment, the marking region may be formed on a portion of the top surface of the base portion 404_III.

The heat sink 400a_III illustrated in FIG. 39 may include a marking area 402a_III in a plane where the protrusions 401_III are not formed at the upper left side, and the marking area 402a_III is mounted in the semiconductor package. Information of the semiconductor chip can be marked. In addition, the heat sink 400_III illustrated in FIG. 40 may include a planar marking area 402b_III in which the protrusions 401_III are not formed at the center, and the marking area 402b_III also includes information about the semiconductor chip. Can be marked. The marking regions 402a_III and 402b_III in which the protrusions 401_III are not formed are not limited to the positions shown in FIGS. 39 and 40, but may be formed at more various positions of the heat sink.

In the marking areas 402a_III and 402b_III of the semiconductor package, information about the semiconductor chip, such as the type, number, performance, name and / or logo of a manufacturing company, a manufacturing date, and a serial number, may be marked.

An ink marking technique or a laser marking technique may be used to mark semiconductor information in the marking regions 402a_III and 402b_III.

More specifically, in the marking areas 402a_III and 402b_III of the heat sinks 400a_III and 400b_III, the information of the semiconductor chip may be marked using a pad printing technique as an ink marking technique. . The pad printing technique may mark semiconductor information by pushing an ink-filled palette onto a pad of silicon rubber having an embossed or intaglio pattern formed thereon so that the ink in the palette contacts the surfaces of the marking regions 402a_III and 402b_III. The pad printing technique can mark the information of the semiconductor package at low cost, and since the pad of the silicone rubber is elastic, the semiconductor information can be cleanly marked even on the surface of the uneven heat sink.

In addition, information on the semiconductor chip may be marked on the marking regions 402a_III and 402b_III of the heat sinks 400a_III and 400b_III by laser marking. The laser marking technique focuses a portion of the marking regions 402a_III and 402b_III by focusing laser light emitted from the laser apparatus onto the marking regions 402a_III and 402b_III of the heat sinks 400a_III and 400b_III. In this case, the information of the semiconductor chip can be expressed by engraving letters or numbers. In addition, the laser device may adjust the intensity of the laser light according to the intensity of the power supplied to the laser device, and thus letters and numbers formed in the marking areas 402a_III and 402b_III of the heat sinks 400a_III and 400b_III. You can adjust the thickness of.

Conventional CO ₂ laser devices, YAG laser devices, and diode laser devices may be used for the laser marking technique. The CO ₂ laser apparatus may include nitrogen (N ₂ ), carbon dioxide (CO ₂ ), and helium (He) in a resonator. When high frequency energy is delivered to the inside of the resonator, the nitrogen molecules stimulate carbon dioxide molecules, and the stimulated carbon dioxide molecules may be excited. The excited carbon dioxide molecules emit energy to return to the ground state, which can emit infrared laser light having a wavelength of about 9 micrometers to about 11 micrometers.

The YAG laser device may use YAG (Yttrium Aluminum Garnet) crystals as a laser medium. The YAG crystal may be composed of yttrium (Yd) and aluminum (Al), and the crystal structure may have a structure similar to garnet. The YAG laser device may emit laser light by adding various rare elements such as neodymium (Nd) and ytterbium (Yb) to the YAG crystal.

In the diode laser device, when a forward bias is applied to a diode, electrons and holes may be injected into the P layer of the diode. The electrons may transition to the region of the valence band and emit laser light when the electrons return to the ground state.

Laser devices used for marking semiconductor chip information of the marking regions 402a_III and 402b_III of the heat sinks 400a_III and 400b_III of the present disclosure are the above-described CO ₂ laser device, YAG laser device, and diode laser device. The present invention is not limited thereto, and may further include various laser devices.

41 is a plan view illustrating a heat sink 500_III on which information on a semiconductor package is marked according to another embodiment of the present disclosure.

Referring to FIG. 41, the heat sink 500_III is positioned on the base 503_III, the protrusion region 504_III including the plurality of protrusions 501_III protruding from the base 503_III, and the base 503_III. The semiconductor chip may include a marking region 502_III in which information of the semiconductor chip is represented. Technical features of the protrusion 501_III may be substantially the same as those of the protrusions 301a_III and 301b_III of FIGS. 36 to 38, and thus description thereof is omitted.

The marking region 502_III may protrude from an upper surface of the base portion 503_III of the heat sink 500_III. More specifically, the marking region 502_III may protrude from the upper surface of the base portion 503_III, and the upper surface of the protruding marking region 502_III may have a planar shape. The width of the upper surface of the marking area 502_III may be larger than the width of the upper surface of the one protrusion 501_III and may be smaller than the footprint of the heat sink 500_III. In one embodiment, the marking area 502_III of the heat sink 500_III may occupy about 10 percent to about 80 percent of the footprint of the heat sink 500_III.

In addition, the height of the marking area 502_III protruding from the base 503_III may be substantially the same as the height of the protrusion 501_III. Therefore, the top surface of the marking region 502_III may be coplanar with the top surface of the protrusions 501_III of the protrusion region 504_III. The height at which the marking area 502_III protrudes from the base 503_III and the height at which the protrusions 501_III protrude from the base 503_III are between about 40 percent and about 60 percent of the total thickness of the heat sink 500_III. It can be characterized by.

The upper surface of the marking area 502_III may express the information of the semiconductor chip by the above-described ink marking technique or laser marking technique.

The heat sink 500_III may include the plurality of protrusions 501_III by cutting a portion of a rectangular parallelepiped heat sink having a predetermined thickness through a cutting device, and the remaining marking portion (501_III). 502_III).

In FIG. 41, the marking region 502_III is illustrated as being formed on the upper left side of the heat sink 500_III. However, the marking region 502_III may be formed at various locations of the heat sink 500_III without being limited to the position.

The heat sink 500_III of FIG. 41 may have a larger cross-sectional area in contact with outside air than the heat sinks 400a_III and 400b_III of FIGS. 39 and 40 due to the shape of the marking area 502_III formed to protrude. May be better.

42 is a plan view illustrating a heat sink 600_III on which information on a semiconductor package is marked according to another exemplary embodiment of the present disclosure.

The heat sink 600_III includes a base portion 602_III to be positioned on an upper surface of an encapsulant of the semiconductor package, a first region 603_III and first base portions 601a_III protruding from the base portion 602_III. The second region 604_III including the second protrusions 601b_III protruding from the 602_III may be included. The first protrusion 601a_III, the second protrusion 601b_III, and the base 602_III are substantially the technical concepts of the protrusions 302a_III, 302b_III, and the base 301_III of the heat sinks 300a_III, 300b_III shown in FIG. May be the same. However, the thicknesses of the first and second protrusions 601a_III and 601b_III formed in the heat sink 600_III may be described later with reference to the protrusions 302a_III and 302b_III of the heat sinks 300a_III and 300b_III illustrated in FIG. 36. May be different from the thickness (f ₂ _III).

As illustrated in FIG. 42, the heat sink 600_III may include first protrusions 601a_III protruding from the base portion 602_III in the first region 603_III, and the second region ( 604_III) may include second protrusions 601b_III protruding from the base 602_III.

The first region 603_III may include continuous letters and numbers indicating information of the semiconductor package on the top of the base portion 602_III and the first protrusions 601a_III. More specifically, the information of the semiconductor chip may be expressed on an upper surface of the base portion 602_III and an upper surface of the first protrusion 601a_III disposed under the first region 603_III. Information of the semiconductor chip may be marked by marking part of the base portion 602_III and part of the first protrusion portion 601a_III by a laser device, and also part of the base portion 602_III and the first protrusion portion 601a_III. The ink may be marked in a portion of the).

In order to include consecutive letters and numbers in the upper surface of the first protrusions 601a_III and the base 602_III in the first region 603_III, the thickness formed by the first protrusions 601_III is smaller. good. The smaller the thickness of the first protrusions 601_III is, the smaller the change in the height of the point where the laser light is collected in the case of laser marking can be in the shape of letters and numbers inscribed, in the case of ink marking This is because the change in the length that the pad of the silicone rubber has to be stretched by elasticity can be small.

Therefore, the height formed by the first protrusions 601a_III in the first region 603_III of the heat sink 600_III is the second of the second region 604_III in which the marking region 603_III is not formed. The second protrusions 601b_III may be substantially smaller than the height formed. In an embodiment, the height formed by the first protrusions 601a_III may be between about 1/4 and about 1/2 of the height formed by the second protrusions 601b_III. In an embodiment, the total thickness of the heat sink 600_III is about 400 micrometers, the thickness of the base 602_III is about 200 micrometers, and the height of the second protrusions 601b_III is about 200 micrometers. , The height of the first protrusions 601a_III may be about 2 to about 4 times smaller than the height of the second protrusions 601b_III. Accordingly, the height of the first protrusions 601a_III may be about 50 micrometers to about 100 micrometers.

Due to the low height of the first protrusions 601a_III formed in the first region 603_III of the heat sink 600_III, the heat sink 600_III is the base portion 602_III of the first region 603_III. And continuous letters and numbers on upper surfaces of the first protrusions 601a_III to represent information of the semiconductor package. In the case of laser marking, a change in the height of the point where the laser light is collected in the first region 603_III may be about 50 micrometers to about 100 micrometers. Accordingly, letters and numbers may be continuously marked in an ordered shape in the first region 603_III without controlling the height of the light converging point of the laser light. In addition, even when controlling the height of the light collecting point of the laser light, only about 50 micrometers to about 100 micrometers of position control of the laser device may be necessary, so that energy consumption may be low when driving the laser device, and the laser device is driven. The control time of can be reduced.

In the case of ink marking, since the change in the length that the pad of the silicone rubber has to be stretched by elasticity may be small from about 50 micrometers to about 100 micrometers, the first protrusions 601a_III of the first region 603_III may be formed. Letters and numbers representing semiconductor information may be marked on the top surface and the base portion 602_III in a more orderly shape.

43 to 49 are views for explaining a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

43 illustrates one step of a method of manufacturing a semiconductor package for attaching a metal frame onto a glass substrate as an embodiment of the present disclosure. Referring to FIG. 43, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a metal frame 102_III to an upper surface of a glass substrate 701_III. An adhesive layer (not shown) may be formed on an upper surface of the glass substrate 701_III. The metal frame 102_III may be physically attached to an upper surface of the glass substrate 701_III by the adhesive layer (not shown).

44 illustrates one step of a method for manufacturing a semiconductor package for mounting a semiconductor chip on a glass substrate, which is an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include mounting a semiconductor chip 101_III on a glass substrate 701_III. The semiconductor chip 101_III may be mounted in the cavity of the metal frame 102_III attached to the glass substrate 701_III and mounted on the glass substrate 701_III.

45 illustrates a step of a method of manufacturing a semiconductor package in which the semiconductor chip 101_III and the metal frame 102_III are covered and sealed with the encapsulant 104_III, which is an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include encapsulating the encapsulant 104_III to cover and seal the semiconductor chip 101_III and the metal frame 102_III. The encapsulant 104_III may integrate the semiconductor chip 101_III and the metal frame 102_III by filling a space formed between the semiconductor chip 101_III and an inner wall of the metal frame 102_III. In addition, the encapsulant 104_III may cover the top surfaces of the semiconductor chip 101_III and the metal frame 102_III.

In an embodiment, the upper surface of the semiconductor chip 101_III and the encapsulant 104_III covering the upper surface of the metal frame 102_III is ground to grind the upper surface of the semiconductor chip 101_III or the metal frame 102_III. The method may further include exposing.

46 illustrates one step of a method of manufacturing a semiconductor package for attaching a heat sink 107_III to a semiconductor package, which is an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a heat sink 107_III on a semiconductor package. The heat sink 107_III may have a concave-convex structure as described above, and the heat sink 107_III of the concave-convex structure may include heat sinks which are embodiments of the present disclosure described above. Accordingly, the heat sink 107_III may include a marking region in which letters and numbers indicating the information of the semiconductor package are formed.

The heat sink 107_III may be attached to an upper surface of the semiconductor chip 101_III or an upper surface of the encapsulant 104_III. The method of arranging the heat sink 107_III in close contact with the upper surface of the semiconductor chip 101_III may include a thermocompression bonding method. The thermal compression method is to apply heat and pressure to the adhesive film located under the heat sink 107_III using a compression machine. Through the thermal compression method, the adhesive film may stably attach the heat sink 107_III to the top surface of the semiconductor chip 101_III and the encapsulant 104_III.

FIG. 47 illustrates one step of a method of fabricating a semiconductor package that removes the glass substrate 701_III and inverts the semiconductor package according to an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include inverting the semiconductor package by separating the glass substrate 701_III.

48 illustrates a step of a method of manufacturing a semiconductor package for forming a redistribution layer and an external connection terminal according to an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include forming a redistribution layer 103_III. The redistribution layer 103_III may include a wiring pattern 1201_III and an insulation pattern 1202_III. In an exemplary embodiment of the present disclosure, the insulating pattern 1202_III may include a non-photosensitive material, and after the insulating pattern 1202_III is formed on the bottom surface of the semiconductor chip 101_III, the insulating pattern 1202_III may be a semiconductor. It may be partially removed to expose the chip pad 113_III of the chip 101_III. After the insulating pattern 1202_III is formed, the wiring pattern 1201_III may be electrically connected to the chip pad 113_III exposed by the opening of the insulating pattern 1202_III. The wiring pattern 1201_III may be formed by plating, electroless plating, electroplating, or a combination thereof, and may be formed on the insulating pattern 1202_III through a plating process. When the wiring pattern 1201_III is formed, the insulating pattern 1202_III may be formed on the wiring pattern 1201_III again. In this case, a part of the wiring pattern 1201_III may be partially exposed to be connected to the external connection terminal 105_III.

Referring to FIG. 48, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching an external connection terminal 105_III. The external connection terminal 105_III may be a solder ball. The external connection terminal 105_III may be attached to the exposed wiring pattern 1201_III through a soldering process.

49 illustrates one step of a semiconductor package manufacturing method for cutting a plurality of semiconductor packages into individual packages according to an embodiment of the present disclosure. The process of cutting the plurality of semiconductor packages into individual packages may sequentially cut the redistribution layer 103_III, the metal frame 102_III, the encapsulant 104_III, and the heat sink 107_III of the semiconductor package using a cutting blade. Can cut

50 is a block diagram schematically illustrating an electronic system 1400_III including a semiconductor package according to an embodiment of the present disclosure. The electronic system 1400_III may include at least one of semiconductor packages of various embodiments of the inventive concept. The electronic system 1400_III may be included in a mobile device or a computer. For example, the electronic system 1400_III may include a memory system 1401_III, a microprocessor 1402_III, a RAM 1403_III, and a user interface 1404_III that performs data communication.

Thereafter, in the cross-sectional views of the attached semiconductor package, the length along the longitudinal direction Z may be defined as the thickness, and the length along the horizontal direction X which is perpendicular to the vertical direction Z may be defined as the width. Can be defined.

In addition, the term footprint, which will be used below, may be defined as an area occupied by the component in the X-Y plane when the component is viewed from the top to the bottom (ie, when viewed from the + Z direction to the -Z direction).

51 is a perspective view illustrating a semiconductor package 100_IV according to an embodiment of the present disclosure, and FIGS. 52 and 53 are cross-sectional views of semiconductor packages 100a_IV and 100b_IV according to an embodiment of the present disclosure. The semiconductor packages 100_IV, 100a_IV, and 100b_IV may be fan-out wafer level packages (FOWLPs) or panel level packages (PLPs).

51 to 53, the semiconductor packages 100_IV, 100a_IV, and 100b_IV according to the exemplary embodiment of the present invention may each include a semiconductor chip 101_IV, an encapsulant 102_IV, a redistribution layer 103_IV, and an external connection. The terminal 104_IV, the adhesive film 105_IV, and the heat sink 106_IV may be included. The semiconductor packages 100_IV, 100a_IV, and 100b_IV may be semiconductor packages having a wafer level package (WLP) structure, specifically, semiconductor packages having a fan-out wafer level package structure. Can be. Each thickness of the semiconductor packages 100_IV, 100a_IV, 100b_IV may be between about 1.1 millimeters and about 1.4 millimeters. However, the semiconductor packages 100_IV, 100a_IV, and 100b_IV may have various thicknesses without being limited to the above thicknesses.

The semiconductor chip 101_IV illustrated in FIGS. 52 and 53 may include various types of individual devices. For example, the plurality of individual devices may be a variety of microelectronic devices, for example a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale (LSI). image sensors such as integration (CIS), CMOS imaging sensors (CIS), and the like, micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.

In an embodiment, the semiconductor chip 101_IV may be a memory semiconductor chip. The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a phase-change random access memory (PRAM), or a magneto-resistive random access memory (MRAM). ), Or a nonvolatile memory semiconductor chip such as ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM).

In one embodiment, the semiconductor chip 101_IV may be a logic chip. For example, the semiconductor chip 101_IV may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

52 and 53, the semiconductor packages 100a_IV and 100b_IV are illustrated as including one semiconductor chip 101_IV, but the semiconductor packages 100a_IV and 100b_IV may include two or more semiconductor chips 101_IV. Can be. Two or more semiconductor chips 101_IV included in the semiconductor packages 100a_IV and 100b_IV may be the same type of semiconductor chip or different types of semiconductor chips. In an embodiment, the semiconductor packages 100a_IV and 100b_IV may be system in packages (SIPs) in which different types of semiconductor chips are electrically connected to each other and operate as one system.

In example embodiments, the semiconductor chip 101_IV may include a lower surface 111_IV and an upper surface 112_IV facing the lower surface 111_IV. In addition, the semiconductor chip 101_IV may include a chip pad 113_IV on a lower surface 111_IV. The chip pad 113_IV may be electrically connected to a plurality of individual elements of various kinds formed on the semiconductor chip 101_IV. The chip pad 113_IV may have a thickness between about 0.5 micrometers and about 1.5 micrometers. 52 and 53, the semiconductor chip 101_IV may include a passivation layer covering the lower surface 111_IV.

51 to 53, the encapsulant 102_IV may surround the semiconductor chip 101_IV and may protect the semiconductor chip 101_IV. In addition, the encapsulant 102_IV may cover the semiconductor chip 101_IV and may fix the semiconductor chip 101_IV on the redistribution layer 103_IV to be described later. The encapsulant 102_IV may include, for example, a silicone-based material, a thermosetting material, a thermoplastic material, a UV treated material, and the like, and may include, for example, a polymer such as resin, for example, an epoxy molding. It may include a compound (Epoxy Molding Compound, EMC).

As illustrated in FIG. 52, the encapsulant 102_IV may cover the upper surface 112_IV and the side surface of the semiconductor chip 101_IV. In this case, the height difference between the top surface 112_IV of the semiconductor chip 101_IV and the top surface of the encapsulant 102_IV may be about 1 micrometer to about 10 micrometers.

In an embodiment, as illustrated in FIG. 53, the encapsulant 102_IV may cover the side surface of the semiconductor chip 101_IV, but may expose the top surface 112_IV of the semiconductor chip 101_IV. As the upper surface 112_IV of the semiconductor chip 101_IV is exposed, the thickness of the semiconductor package 100b_IV may be reduced. In addition, the heat generated in the semiconductor chip 101_IV passes through the adhesive film 105_IV and the heat sink 106_IV on the upper surface 112_IV of the semiconductor chip 101_IV, which will be described later, without passing through the encapsulant 102_IV. Since it may be emitted to the outside, the heat dissipation performance of the semiconductor package 100b_IV may be improved.

51 to 53, the semiconductor packages 100_IV, 100a_IV, and 100b_IV may include an adhesive film 105_IV. The adhesive film 105_IV may contact at least one of the top surface 112_IV of the semiconductor chip 101_IV and the top surface of the encapsulant 102_IV. The adhesive film 105_IV may include a material having excellent adhesion to the encapsulant 102_IV and the semiconductor chip 101_IV. The adhesive film 105_IV may include a conductive material or a non-conductive material. For example, the adhesive film 105_IV may include an epoxy resin. In addition, the adhesive film 105_IV may include a filler having excellent thermal conductivity, for example, silver, aluminum, silicon dioxide, aluminum nitride, boron nitride, and the like, and have aluminum oxide having thermal conductivity to maintain rigidity. It may include. The adhesive film 105_IV may have adhesive properties by itself, and may also be provided by being bonded with a separate thermal conductive adhesive tape. The adhesive tape may be a double-sided adhesive tape. The thickness of the adhesive film 105_IV formed on the semiconductor packages 100_IV, 100a_IV, and 100b_IV may be about 5 micrometers to about 20 micrometers, and more specifically, about 10 micrometers to about 14 micrometers.

In an embodiment, the width of the first direction X of the adhesive film 105_IV may be greater than the width of the heat sink 106_IV. However, the present invention is not limited thereto, and the width of the adhesive film 105_IV in the first direction X may be substantially the same as that of the heat sink 106_IV.

In an embodiment, as shown in the drawing, the width of the first direction X of the adhesive film 105_IV may be substantially the same as the width of the first direction X of the semiconductor package 100_IV. However, the present invention is not limited thereto, and the width of the first direction X of the adhesive film 105_IV may be smaller than the width of the first direction X of the semiconductor package 100_IV.

In an embodiment, the width of the first direction X of the adhesive film 105_IV is greater than the width of the first direction X of the heat sink 106_IV and the width of the first direction X of the semiconductor package 100_IV. It can be smaller than the width. In addition, the width of the first direction X of the adhesive film 105_IV is greater than the width of the first direction X of the heat sink 106_IV, and substantially the width of the first direction X of the semiconductor package 100_IV. May be the same. In addition, the width of the first direction X of the adhesive film 105_IV may be substantially the same as the width of the first direction X of the heat sink 106_IV, and the first direction X of the semiconductor package 100_IV. May be smaller than In addition, the width of the first direction X of the adhesive film 105_IV is substantially the same as the width of the first direction X of the heat sink 106_IV and the width of the first direction X of the semiconductor package 100_IV. You may.

In one embodiment, when the footprint of the adhesive film 105_IV is smaller than the footprint of the semiconductor package 100_IV, and the footprint of the heat sink 106_IV is smaller than the footprint of the adhesive film 105_IV, the semiconductor package 100_IV When viewed from the top to the bottom, the top surface of the encapsulant 102_IV and the top surface of the adhesive film 105_IV may be exposed. When the semiconductor package 100_IV is viewed from top to bottom, an area where the top surface of the encapsulant 102_IV and the top surface of the adhesive film 105_IV are exposed is about 5% to about 40% of the area of the top surface of the semiconductor package 100_IV. Can be.

In one embodiment, when the footprint of the adhesive film 105_IV is substantially the same as the footprint of the semiconductor package 100_IV, and the footprint of the heat sink 106_IV is smaller than the footprint of the adhesive film 105_IV, the semiconductor When looking at the package 100_IV from the top down, the top surface of the encapsulant 102_IV may not be exposed, and the top surface of the adhesive film 105_IV may be exposed. When the semiconductor package 100_IV is viewed from the top to the bottom, the area where the top surface of the adhesive film 105_IV is exposed may be about 5% to about 40% of the area of the top surface of the semiconductor package 100_IV.

51 to 53, the semiconductor packages 100_IV, 100a_IV, and 100b_IV may include a redistribution layer 103_IV. The redistribution layer 103_IV may be formed on the lower surface 111_IV of the semiconductor chip 101_IV to electrically connect the chip pad 113_IV and the external connection terminal 104_IV of the semiconductor chip 101_IV. The semiconductor packages 100_IV, 100a_IV, and 100b_IV may form the external connection terminal 104_IV in a region outside the footprint of the bottom surface 111_IV of the semiconductor chip 101_IV through the redistribution layer 103_IV. An efficient external connection terminal 104_IV may be disposed in the semiconductor package 100_IV through the redistribution layer 103_IV.

Although not shown in FIGS. 51 to 53, the redistribution layer 103_IV may include a wiring pattern and an insulation pattern. The wiring pattern may be electrically connected to the chip pad 113_IV formed on the bottom surface 111_IV of the semiconductor chip 101_IV, and may provide an electrical connection path for electrically connecting the chip pad 113_IV to an external device. . The insulating pattern may serve to protect a wiring pattern electrically connected to the chip pad 113_IV from an external shock and prevent a short circuit. For example, the insulating pattern may include a photosensitive material such as polyimide or epoxy. However, the present invention is not limited thereto, and the insulating pattern may be formed of a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

51 to 53, the semiconductor packages 100_IV, 100a_IV, and 100b_IV may include external connection terminals 104_IV. The external connection terminal 104_IV may be positioned on the bottom surface of the redistribution layer 103_IV and may be electrically connected to the wiring pattern of the redistribution layer 103_IV. The semiconductor packages 100_IV, 100a_IV, and 100b_IV may be electrically connected to an external device, such as a system board or a main board, by the external connection terminal 104_IV. The external connection terminal 104_IV may include solder balls, as shown in FIGS. 51 to 53. The solder ball may include at least one of tin, silver, copper, and aluminum. In addition, the solder ball may have a ball shape as illustrated in FIGS. 51 to 53, but is not limited thereto. The solder ball may have various shapes such as a cylinder, a polygonal column, and a polyhedron.

51 to 53, the semiconductor packages 100_IV, 100a_IV, and 100b_IV may include a heat sink 106_IV. The heat sink 106_IV may be on top of the adhesive film 105_IV. The heat sink 106_IV may effectively radiate heat generated from the semiconductor chip 101_IV in the semiconductor package 100_IV to the outside.

Referring to FIG. 52, heat generated in the semiconductor chip 101_IV in the semiconductor package 100a_IV may be generated by the upper surface 112_IV, the encapsulant 102_IV, the adhesive film 105_IV, and the heat sink 106_IV of the semiconductor chip 101_IV. ) May be emitted to the outside sequentially. In addition, the thickness of the encapsulant 102_IV may be greater than the thickness of the semiconductor chip 101_IV, and the upper surface of the semiconductor chip 101_IV is covered by the encapsulant 102_IV, and the upper surface of the encapsulant 102_IV is an adhesive film. Can be in contact with (105_IV).

Referring to FIG. 53, heat generated from the semiconductor chip 101_IV in the semiconductor package 100b_IV is sequentially passed through the top surface 112_IV, the adhesive film 105_IV, and the heat sink 106_IV of the semiconductor chip 101_IV. Can be released. Since the encapsulant 102_IV may not be formed between the upper surface 112_IV of the semiconductor chip 101_IV and the adhesive film 105_IV, the heat transfer resistance of the heat in the path of heat generated in the semiconductor chip 101_IV may be reduced. The heat resistance of the heat of the package 100a_IV may be smaller, and accordingly, the heat dissipation performance of the semiconductor package 100b_IV may be improved. In addition, the thickness of the encapsulant 102_IV may be substantially the same as the thickness of the semiconductor chip 101_IV, and an upper surface of the semiconductor chip 101_IV may be exposed by the encapsulant 102_IV, and the semiconductor chip 101_IV may be exposed. The top surface and the top surface of the encapsulant 102_IV may be in contact with the adhesive film 105_IV.

In an embodiment, the heat sinks 106_IV of the semiconductor packages 100_IV, 100a_IV, and 100b_IV may include metal materials, ceramic materials, carbon materials, and polymer materials having various thermal conductivity.

More specifically, the heat sink 106_IV of the metallic material includes aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and about 380 W / m. Metal-based materials such as copper (Cu) with a thermal conductivity of K, nickel (Ni) with a thermal conductivity of about 90 W / mK and silver (Ag) with a thermal conductivity of about 410 W / m · K Can be.

The ceramic heat sink 106_IV includes boron nitride (BN) having a thermal conductivity of about 1800 W / m · K, aluminum nitride (AlN) having a thermal conductivity of about 320 W / m · K, and about 30 W / m. Aluminum oxide (Al ₂ O ₃ ) with a K thermal conductivity, silicon carbide (SiC) with a thermal conductivity of about 480 W / m · K, and beryllium oxide (BeO) with a thermal conductivity of about 270 W / m · K It may include a ceramic-based material.

The heat sink 106_IV of the carbon-based material includes diamond having a thermal conductivity of about 2500 W / m · K, carbon fiber having a thermal conductivity of about 100 W / m · K, and about 5 W / m · K to about 1950 W / m. Carbon-based materials such as graphite having a thermal conductivity of K, carbon nanotubes having a thermal conductivity of about 1.5 W / m · K to about 3500 W / m · K, and graphene having a thermal conductivity of about 5000 W / m · K. It may include.

The heat sink 106_IV of the polymer material may include a polymer material such as polyethylene having an ultra high molecular weight having a thermal conductivity of about 45 W / m · K to about 100 W / m · K.

However, the heat sink 106_IV is not limited to the metal-based material, the cerium-based material, the carbon-based material, and the polymer-based material described above, and may include a combination of the above materials or other materials not shown above.

In one embodiment, the heat sink 106_IV may be formed in various thicknesses v_IV. More specifically, the thickness v_IV of the heat sink 106_IV may occupy about 25 percent to about 40 percent of the thickness of the semiconductor packages 100_IV, 100a_IV, and 100b_IV. In one embodiment, the thickness of the semiconductor packages 100_IV, 100a_IV, 100b_IV may be from about 1.1 millimeters to about 1.4 millimeters, so that the thickness v_IV of the heat sink 106_IV may be from about 280 micrometers to about 560 micrometers. have.

52 and 53, the thickness t_IV of the semiconductor chip 101_IV may be greater than or equal to the thickness v_IV of the heat sink 106_IV. However, the present disclosure is not limited thereto, and the thickness t_IV of the semiconductor chip 101_IV may be smaller than the thickness v_IV of the heat sink 106_IV.

54 is a cross-sectional view of a semiconductor package 100c_IV according to an embodiment of the present disclosure. Referring to FIG. 54, a width in the first direction X of the heat sink 106_IV may be greater than or equal to a width in the first direction X of the semiconductor chip 101_IV. In addition, the footprint of the heat sink 106_IV may be greater than or equal to the footprint of the semiconductor chip 101_IV. Accordingly, the heat sink 106_IV may effectively radiate heat generated from the semiconductor chip 101_IV to the outside.

In an embodiment, the width of the first direction X of the semiconductor chip 101_IV of the semiconductor package 100c_IV of the present disclosure may be smaller than the width of the first direction X of the heat sink 106_IV. In addition, the width of the first direction X of the heat sink 106_IV may be smaller than the width of the first direction of the semiconductor package 100c_IV. For example, the width of the semiconductor chip 100c_IV may be smaller than the width of the heat sink 106_IV, and at the same time, the width of the heat sink 106_IV may be smaller than the width of the semiconductor package 100c_IV. However, the present invention is not limited thereto, and the width of the semiconductor chip 101_IV may be substantially the same as the width of the heat sink 106_IV. The width of the heat sink 106_IV may be greater than the width of the semiconductor chip 101_IV or may be substantially the same as the width of the semiconductor chip 101_IV, so that the heat generated in the semiconductor chip 101_IV may be reduced by the heat sink 106_IV. It is easily delivered to the lower surface can be improved heat dissipation effect.

In addition, the thickness v_IV of the heat sink 106_IV may be smaller than the thickness t_IV of the semiconductor chip 101_IV, and may be substantially the same. However, the present invention is not limited thereto, and the thickness v_IV of the heat sink 106_IV may be greater than the thickness t_IV of the semiconductor chip 101_IV. In one embodiment, the sum (v_IV + t_IV) of the thicknesses of the semiconductor chip 101_IV and the heat sink 106_IV may account for about 60% to 95% of the total thickness of the semiconductor package.

55 and 56 are cross-sectional views of semiconductor packages 100d_IV and 100e_IV according to an embodiment of the present disclosure. Referring to FIGS. 55 and 56, the heat dissipation molding part 107_IV is formed on the encapsulant 102_IV (more specifically, on the top surface of the adhesive film 105_IV on the encapsulant 102_IV), and the heat sink 106_IV is formed. The heat sink 106_IV may be surrounded to cover at least a portion of the side surface. The heat dissipation molding part 107_IV may include various materials such as a metal material, a ceramic material, a carbon material, and a polymer material. In one embodiment, the heat dissipation molding part 107_IV may be an epoxy molding compound. By covering at least a portion of the side surface of the heat sink 106_IV with the heat dissipation molding part 107_IV, heat generated in the semiconductor chip 101_IV may be concentrated at the center of the heat sink 106_IV. In addition, before the semiconductor packages 100d_IV and 100e_IV are individualized, processing, transportation, and cutting processes of the heat sinks 106_IV may be facilitated by the heat dissipation molding part 107_IV surrounding the heat sinks 106_IV. .

Referring to FIG. 55, the heat dissipation molding part 107_IV may be positioned on the encapsulant 102_IV and may surround the heat sink 106_IV to cover only one region of the side surface of the heat sink 106_IV. . Accordingly, one portion of the side surface of the heat sink 106_IV may be exposed to the outside. In addition, a height difference between the top surface of the heat sink 106_IV and the top surface of the heat dissipation molding part 107_IV may occur. Accordingly, a step D1_IV may occur at the edge of the heat sink 106_IV.

Referring to FIG. 56, the heat dissipation molding part 107_IV may be positioned on the encapsulant 102_IV and may surround the heat sink 106_IV to cover all of the side surfaces of the heat sink 106_IV. Accordingly, the side surface of the heat sink 106_IV may not be exposed to the outside. In addition, the top surface of the heat sink 106_IV and the top surface of the heat dissipation molding part 107_IV may be substantially the same height.

57 is a view illustrating a semiconductor package 200_IV according to an embodiment of the present disclosure. The semiconductor package 200_IV may include a semiconductor chip 101_IV, an encapsulant 102_IV, a redistribution layer 103_IV, an external connection terminal 104_IV, an adhesive film 105_IV, and a heat sink 106_IV. The technical concepts of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, the adhesive film 105_IV, and the heat sink 106_IV will be described with reference to FIGS. 51 to 53. Since it is substantially the same as the technical idea demonstrated, detailed description is abbreviate | omitted.

In an embodiment, the semiconductor package 200_IV may further include a protrusion 201_IV extending from the side surface of the heat sink 106_IV to the side surface of the semiconductor package 200_IV. The protrusion 201_IV may be one region of the remaining connection area S_IV after the connection area S_IV of the group of heat sinks (FIGS. 58 and 250_IV) to be described later is cut by the individualization process of the semiconductor package 200_IV. have.

In one embodiment, the top surface of the protrusion 201_IV may be at the same height as the top surface of the heat sink 106_IV. In addition, the outer surface 201a_IV of the protrusion 201_IV may be self-aligned with the side surface of the semiconductor package 200_IV. In addition, the protrusion 201_IV may be integrated with the heat sink 106_IV.

In an embodiment, the plurality of protrusions 201_IV may extend from one side of the heat sink 106_IV to one side of the semiconductor package 200_IV. For example, as illustrated in FIG. 57, two protrusions 201_IV may extend from one side of the heat sink 106_IV to one side of the semiconductor package 200_IV. However, the number of protrusions 201_IV extending from one side of the heat sink 106_IV to one side of the semiconductor package 200_IV may be various, without being limited to the above.

In an embodiment, when the number of protrusions 201_IV extending from one side of the heat sink 106_IV to one side of the semiconductor package 200_IV is plural, the heat sinks between the plurality of protrusions 201_IV may be formed. A step D2_IV may occur due to a height difference between the top surface of the substrate 106_IV and the top surface of the adhesive film 105_IV. The number of steps D2_IV formed at one side of the heat sink 106_IV may be different depending on the number of protrusions 201_IV formed at one side of the heat sink 106_IV. For example, referring to FIG. 57, when the number of protrusions 201_IV formed at one side of the heat sink 106_IV is two, the number of steps D2_IV formed at one side of the heat sink 106_IV is shown. May be three.

In an embodiment, the number of protrusions 201_IV extending from one side of the heat sink 106_IV to one side of the semiconductor package 200_IV may be one. When the number of protrusions 201_IV formed at one side of the heat sink 106_IV is one, the number of steps D2_IV formed at one side of the heat sink 106_IV may be two.

In one embodiment, the material of the protrusion 201_IV may be different from the material of the heat sink 106_IV. For example, the material of the protrusion 201_IV may be less rigid than the material of the heat sink 106_IV. In an embodiment, the protrusion 201_IV may include a metal material, a ceramic material, a carbon material, and a polymer material. Accordingly, the connection region S_IV may be easily cut in the process of individualizing the semiconductor package 200_IV to be described later.

FIG. 58 is a plan view of a group of heat sinks 250_IV to which a plurality of heat sinks 106_IV are connected, according to an embodiment of the present disclosure. FIG. 59 is a cross-sectional view at A_IV-A_IV of FIG. 58 of a population 250_IV of heat sinks as one embodiment of the present disclosure, and FIG. 60 is B_IV- of FIG. 58 of a population 250_IV as one embodiment of the present disclosure. It is sectional drawing in B_IV.

58 to 60, the heat sinks 106_IV may be interconnected with the other heat sinks 106_IV by the connection region S_IV to form a group 250_IV of heat sinks. More specifically, the heat sink 106_IV may be connected with the other heat sinks 106_IV and the connection region S_IV in four directions of the side surfaces of the heat sink 106_IV to form a population 250_IV of the heat sinks. have.

In an embodiment, the connection region S_IV may have a first length w_IV which is a length value of the first direction X, and a second value Y which is a length value of the second direction Y perpendicular to the first direction X. It may have a length t_IV. The first length w_IV and the second length t_IV may be determined as various values.

In an embodiment, the population 250_IV of the heat sinks is formed on the top surface of the adhesive film 105_IV of the plurality of semiconductor packages 200_IV before the plurality of semiconductor packages 200_IV are cut into individual semiconductor packages 200_IV. Can be positioned and fixed. The heat sinks 106_IV may form the population 250_IV of the heat sinks by the connection region S_IV, so that the population of the heat sinks 250_IV can be easily aligned and mounted on the upper surfaces of the semiconductor packages 200_IV. Can be. In addition, after placing the group of heat sinks 250_IV on the adhesive film 105_IV, heat and pressure may be applied to the adhesive film 105_IV. The adhesive film 105_IV may stably fix the group 250_IV of heat sinks on the plurality of semiconductor packages 200_IV.

In one embodiment, when the population of heat sinks 250_IV is stably mounted on the plurality of semiconductor packages 200_IV, the plurality of semiconductor packages 200_IV are cut into individual semiconductor packages 200_IV through a cutting process. Can be cut. Referring to FIG. 58, a cutting line L_IV may be formed on the plurality of connection regions S_IV. Since the cutting line L_IV may be formed on the connection region S_IV having the first length w_IV and the second length t_IV, the first length w_IV and the second length t_IV of the connection region S_IV The smaller the value), the easier the cutting process of cutting the plurality of semiconductor packages 200_IV mounted with the group of heat sinks 250_IV into individual semiconductor packages 200_IV.

In addition, since the population of heat sinks 250_IV is integrally handled, embodiments of the present disclosure may provide ease in the process of processing, transporting, and cutting the population of heat sinks 250_IV.

FIG. 61 is a cross-sectional view taken along line A_IV-A_IV of FIG. 58 of a plurality of semiconductor packages 200_IV on which a group of heat sinks 250_IV are mounted, and FIG. 62 is a heat sink that is an embodiment of the present disclosure. A cross-sectional view in B_IV-B_IV of FIG. 58 of a plurality of semiconductor packages 200_IV mounted with a group of fields 250_IV.

Referring to FIG. 61, due to the difference in height between the top surface of the heat sink 106_IV and the top surface of the adhesive film 105_IV in a portion where the connection region S_IV is not formed (that is, the space between the connection regions S_IV). A step D2_IV may be formed.

Referring to FIG. 62, a step D2_IV may not be formed in a portion where the connection region S_IV is formed.

Referring to FIG. 61, the cutting process of the semiconductor packages 200_IV sequentially cuts the adhesive film 105_IV, the encapsulant 102_IV, and the redistribution layer 103_IV at a portion where the connection region S_IV is not formed. Process may be included. In addition, referring to FIG. 62, in the cutting process of the semiconductor packages 200_IV, the connection region S_IV, the adhesive film 105_IV, the encapsulant 102_IV, and the redistribution layer 103_IV are formed at the portion where the connection region S_IV is formed. ) May be sequentially cut. As described above, when the rigidity of the material of the connection region S_IV is weaker than that of the material of the heat sink 106_IV, the cutting process may be easy. In addition, the cutting process may be facilitated by minimizing the first length w_IV and the second length t_IV of the connection region S_IV.

FIG. 63 is an enlarged view of a side of a semiconductor package 200_IV that is an embodiment of the present disclosure. Referring to FIG. 63, the outer surface 201a_IV of the protrusion 201_IV of the semiconductor package 200_IV, the side of the adhesive film 105_IV, the side of the encapsulant 102_IV, and the side of the redistribution layer 103_IV The surfaces may be cut in the cutting process of the semiconductor package 200_IV. Accordingly, the grains of the outer surface 201a_IV of the protrusion 201_IV, the side surface of the adhesive film 105_IV, the side surface of the encapsulant 102_IV, and the side surface of the redistribution layer 103_IV may be substantially the same. The grain may mean a pattern or roughness formed on the surface.

In an embodiment, the side surface 106a_IV of the heat sink 106_IV of the semiconductor package 200_IV may be a surface that is not cut in the cutting process. Accordingly, the texture of the side surface 106a_IV of the heat sink 106_IV is formed by the outer surface 201a_IV of the protrusion 201_IV, the side surface of the adhesive film 105_IV, the side surface of the encapsulant 102_IV, and the redistribution layer 103_IV. The results of the aspects of the can be mutually different.

64 is a plan view of a semiconductor package 200a_IV according to an embodiment of the present disclosure. The semiconductor package 200a_IV may include a semiconductor chip 101_IV, an encapsulant 102_IV, a redistribution layer 103_IV, an external connection terminal 104_IV, an adhesive film 105_IV, and a heat sink 106_IV. The technical concepts of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, the adhesive film 105_IV, and the heat sink 106_IV will be described with reference to FIGS. 51 to 53. Since it is substantially the same as the technical idea demonstrated, detailed description is abbreviate | omitted.

Referring to FIG. 64, the footprint of the adhesive film 105_IV may be smaller than the footprint of the semiconductor package 200a_IV. In addition, the footprint of the adhesive film 105_IV may be smaller than the footprint of the encapsulant 102_IV. As illustrated in FIG. 64, the footprint of the adhesive film 105_IV may be larger than the footprint of the heat sink 106_IV and smaller than the footprint of the encapsulant 102_IV.

In one embodiment, when the semiconductor package 200a_IV is viewed from above, at least one of the adhesive film 105_IV and the encapsulant 102_IV may be exposed to the outside and observed. For example, as shown in FIG. 64, when the footprint of the adhesive film 105_IV is larger than the footprint of the heat sink 106_IV and smaller than the footprint of the encapsulant 102_IV, the semiconductor package 200a_IV may be removed. When viewed from top to bottom, both the adhesive film 105_IV and the encapsulant 102_IV may be exposed to the outside.

However, the present invention is not limited thereto, and as illustrated in FIG. 57, when the footprint of the adhesive film 105_IV is larger than the footprint of the heat sink 106_IV and is substantially the same as the footprint of the encapsulant 102_IV, the semiconductor package When looking down 200_IV from above, the encapsulant 102_IV is not exposed to the outside, and only the adhesive film 105_IV may be exposed to the outside.

In one embodiment, when looking down the semiconductor packages 200_IV and 200a_IV, the sum of the exposed areas of the adhesive film 105_IV and the encapsulant 102_IV is about 5 of the area of the top surface of the semiconductor packages 200_IV and 200a_IV. % To about 40%.

65 and 66 are perspective views of semiconductor packages 200b_IV and 200c_IV according to an embodiment of the present disclosure. The semiconductor packages 200b_IV and 200c_IV may include a semiconductor chip 101_IV, an encapsulant 102_IV, a redistribution layer 103_IV, an external connection terminal 104_IV, an adhesive film 105_IV, and a heat sink 106_IV. . The technical concepts of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, the adhesive film 105_IV, and the heat sink 106_IV will be described with reference to FIGS. 51 to 53. Since it is substantially the same as the technical idea demonstrated, detailed description is abbreviate | omitted.

65 and 66, the semiconductor packages 200b_IV and 200c_IV cover at least a portion of the side surface of the heat sink 106_IV on the encapsulant 102_IV and cover the upper surface of the heat sink 106_IV to the outside. The heat dissipation molding part 210_IV surrounding the heat sink 106_IV may be further included to expose the heat sink 106_IV. The heat dissipation molding part 210_IV may firmly fix the heat sink 106_IV on the encapsulant 102_IV, and may concentrate heat generated in the semiconductor chip 101_IV to the center of the heat sink 106_IV, thereby forming a semiconductor. The heat dissipation effect of the packages 200b_IV and 200c_IV may be improved.

In one embodiment, the heat dissipation molding part 107_IV may include various materials such as a metal material, a ceramic material, a carbon material, and a polymer material. In one embodiment, the heat dissipation molding part 210_IV may be an epoxy molding compound.

In an embodiment, the outer surface of the heat dissipation molding part 210_IV may be self-aligned with the side surfaces of the semiconductor packages 200b_IV and 200c_IV. In addition, when the semiconductor packages 200b_IV and 200c_IV are viewed from the top to the bottom, the sum of the footprints of the heat dissipation molding parts 210_IV, the heat sinks 106_IV, and the protrusions 201_IV of the semiconductor packages 200b_IV and 200c_IV is equal to that of the semiconductor packages 200b_IV and 200c_IV. 200b_IV, 200c_IV) may be substantially the same.

Referring to FIG. 65, the heat dissipation molding part 210_IV of the semiconductor package 200b_IV may completely cover the side surface of the heat sink 106_IV. Accordingly, the side surface of the heat sink 106_IV may not be exposed to the outside. In addition, the heat dissipation molding part 210_IV completely covers the inner side surface of the protrusion 201_IV and the outer side surface 201a_IV may be exposed to the outside. The height of the heat dissipation molding part 210_IV may be substantially the same as the height of the heat sink 106_IV and the protrusion 201_IV. That is, the top surface of the heat dissipation molding part 210_IV may be self-aligned with the top surface of the heat sink 106_IV and the top surface of the protrusion 201_IV.

Referring to FIG. 66, the heat dissipation molding part 210_IV of the semiconductor package 200c_IV may cover only a portion of a side surface of the heat sink 106_IV. Accordingly, one portion of the side surface of the heat sink 106_IV may be exposed to the outside. In addition, the heat dissipation molding part 210_IV may cover only a portion of the inner side surface of the protrusion 201_IV and the outer side surface 201a_IV may be exposed to the outside. The height of the heat dissipation molding part 210_IV may be lower than the height of the heat sink 106_IV and the protrusion 201_IV. Accordingly, a step D3_IV may be formed between the top surface of the heat sink 106_IV and the top surface of the heat dissipation molding part 210_IV.

67 is a perspective view of a semiconductor package 300_IV according to an embodiment of the present disclosure. The semiconductor package 300_IV may include a semiconductor chip 101_IV, an encapsulant 102_IV, a redistribution layer 103_IV, an external connection terminal 104_IV, and an adhesive film 105_IV. The technical concepts of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, and the adhesive film 105_IV are substantially the same as those described with reference to FIGS. 51 to 53. Since it is the same, detailed description is omitted.

In an embodiment, the semiconductor package 300_IV may further include a heat sink 301_IV. As illustrated in FIG. 67, the heat sink 301_IV may include a first heat dissipation layer 302_IV and a second heat dissipation layer 303_IV on the first heat dissipation layer 302_IV. The footprint of the second heat dissipation layer 303_IV may be smaller than the footprint of the first heat dissipation layer 302_IV. Due to the difference in the footprint of the first heat dissipation layer 302_IV and the second heat dissipation layer 303_IV and the height of the second heat dissipation layer 303_IV, the heat sink 301_IV has an inverted T shape. can do.

In one embodiment, the materials of the first heat dissipation layer 302_IV and the second heat dissipation layer 303_IV may be substantially the same. More specifically, the first heat dissipation layer 302_IV and the second heat dissipation layer 303_IV may be combined and integrated with each other using the same material.

In an embodiment, the materials of the first heat dissipation layer 302_IV and the second heat dissipation layer 303_IV may be different. For example, the material of the first heat dissipation layer 302_IV may include a metal having a higher thermal conductivity than the material of the second heat dissipation layer 303_IV. However, the present invention is not limited thereto, and the material of the second heat dissipation layer 303_IV may include a metal having a higher thermal conductivity than the material of the first heat dissipation layer 302_IV.

In one embodiment, the first heat dissipation layer 302_IV and the second heat dissipation layer 303_IV may be substantially the same thickness. However, the present invention is not limited thereto, and the first heat dissipation layer 302_IV and the second heat dissipation layer 303_IV may have different thicknesses. The sum of the thicknesses of the first heat dissipation layer 302_IV and the second heat dissipation layer 303_IV may be about 280 micrometers to about 560 micrometers, and may be about 25 percent to about 40 percent of the total semiconductor package thickness.

Referring to FIG. 67, the footprint of the first heat dissipation layer 302_IV may be smaller than that of the adhesive film 105_IV, and the footprint of the second heat dissipation layer 303_IV may be smaller than that of the first heat dissipation layer 302_IV. It can be smaller than the footprint. Accordingly, the semiconductor package 300_IV may include a step D4_IV formed by a height difference between an upper surface of the first heat dissipation layer 302_IV and an upper surface of the adhesive film 105_IV. In addition, the semiconductor package 300_IV may include a step D5_IV formed by a height difference between an upper surface of the second heat dissipation layer 303_IV and an upper surface of the first heat dissipation layer 302_IV.

68 is a perspective view of a semiconductor package 300a_IV according to an embodiment of the present disclosure. The semiconductor package 300a_IV includes the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, the adhesive film 105_IV, the first heat dissipation layer 302_IV, and the second heat dissipation layer. 303_IV may be included. Technical description of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, the adhesive film 105_IV, the first heat dissipation layer 302_IV, and the second heat dissipation layer 303_IV Since the idea is substantially the same as the technical idea described with reference to FIGS. 51 to 53 and 67, a detailed description thereof will be omitted.

In an embodiment, the semiconductor package 300a_IV may further include a protrusion 304_IV extending from the side surface of the first heat dissipation layer 302_IV of the heat sink 301_IV to the side surface of the semiconductor package 300a_IV. The protrusion 304_IV may be one area of the remaining connection area S_IV after the connection area S_IV of the group of heat sinks (FIGS. 69 and 350_IV) to be described later is cut by the individualization process of the semiconductor package 300a_IV. have.

In one embodiment, the top surface of the protrusion 304_IV may be at the same height as the top surface of the first heat dissipation layer 302_IV. In addition, the outer surface 304a_IV of the protrusion 304_IV may be self-aligned with the side surface of the semiconductor package 300a_IV.

In an embodiment, the plurality of protrusions 304_IV may extend from one side of the first heat dissipation layer 302_IV to one side of the semiconductor package 300a_IV. For example, as illustrated in FIG. 68, two protrusions 304_IV may extend from one side of the first heat dissipation layer 302_IV to one side of the semiconductor package 300a_IV. However, the number of protrusions 304_IV extending from one side of the first heat dissipation layer 302_IV to one side of the semiconductor package 300a_IV may be various, without being limited thereto.

Since other technical concepts of the protrusion 304_IV of the semiconductor package 300a_IV disclosed in FIG. 68 are substantially the same as those of the protrusion 201_IV of the semiconductor package 200_IV described with reference to FIG. 57, a detailed description thereof will be omitted.

Referring to FIG. 68, the semiconductor package 300a_IV may include a step D4_IV formed by a height difference between an upper surface of the first heat dissipation layer 302_IV and an upper surface of the adhesive film 105_IV, and the second heat dissipation layer 303_IV. It may include a step (D5_IV) formed by the difference in the height of the upper surface of the upper surface and the first heat dissipation layer (302_IV).

The height of the step D4_IV formed by the height difference between the top surface of the first heat dissipation layer 302_IV and the top surface of the adhesive film 105_IV may be substantially the same as the height of the first heat dissipation layer 302_IV, and the second heat dissipation layer 303_IV. The height of the step D5_IV formed by the height difference between the top surface of the top surface and the top surface of the first heat dissipation layer 302_IV may be substantially the same as the height of the second heat dissipation layer 303_IV.

The height of the step D4_IV formed by the height difference between the top surface of the first heat dissipation layer 302_IV and the top surface of the adhesive film 105_IV is formed by the height difference between the top surface of the second heat dissipation layer 303_IV and the top surface of the first heat dissipation layer 302_IV. It may be smaller than the height of the step D5_IV. In addition, the height of the protrusion 304_IV may be substantially the same as the height of the step D4_IV formed by the height difference between the top surface of the first heat dissipation layer 302_IV and the top surface of the adhesive film 105_IV. When the height of the protrusion 304_IV is small, in the individualization process of the semiconductor package 300a_IV, a small external force required for cutting may be required, thereby increasing flexibility of the cutting process. However, the heights of the steps D4_IV and D5_IV are not limited to the above, but may have various height values. For example, the height of the step D4_IV formed by the height difference between the top surface of the first heat dissipation layer 302_IV and the top surface of the adhesive film 105_IV is greater than that of the top surface of the second heat dissipation layer 303_IV and the first heat dissipation layer 302_IV. It may be greater than or equal to the height value of the step D5_IV formed by the height difference of the upper surface.

In addition, the sum of the heights of the steps D4_IV and D5_IV may be about 25 percent to about 40 percent of the total thickness of the semiconductor package 300a_IV. Thus, when the total thickness of the semiconductor package 300a_IV is about 1.1 millimeters to about 1.4 millimeters, the sum of the heights of the steps D4_IV and D5_IV may be about 280 micrometers to about 560 micrometers.

FIG. 69 is a plan view of a group 350_IV of heat sinks to which a plurality of heat sinks 301_IV are connected, according to an embodiment of the present disclosure.

Referring to FIG. 69, the heat sinks 301_IV may be interconnected with the other heat sinks 301_IV by the connection region S_IV to form a group 350_IV of heat sinks. More specifically, the heat sink 301_IV is connected to the side surface of the first heat dissipation layer 302_IV of the other heat sinks 301_IV by the connection region S_IV in four directions of the side surfaces of the first heat dissipation layer 302_IV. The group of heat sinks 350_IV may be formed.

In an embodiment, the population of heat sinks 350_IV is formed on the top surface of the adhesive film 105_IV of the plurality of semiconductor packages 300a_IV before the plurality of semiconductor packages 300a_IV are cut into individual semiconductor packages 300a_IV. It can be fixed in place. The heat sinks 301_IV may form the population 350_IV of the heat sinks by the connection region S_IV, so that the populations of the heat sinks 350_IV are easily aligned and mounted on the upper surfaces of the semiconductor packages 300a_IV. can do. In addition, after the population of the heat sinks 350_IV is positioned on the adhesive film 105_IV, heat and pressure may be applied to the adhesive film 105_IV. The adhesive film 105_IV may stably fix the group 350_IV of heat sinks on the plurality of semiconductor packages 300a_IV.

In one embodiment, when the population of heat sinks 350_IV is stably mounted on the plurality of semiconductor packages 300a_IV, the plurality of semiconductor packages 300a_IV are cut into individual semiconductor packages 300a_IV through a cutting process. Can be cut. The cutting line L_IV may be formed on the plurality of connection regions S_IV. Since the cutting line L_IV may be formed on the connection region S_IV having the first length w_IV and the second length t_IV, the first length w_IV and the second length t_IV of the connection region S_IV The smaller the value), the easier the cutting process of cutting the plurality of semiconductor packages 300a_IV mounted with the group of heat sinks 350_IV into individual semiconductor packages 300a_IV.

In addition, since the population of heat sinks 350_IV is integrally handled, embodiments of the present disclosure may provide ease in the process of processing, transporting, and cutting the population of heat sinks 350_IV.

70 is a cross-sectional view in C_IV-C_IV of FIG. 69 of a plurality of semiconductor packages 300a_IV mounted with a group of heatsinks 350_IV, which is an embodiment of the present disclosure, and FIG. 71 is a heatsink that is an embodiment of the present disclosure. 69 is a cross-sectional view of D-IV-D_IV of FIG. 69 of the plurality of semiconductor packages 300a_IV mounted with the group 350_IV of the field.

Referring to FIG. 70, in a portion where the connection region S_IV is not formed (that is, a space between the connection regions S_IV), the semiconductor package 300a_IV may have an upper surface of the first heat dissipation layer 302_IV and an adhesive film ( It may include a step (D4_IV) formed by the height difference of the upper surface of 105_IV, and may include a step (D5_IV) formed by the height difference between the upper surface of the second heat dissipating layer (303_IV) and the top surface of the first heat dissipating layer (302_IV). .

Referring to FIG. 71, the portion where the connection region S_IV is formed may include only the step D5_IV formed by the height difference between the top surface of the second heat dissipation layer 303_IV and the top surface of the first heat dissipation layer 302_IV.

Referring to FIG. 70, in the cutting process of the semiconductor packages 300a_IV, the adhesive film 105_IV, the encapsulant 102_IV, and the redistribution layer 103_IV are sequentially cut at portions where the connection region S_IV is not formed. It may include a process to. In addition, referring to FIG. 71, the cutting process of the semiconductor packages 300a_IV may include a connection region S_IV, an adhesive film 105_IV, an encapsulant 102_IV, and a redistribution layer in a portion where the connection region S_IV is formed. 103_IV) may include a step of sequentially cutting. As described above, when the rigidity of the material of the connection region S_IV is weaker than that of the material of the heat sink 301_IV, the cutting process may be easy. In addition, since the material of the encapsulant 102_IV and the redistribution layer 103_IV may include an epoxy molding compound having a relatively weaker rigidity than the material of the connection region S_IV, in the cutting process of the semiconductor package 300a_IV, Various cutting blades are available. In addition, the cutting process may be facilitated by minimizing the first length w_IV and the second length t_IV of the connection region S_IV.

72 and 73 are perspective views of semiconductor packages 300b_IV and 300c_IV according to an embodiment of the present disclosure. The semiconductor packages 300b_IV and 300c_IV may include the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, the adhesive film 105_IV, the first heat dissipation layer 302_IV, and 2 may include a heat radiation layer (303_IV). Technical description of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, the adhesive film 105_IV, the first heat dissipation layer 302_IV, and the second heat dissipation layer 303_IV The idea is substantially the same as the technical idea described with reference to FIGS. 51 to 53 and 67, and thus, a detailed description thereof will be omitted.

In one embodiment, the semiconductor packages 300b_IV and 300c_IV cover at least a portion of the side surface of the heat sink 301_IV and heat sink 301_IV to expose at least a portion of the upper surface of the heat sink 301_IV to the outside. ) May further include a heat dissipation molding part 380_IV. The heat dissipation molding part 380_IV can firmly fix the heat sink 301_IV on the encapsulant 102_IV, and can concentrate heat generated in the semiconductor chip 101_IV to the center of the heat sink 301_IV, thereby providing a semiconductor. The heat dissipation effect of the packages 300b_IV and 300c_IV may be improved.

Referring to FIG. 72, the heat dissipation molding part 380_IV of the semiconductor package 300b_IV covers the side surface of the second heat dissipation layer 303_IV on the top surface of the first heat dissipation layer 302_IV. Can surround the side of the. In this case, the side surface of the first heat dissipation layer 302_IV may be exposed to the outside, but the top surface of the first heat dissipation layer 302_IV may not be exposed to the outside. In addition, the side surface of the second heat dissipation layer 303_IV may not be exposed to the outside, but the top surface of the second heat dissipation layer 303_IV may be exposed to the outside. The top surface of the second heat dissipation layer 303_IV and the top surface of the heat dissipation molding part 380_IV may be at the same height, and the sum of the footprints of the second heat dissipation layer 303_IV and the heat dissipation molding part 380_IV is the first heat dissipation layer. It may be substantially the same as the footprint of 302_IV. Accordingly, when the semiconductor package 300b_IV is viewed from above, the first heat dissipation layer 302_IV may not be observed.

Referring to FIG. 73, the heat dissipation molding part 380_IV of the semiconductor package 300c_IV surrounds the side surface of the first heat dissipation layer 302_IV to cover the side surface of the first heat dissipation layer 302_IV on the adhesive film 105_IV. Can be. In this case, the side and top surfaces of the second heat dissipation layer 303_IV may be exposed to the outside. In addition, a portion of the upper surface of the first heat dissipation layer 302_IV may be exposed to the outside, but the side surface of the first heat dissipation layer 302_IV may not be exposed to the outside.

74 is a perspective view of a semiconductor package 400_IV according to an embodiment of the present disclosure, and FIG. 75 is a cross-sectional view of a semiconductor package 400_IV according to an embodiment of the present disclosure.

74 and 75, the semiconductor package 400_IV may include a semiconductor chip 101_IV, an encapsulant 102_IV, a redistribution layer 103_IV, an external connection terminal 104_IV, and a heat sink 106_IV. Can be. The technical concepts of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, and the heat sink 106_IV are substantially the same as those described with reference to FIGS. 51 to 53. Since it is the same, detailed description is omitted.

In an embodiment, the semiconductor package 400_IV may further include an adhesive film 401_IV. The footprint of the adhesive film 401_IV may be larger than the footprint of the heat sink 106_IV, and the width of the first direction X of the adhesive film 401_IV is the first direction X of the heat sink 106_IV. It can be larger than the width.

In one embodiment, the adhesive film 401_IV may extend upwardly to the side of the heat sink 106_IV to cover at least a portion of the side surface of the heat sink 106_IV. As the adhesive film 401_IV extends upwardly to the side of the heat sink 106_IV, the heat sink 106_IV may be firmly coupled to the encapsulant 102_IV.

In one embodiment, the adhesive film 401_IV may include a conductive material and a non-conductive material. For example, the material of the adhesive film 401_IV may include at least one of silver, aluminum, silicon dioxide, aluminum nitride, and boron nitride.

76 and 77 are cross-sectional views of semiconductor packages 400a_IV and 400b_IV according to an embodiment of the present disclosure.

In an embodiment, the adhesive film 401_IV of the semiconductor packages 400a_IV and 400b_IV may cover at least a portion of a side surface of the heat sink 106_IV. For example, as illustrated in FIG. 76, the adhesive film 401_IV covers only a portion of the side surface of the heat sink 106_IV and the outside of the remaining portion except for the portion of the upper surface and the side surface of the heat sink 106_IV. May be exposed. In addition, as illustrated in FIG. 77, the adhesive film 401_IV may cover all of the side surfaces of the heat sink 106_IV and expose only the upper surface of the heat sink 106_IV to the outside.

Referring to FIG. 76, the side surface of the adhesive film 401_IV may be self-aligned with the side surface of the semiconductor package 400a_IV. In addition, when looking down the semiconductor package 400a_IV from the top, the sum of the footprints of the heat sink 106_IV and the adhesive film 401_IV may be substantially the same as the footprint of the semiconductor package 400a_IV.

Referring to FIG. 77, the footprint of the adhesive film 401_IV of the semiconductor package 400b_IV may be smaller than the footprint of the semiconductor package 400b_IV. More specifically, when looking at the semiconductor package 400b_IV from the top down, the sum of the footprints of the heat sink 106_IV and the adhesive film 401_IV may be smaller than the footprint of the semiconductor package 400a_IV.

78 is a view illustrating a heat sink 500a_IV according to an embodiment of the present disclosure, and FIG. 79 is a view illustrating a process of manufacturing the heat sink 500a_IV according to an embodiment of the present disclosure. 80 is a view illustrating a heat sink 500b_IV according to an embodiment of the present disclosure, and FIG. 81 is a view illustrating a manufacturing process of a heat sink 500b_IV according to an embodiment of the present disclosure. The heat sinks 500a_IV and 500b_IV of the present disclosure may be mounted on the adhesive film 105_IV of the semiconductor package 100_IV described with reference to FIG. 51.

In one embodiment, the heat sinks 500a_IV and 500b_IV may include a plurality of materials. For example, the heat sinks 500a_IV and 500b_IV may include a first metal 501_IV and a second metal 502_IV different from the first metal 501_IV. The second metal 502_IV may be a plating layer formed on the first metal 501_IV by a plating method. The second metal 502_IV is to prevent oxidation of the first metal 501_IV, and the second metal 502_IV may be a metal having a slower oxidation rate than the first metal 501_IV. Since the second metal 502_IV may be plated on the surface of the first metal 501_IV, the degradation of the heat dissipation effect by the oxide film generated by oxidizing the first metal 501_IV may be prevented.

In one embodiment, the first metal 501_IV may be copper and the second metal may be nickel. In addition, the first metal 501_IV may be aluminum, and the second metal may be nickel. However, the present disclosure is not limited thereto, and the first metal 501_IV and the second metal 502_IV may include various metal materials.

Referring to FIG. 78, the second metal 502_IV of the heat sink 500a_IV may cover the top and bottom surfaces of the first metal 501_IV and may be exposed to the outside without covering the side surfaces of the first metal 501_IV. Can be. Accordingly, when the heat sink 500a_IV is viewed from the side, the first metal 501_IV and the second metal 502_IV may be exposed to the outside and observed.

Referring to FIG. 79, after the first metal 501_IV is manufactured to a wafer level or panel level, the second metal 502_IV may form a plating layer on the first metal 501_IV by a plating method. have. After the second metal 502_IV is plated on the first metal 501_IV, individual heat sinks 500a_IV may be formed through a cutting process. Accordingly, the second metal 502_IV may not be plated on the side surface of the first metal 501_IV.

Referring to FIG. 80, the second metal 502_IV of the heat sink 500b_IV may cover all of the top, bottom, and side surfaces of the first metal 501_IV. Accordingly, the first metal 501_IV may not be exposed to the outside. When the heat sink 500b_IV is viewed from the side, only the second metal 502_IV may be exposed to the outside and observed.

Referring to FIG. 81, after the first metal 501_IV is individualized at the package level, the second metal 502_IV may form a plating layer on the first metal 501_IV by a plating method. Accordingly, the second metal 502_IV may be plated on all of the top, bottom, and side surfaces of the first metal 501_IV.

In one embodiment, when the second metal 502_IV is plated on the surface of the first metal 501_IV, the thickness of the first metal 501_IV is about 10 times to about 1000 times the thickness of the second metal 502_IV. Can be. As the second metal 502_IV is plated on the surface of the first metal 501_IV, the heat dissipation effect of the heat sinks 500a_IV and 500b_IV may be improved. In addition, the rigidity of the heat sinks 500a_IV and 500b_IV can be increased, thereby preventing damage to the heat sinks 500a_IV and 500b_IV from an external impact.

In one embodiment, the heat sinks 500a_IV and 500b_IV may comprise metal oxides or metal nitrides. For example, the heat sinks 500a_IV and 500b_IV may include aluminum oxide or aluminum nitride.

Without being limited to the foregoing, the heat sink of the present disclosure may include a silicon-based material. Silicon-based materials can have high thermal conductivity and at the same time be elastic. Accordingly, the heat sink can absorb external shocks and prevent damage to the semiconductor package due to the shocks.

Heat sinks of the present disclosure may be cut to the size of individual heat sinks and then individually seated on a semiconductor package. However, the present disclosure is not limited thereto, and the heat sinks of the present disclosure may be mounted on a semiconductor package manufactured at a wafer level or a panel level, manufactured in a size corresponding to a wafer level or a panel level, and then cut into individual heat sinks through an individualization process. Can be.

82 is a cross-sectional view of a semiconductor package 600_IV according to an embodiment of the present disclosure. The semiconductor package 600_IV may include a semiconductor chip 101_IV, an encapsulant 102_IV, a redistribution layer 103_IV, an external connection terminal 104_IV, an adhesive film 105_IV, and a heat sink 601_IV. The technical concepts of the semiconductor chip 101_IV, the encapsulant 102_IV, the redistribution layer 103_IV, the external connection terminal 104_IV, and the adhesive film 105_IV are substantially the same as those described with reference to FIGS. 51 to 53. Since the same, detailed description is omitted.

The heat sink 601_IV of the semiconductor package 600_IV may have a shape of an uneven structure. The dictionary meaning of the irregularities is concave and convex. The heat sink 601_IV may include a base 602_IV and a plurality of protrusions 603_IV on the base 602_IV. More specifically, the heat sink 601_IV may include a plurality of protrusions 603_IV protruding from an upper surface of the base 602_IV having a flat plate shape. The plurality of protrusions 603_IV may be repeatedly disposed at a predetermined distance apart. For this reason, the heat sink 601_IV can have the shape of the uneven structure in which the concave and convex are repeated.

In an embodiment, the bottom surface of the base portion 602_IV of the heat sink 601_IV may be fixed by the adhesive film 105_IV on the encapsulant 102_IV of the semiconductor package 600.

83 and 84 are cross-sectional views of heat sinks 601a_IV and 601b_IV according to an embodiment of the present disclosure.

83 and 84, the thickness f ₁ _ IV of the base 602_IV may occupy about 40% to about 60% of the total thickness f_IV of the heat sinks 601a_IV and 601b_IV. For example, the thickness f ₁ _ IV of the base portion 602_IV of the heat sink 601_IV may be half of the overall thickness f_IV of the heat sinks 601a_IV and 601b_IV. When the total thickness f_IV of the heat sinks 601a_IV and 601b_IV is about 400 micrometers, the thickness of the base 602_IV of the heat sinks 601a_IV and 601b_IV may be about 200 micrometers.

In an embodiment, the protrusions 603a_IV and 603b_IV of the heat sinks 601a_IV and 601b_IV may be formed to be spaced apart from the neighboring protrusions 603a_IV and 603b_IV by a predetermined distance g_IV. The separation distance g_IV may be about 100 micrometers to about 300 micrometers. More specifically, the separation distance g_IV may be about 200 micrometers.

In an embodiment, the width e_IV formed by the protrusions 603a_IV and 603b_IV of the heat sinks 601a_IV and 601b_IV may be about 100 micrometers to about 300 micrometers. More specifically, the width e_IV formed by the protrusions 603a_IV and 603b_IV may be about 200 micrometers.

In one embodiment, the thickness f ₂ _ IV formed by the protrusions 603a_IV and 603b_IV of the heat sinks 601a_IV and 601b_IV is about 40 percent to about 60 percent of the total thickness f_IV of the heat sinks 601a_IV and 601b_IV. Can occupy. In an embodiment, the thickness f ₂ _ IV of the protrusions 603a_IV and 603b_IV of the heat sinks 601a_IV and 601b_IV may be half of the total thickness f_IV of the heat sinks 601a_IV and 601b_IV. For example, when the total thickness f_IV of the heat sinks 601a_IV and 601b_IV is about 400 micrometers, the thickness f ₂ _IV of the protrusions 603a_IV and 603b_IV of the heat sinks 601a_IV and 601b_IV is about 200 micrometers.

In one embodiment, the heat sink (601a_IV, 601b_IV) Total thickness (f_IV) has a base (602_IV) thickness (f ₁ _IV) and projection sum (f_IV = f of the thickness (f ₂ _IV) of (603a_IV, 603b_IV) of ₁ _IV + f ₂ _IV). In one embodiment, when the total thickness f_IV of the heat sinks 601a_IV and 601b_IV is about 400 micrometers, the thickness f ₁ _IV of the base 602_IV is the total thickness f_IV of the heat sinks 601a_IV and 601b_IV. About 160 micrometers, which is about 40 percent, and wherein the thickness f ₂ _ IV of the projections 603a_IV, 603b_IV is about 240, about 60 percent of the thickness f_IV of the heat sinks 601a_IV, 601b_IV. Micrometers. Further, when the thickness f ₁ _ IV of the base portion 602_IV is about 240 micrometers which is about 60 percent of the thickness f_IV of the heat sinks 601a_IV and 601b_IV, the thickness f of the protrusions 603a_IV and 603b_IV is determined. ₂ _IV may be about 160 micrometers, which is about 40 percent of the thickness f_IV of the heat sinks 601a_IV and 601b_IV. In addition, the thickness f ₁ _IV of the base 602_IV of the heat sinks 601a_IV and 601b_IV and the thickness f ₂ _IV of the protrusions 603a_IV and 603b_IV may be substantially the same, and in some embodiments, about 200, respectively. Micrometers.

Referring to FIG. 83, the protrusion 603a_IV of the heat sink 601a_IV may include a flat plane thereon. In addition, referring to FIG. 84, the protrusion 603b_IV of the heat sink 601b_IV may include a curved surface that is convex from the top. However, the present invention is not limited thereto, and the protrusions of the heat sink may have various shapes.

Referring to FIG. 83, the heat sink 601a_IV may include the plurality of protrusions 603a_IV through a process of cutting a portion of a rectangular parallelepiped heat sink having a predetermined thickness f_IV using a cutting device. Can be. The cutting blade of the cutting device may have a separation width g_IV between the plurality of protrusions 603a_IV as a cutting width, and may have a thickness f ₂ _IV of the plurality of protrusions 603a_IV as a cutting depth. have. The cutting device may simultaneously cut a portion of the heat sink while moving along the cutting lane, such that the heat sink 601a_IV may include the plurality of protrusions 603a_IV described above.

Referring to FIG. 84, the heat sink 601b_IV forms the protrusions 603a_IV through the above-described cutting device, and then the upper surface of the heat sink 601b_IV is convexly curved through the additional cutting process of smoothly cutting the upper portions of the protrusions 603a_IV. It may include protrusions 603b_IV having a shape of.

In one embodiment, the heat sinks 601a_IV and 601b_IV shown in FIGS. 83 and 84 may be formed through an injection molding process rather than the above-described cutting process.

More specifically, the material to be formed as the heat sinks 601a_IV and 601b_IV may be injected into the injection molding heating chamber. The material of the heat sinks 601a_IV and 601b_IV injected into the heating chamber may be melted by the high temperature of the heating chamber. The molten material may be injected into an injection molding machine including an injection space in the shape of the heat sinks 601a_IV and 601b_IV of FIGS. 83 and 84. The injected molten material may fill the injection space in the shape of the heat sinks 601a_IV and 601b_IV. Thereafter, the injection molding machine may cool the molten material in the injection space to finally form the heat sinks 601a_IV and 601b_IV shown in FIGS. 83 and 84. When the injection molding process is used, the shape of the concave-convex structure of the heat sinks 601a_IV and 601b_IV is not limited to those shown in FIGS. 83 and 84, and may have various shapes according to the shape of the injection space of the injection molding machine. Can be.

The heat sinks 601a_IV and 601b_IV of FIGS. 83 and 84 are not limited to the above-described cutting process and injection molding process, and may form the uneven structure through various processes. In an embodiment, the uneven structures of the heat sinks 601a_IV and 601b_IV may be formed through a chemical reaction. In addition, in one embodiment, the heat sinks 601a_IV and 601b_IV may form an uneven structure through a process of physically bonding a plurality of protrusions 603a_IV and 603b_IV separately formed on the base 602_IV. In this case, the materials of the protrusions 603a_IV and 603b_IV and the base 602_IV of the heat sinks 601a_IV and 601b_IV may be different.

In an embodiment, the heat sinks 601a_IV and 601b_IV may have a concave-convex structure, so that heat dissipation performance of the semiconductor package 600_IV may be improved. More specifically, by forming the concave-convex structure, the heat sinks 601a_IV and 601b_IV may have a large surface area that contacts the outside air. Therefore, the semiconductor package 600_IV equipped with the heat sinks 601a_IV and 601b_IV may more quickly discharge heat emitted from the semiconductor chip 101_IV in the semiconductor package 600_IV to the outside.

85 to 87 are plan views of heat sinks 700a_IV, 700b_IV, and 700c_IV having a concave-convex structure including a marking area in which information of a semiconductor package is displayed, according to an exemplary embodiment.

Referring to FIG. 85, the heat sink 700a_IV may include a base 701_IV and a protrusion 702_IV, as described above. In addition, the heat sink 700a_IV may include a marking area 704_IV including marking of information on the semiconductor package on the base 701_IV, and a protrusion area including a plurality of protrusions 702_IV protruding from the base 701_IV. 703_IV).

In an embodiment, the protrusion 702_IV may not be formed in the marking region 704_IV. In other words, the heat sink 700a_IV may not include a concave-convex structure at one portion, and the marking region 704_IV may be formed on the surface of the base portion 701_IV in which the protrusion 702_IV is not formed. Therefore, the marking area 704_IV may be lower than the upper surface of the protrusion 702_IV.

The heat sink 700a_IV shown in FIG. 85 may include a marking region 704_IV in the plane of the base portion 701_IV in which the protrusions 702_IV are not formed at the upper left side, and the marking region 704_IV includes a semiconductor package. Information of the semiconductor chip mounted therein may be marked. However, the marking area 704_IV is not limited to the position shown in FIG. 85 and may be formed at more various positions of the heat sink 700a_IV.

In an embodiment, the marking area 704_IV of the semiconductor package may be marked with information about the semiconductor chip, such as the type, number, performance, name and / or logo of the manufacturer, manufacturing date, serial number, and the like of the semiconductor chip.

In one embodiment, an ink marking technique or a laser marking technique may be used for marking semiconductor package information.

More specifically, as a technique of ink marking, the information of the semiconductor chip may be marked by using a pad printing technique. The pad printing technique may mark semiconductor information by pushing an ink-filled palette onto a pad of silicon rubber having an embossed or intaglio pattern formed thereon so that the ink in the palette contacts the surface of the marking region 704_IV. The pad printing technique can mark the information of the semiconductor package at low cost, and since the pad of the silicone rubber is elastic, the semiconductor information can be cleanly marked even on the surface of the uneven heat sink.

In addition, the information of the semiconductor chip may be marked by a technique of laser marking. The laser marking technique focuses laser light emitted from the laser device on the marking area 704_IV of the heat sink 700a_IV by digging a portion of the marking area 704_IV to form letters or numbers. Inscribed can represent the information of the semiconductor chip. In addition, the laser device may adjust the intensity of the laser light according to the intensity of the power supplied to the laser device, thereby adjusting the thickness of letters and numbers formed in the marking area 704_IV of the heat sink 700a_IV. Can be.

Laser devices used for marking semiconductor chip information in the marking area 704_IV of the heat sink 700a_IV of the present disclosure are not limited to the above-described CO ₂ laser device, YAG laser device, and diode laser device. Various laser devices may further be included.

Referring to FIG. 86, the heat sink 700b_IV may include a base 701_IV and protrusions 702_IV. In addition, the heat sink 700b_IV may include the above-described protrusion region 703_IV and the marking region 705_IV formed to protrude from the base portion 701_IV.

In one embodiment, the marking region 705_IV may protrude from the top surface of the base portion 701_IV of the heat sink 700b_IV. More specifically, the marking region 705_IV may protrude from the top surface of the base portion 701_IV, and the top surface of the protruding marking region 705_IV may have a planar shape. The width of the upper surface of the marking area 705_IV may be larger than the width of the upper surface of the one protrusion 702_IV and may be smaller than the footprint of the heat sink 700b_IV. In one embodiment, the marking area 705_IV of the heat sink 700b_IV may occupy about 10 percent to about 80 percent of the footprint of the heat sink 700b_IV.

In one embodiment, the height formed by the marking area 705_IV protruding from the base 701_IV may be substantially the same as the height of the protrusion 702_IV. Accordingly, the top surface of the marking region 705_IV may be coplanar with the top surface of the protrusions 702_IV of the protrusion region 703_IV. The height at which the marking area 705_IV protrudes from the base 701_IV and the height at which the protrusions 702_IV protrude from the base 701_IV may be between about 40 percent and about 60 percent of the total thickness of the heat sink 700b_IV.

In an exemplary embodiment, the information of the semiconductor chip may be represented on the upper surface of the marking region 705_IV by the ink marking technique or the laser marking technique.

In FIG. 86, the marking region 705_IV is illustrated as being formed on the upper left side of the heat sink 700b_IV. However, the marking region 705_IV is not limited to the above position and may be formed at more various positions of the heat sink 700b_IV. .

The heat sink 700b_IV of FIG. 86 may have a large cross-sectional area of the heat sink 700b_IV in contact with the outside air due to the shape of the marking area 705_IV protruding from the base 701_IV, and thus may have excellent heat dissipation effect. .

As shown in FIG. 87, the heat sink 700c_IV may include first protrusions 702a_IV protruding on the base 701_IV in the protrusion area 703_IV and the base 602_IV in the marking area 706_IV. ) May include second protrusions 702b_IV. In other words, a region including the protrusion 702b_IV in which the information of the semiconductor package is marked among the plurality of protrusions may be the marking region 706_IV, and an area including the protrusion 702a_IV in which the information of the semiconductor package is not marked. May be the protruding region 703_IV.

In one embodiment, the marking region 706_IV may include consecutive letters and numbers representing information of the semiconductor package on the top surface of the base portion 701_IV and the second protrusions 702b_IV. More specifically, the information of the semiconductor chip may be expressed on the upper surface of the base portion 701_IV and the upper surface of the second protrusion 702b_IV disposed under the marking region 706_IV. The information of the semiconductor chip may be marked by marking part of the base 701_IV and part of the second protrusion 702b_IV by the laser device, and also on part of the base 701_IV and part of the second protrusion 702b_IV. Ink can be painted and marked.

In an embodiment, the thicknesses of the first protrusions 702a_IV and the second protrusions 702b_IV formed in the heat sink 700c_IV may be different from each other. More specifically, the thickness formed by the second protrusions 702b_IV may be smaller in order to include consecutive letters and numbers on the upper surface and the base 701_IV of the second protrusions 702b_IV in the marking area 702b_IV. . The smaller the thickness of the second protrusions 702b_IV, the smaller the change of the height of the point where the laser light is collected in the case of laser marking, so that the letters and numbers can be inscribed. In the case of ink marking, the silicon This is because the change in the length that the pad of rubber has to be stretched by elasticity can be small.

Therefore, the height formed by the second protrusions 702b_IV in the marking area 706_IV of the heat sink 700c_IV of the present disclosure may be substantially smaller than the height formed by the second protrusions 702a_IV of the protrusion area 703_IV. have. In an embodiment, the height formed by the second protrusions 702b_IV may be between about 1/4 and about 1/2 of the height formed by the first protrusions 702a_IV. In an embodiment of the present disclosure, when the total thickness of the heat sink 700c_IV is about 400 micrometers, the thickness of the base 701_IV is about 200 micrometers, and the height of the first protrusions 702a_IV is about 200 micrometers, The height of the second protrusions 702b_IV may be about 2 times to about 4 times smaller than the height of the first protrusions 702a_IV. Accordingly, the height of the second protrusions 702b_IV may be about 50 micrometers to about 100 micrometers.

In one embodiment, due to the low height of the second protrusions 702b_IV formed in the marking area 706_IV of the heat sink 700c_IV, the heat sink 700c_IV is the base 701_IV and the second of the marking area 706_IV. Continuous letters and numbers may be formed on the upper surfaces of the protrusions 702b_IV to represent information of the semiconductor package. For example, in the case of laser marking, the change in the height of the point where the laser light is collected in the marking area 706_IV may be about 50 micrometers to about 100 micrometers. Accordingly, letters and numbers may be continuously marked in an ordered shape in the marking area 706_IV without controlling the height of the light converging point of the laser light. In addition, even when controlling the height of the light collecting point of the laser light, only about 50 micrometers to about 100 micrometers of position control of the laser device may be necessary, so that energy consumption may be low when driving the laser device, and the laser device is driven. The control time of can be reduced.

In the case of ink marking, since the change in length that the pad of the silicone rubber should be stretched by elasticity may be small, from about 50 micrometers to about 100 micrometers, the upper surface of the second protrusions 702b_IV of the marking region 706_IV and Letters and numbers representing semiconductor information may be marked in a more ordered shape at the base 701_IV.

88 to 92 illustrate a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

Referring to FIG. 88, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a semiconductor chip 101_IV to an upper surface of a glass substrate 140_IV. The semiconductor chip 101_IV may be physically attached to an upper surface of the glass substrate 140_IV.

Referring to FIG. 89, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include forming an encapsulant 102_IV surrounding a semiconductor chip 101_IV. The forming of the encapsulant 102_IV may include, for example, closely contacting a molding control film MCF to an upper surface of the semiconductor chip 101_IV, and then forming the molding control film MCF and the glass substrate 140_IV. It may include the step of filling the encapsulant (102_IV) therebetween. The encapsulant 102_IV may cover both the side and top surfaces of the semiconductor chip 101_IV, and may cover only the side surfaces of the semiconductor chip 101_IV and expose the top surface to the outside.

Referring to FIG. 90, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a heat sink 106_IV. The heat sink 106_IV may be attached to an upper surface of the semiconductor chip 101_IV or an upper surface of the encapsulant 102_IV. Attaching the heat sink 106_IV to the top surface of the semiconductor chip 101_IV may include a thermocompression bonding method. The thermal crimping method may be a method of applying heat and pressure to the adhesive film 105_IV under the heat sink 106_IV using a compactor. The adhesive film 105_IV may stably attach the heat sink 106_IV to the top surface of the semiconductor chip 101_IV and the encapsulant 102_IV through a thermocompression bonding method.

Referring to FIG. 91, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include inverting a semiconductor package by separating the glass substrate 140_IV.

Referring to FIG. 92, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include forming a redistribution layer 103_IV. The redistribution layer 103_IV may include an insulation pattern 141_IV and a wiring pattern 142_IV. In an exemplary embodiment, the insulating pattern 141_IV may include a non-photosensitive material, and after the insulating pattern 141_IV is formed on the bottom surface of the semiconductor chip 101_IV, the insulating pattern 141_IV is formed of the semiconductor chip 101_IV. It may be partially removed to expose the chip pad 113_IV. After the insulating pattern 141_IV is formed, the wiring pattern 142_IV may be connected to the chip pad 113_IV exposed by the opening of the insulating pattern 141_IV. The wiring pattern 142_IV may be formed by plating, electroless plating, electroplating, or a combination thereof, and may be formed on the insulating pattern 141_IV through a plating process. When the wiring pattern 142_IV is formed, the wiring pattern 142_IV may be formed once again on the wiring pattern 142_IV. In this case, a part of the wiring pattern 142_IV may be partially exposed to be connected to the external connection terminal.

Referring to FIG. 92, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching an external connection terminal 104_IV. The external connection terminal 104_IV may be a solder ball. The external connection terminal 104_IV may be attached to the wiring pattern 142_IV exposed through the soldering process.

In an embodiment, the method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include a cutting process for performing an individualization process. The cutting process may separate the plurality of semiconductor packages into individual semiconductor packages. An embodiment of the cutting device of the cutting process may include a cutting blade, a laser device and the like.

Referring to FIG. 93, the electronic system 1500_IV may include at least one of semiconductor packages of various embodiments of the inventive concept. The electronic system 1500_IV may be included in a mobile device or a computer. For example, the electronic system 1500_IV may include a memory system 1501_IV, a microprocessor 1502_IV, a RAM 1503_IV, and a user interface 1504_IV that performs data communication.

94 is a cross-sectional view of a semiconductor package 100_V according to an embodiment of the present disclosure. The semiconductor package 100_V may be a wafer level package (WLP) or a panel level package (PLP).

Referring to FIG. 94, the semiconductor package 100_V includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, and an adhesive film 106_V. , And a heat sink 107_V. As described above, the semiconductor package 100_V may be a semiconductor package having a wafer level package (WLP) structure, and more specifically, a semiconductor package having a fan-out wafer level package structure. Can be. The overall thickness of the semiconductor package 100_V may be about 0.8 millimeters to about 1.8 millimeters. More specifically, in an embodiment of the present disclosure, the overall thickness of the semiconductor package 100_V may be about 1.1 millimeters to about 1.4 millimeters. However, the semiconductor package 100_V is not limited to the above-described thickness, but may have various thicknesses.

In an embodiment, the semiconductor chip 101_V may include a plurality of individual devices of various kinds. For example, the plurality of individual devices may be a variety of microelectronic devices, for example a metal-oxide-semiconductor field effect transistor (MOSFET), such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system LSI (large). image sensors, such as scale integration (CIS), CMOS imaging sensors (CIS), micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.

In an embodiment, the semiconductor chip 101_V may be a memory semiconductor chip. The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a phase-change random access memory (PRAM), or a magneto-resistive random access memory (MRAM). ), Or a nonvolatile memory semiconductor chip such as ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM).

Also, in one embodiment, the semiconductor chip 101_V may be a logic chip. For example, the semiconductor chip 101_V may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

Referring to FIG. 94, the semiconductor package 100_V is illustrated as including one semiconductor chip 101_V, but the semiconductor package 100_V may include two or more semiconductor chips 101_V. Two or more semiconductor chips 101_V included in the semiconductor package 100_V may be the same kind of semiconductor chip or different types of semiconductor chips. In an embodiment, the semiconductor package 100_V may be a system in package (SIP) in which different types of semiconductor chips are electrically connected to each other and operate as one system.

In example embodiments, the semiconductor chip 101_V may include a lower surface 111_V and an upper surface 112_V opposite to the lower surface 111_V. The semiconductor chip 101_V may include a chip pad 113_V on a lower surface 111_V. The chip pad 113_V may be electrically connected to a plurality of individual elements of various kinds formed in the semiconductor chip 101_V. The chip pad 113_V may have a thickness between about 0.5 micrometers and about 1.5 micrometers. In addition, although not illustrated in FIG. 94, the semiconductor chip 101_V may include a passivation layer covering the lower surface 111_V.

Referring to FIG. 94, the semiconductor package 100_V may include a metal frame 102_V. More specifically, the semiconductor package 100_V may include a metal frame 102_V on the redistribution layer 103_V.

In one embodiment, the metal frame 102_V may include various metal-based materials. For example, the metal frame 102_V includes aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and a thermal conductivity of about 380 W / m · K. Metal-based materials such as copper (Cu) having a degree, nickel (Ni) having a thermal conductivity of about 90 W / m · K, and silver (Ag) having a thermal conductivity of about 410 W / m · K.

In one embodiment, the metal frame 102_V may include a cavity 114_V formed by the inner wall 102b_V of the metal frame 102_V. The semiconductor chip 101_V may be located in the cavity 114_V of the metal frame 102_V, and the semiconductor chip 101_V may be surrounded by the metal frame 102_V. In order to prevent an electrical short between the metal frame 102_V and the semiconductor chip 101_V, the inner wall 102b_V of the metal frame 102_V and the semiconductor chip 101_V may be spaced apart from each other by a predetermined distance d_V.

In an embodiment, an encapsulant 104_V to be described later may be provided in a space formed by separating the inner wall 102b_V and the semiconductor chip 101_V of the metal frame 102_V. The encapsulant 104_V may be configured to prevent electrical short circuits of the semiconductor chip 101_V and the metal frame 102_V, and at the same time, the semiconductor chip 101_V and the metal frame 102_V may be disposed on the upper surface of the redistribution layer 103_V. It may be configured to be fixed.

In an embodiment, the outer wall 102a_V of the metal frame 102_V may be coplanar with the side surface of the semiconductor package 100_V. In other words, the outer wall 102a_V of the metal frame 102_V may be self-aligned with the side surface of the semiconductor package 100_V. Accordingly, when the semiconductor package 100_V is viewed from the side, the outer wall 102a_V of the metal frame 102_V may be exposed to the outside.

As illustrated in FIG. 94, the thickness of the metal frame 102_V may be substantially the same as the thickness of the semiconductor chip 101_V. However, the present invention is not limited thereto, and the metal frame 102_V may be smaller or larger than the height of the semiconductor chip 101_V. The shape of the metal frame 102_V is explained in full detail later.

In an embodiment, the separation distance d_V between the semiconductor chip 101_V and the inner wall 102b_V of the metal frame 102_V may be about 50 micrometers to about 150 micrometers. Accordingly, heat generated in the semiconductor chip 101_V may be transferred to the metal frame 102_V and quickly discharged to the outside.

In an embodiment, the semiconductor package 100_V may include an encapsulant 104_V. The encapsulant 104_V may be provided on the redistribution layer 103_V to fix the semiconductor chip 101_V and the metal frame 102_V on the redistribution layer 103_V. In addition, the encapsulant 104_V may surround and protect the semiconductor chip 101_V. As described above, the encapsulant 104_V is formed by spaced apart from the inner wall 102b_V of the metal frame 102_V and the semiconductor chip 101_V to prevent electrical short between the semiconductor chip 101_V and the metal frame 102_V. It may be provided in the space.

In an embodiment, the encapsulant 104_V may include, for example, a silicone based material, a thermosetting material, a thermoplastic material, a UV treated material, and the like, and for example, the encapsulant 104_V may be formed of a resin ( Polymers such as Resin), and may include, for example, an epoxy molding compound (EMC).

In an embodiment, the encapsulant 104_V may cover the side surface (not shown) and the upper surface 112_V of the semiconductor chip 101_V, the inner wall 102b_V and the upper surface of the metal frame 102_V. At this time, the adhesive film 106_V to be described later may contact the upper surface of the encapsulant 104_V. Referring to FIG. 94, the thicknesses of the semiconductor chip 101_V and the metal frame 102_V may be substantially the same, and the upper surface of the semiconductor chip 101_V and the upper surface of the metal frame 102_V may be at the same height. In this case, the thickness of the encapsulant 104_V positioned on the top surface of the semiconductor chip 101_V and the top surface of the metal frame 102_V may be about 1 micrometer to about 10 micrometers.

In an embodiment, the semiconductor package 100_V may include an adhesive film 106_V. The adhesive film 106_V may be on the encapsulant 104_V. The adhesive film 106_V may contact at least one of the top surface 112_V of the semiconductor chip 101_V and the top surface of the encapsulant 104_V. For example, as illustrated in FIG. 94, the adhesive film 106_V may not contact the upper surface of the semiconductor chip 101_V but may contact the upper surface of the encapsulant 104_V.

In one embodiment, the adhesive film 106_V may include an epoxy resin having excellent adhesion to the encapsulant 104_V and the semiconductor chip 101_V. In addition, the adhesive film 106_V may include a filler having excellent thermal conductivity, for example, silver, aluminum, silicon dioxide, aluminum nitride, boron nitride, or the like, and may have aluminum oxide having thermal conductivity to maintain rigidity. It may also include. The adhesive film 106_V may have adhesive properties by itself, and may also be provided by being bonded with a separate thermal conductive adhesive tape. The adhesive tape may be a double-sided adhesive tape.

In an embodiment, the adhesive film 106_V may fix the heat sink 107_V on the encapsulant 104_V of the semiconductor package 100_V. The thickness of the adhesive film 106_V formed on the semiconductor package 100_V may be about 5 micrometers to about 20 micrometers, and more specifically, about 10 micrometers to about 14 micrometers.

In an embodiment, the semiconductor package 100_V may include the redistribution layer 103_V. The redistribution layer 103_V may be formed on the bottom surface 111_V of the semiconductor chip 101_V and may be electrically connected to the chip pad 113_V and the external connection terminal 105_V of the semiconductor chip 101_V. The semiconductor package 100_V may form the external connection terminal 105_V in a region outside the footprint of the bottom surface 111_V of the semiconductor chip 101_V through the redistribution layer 103_V. That is, the semiconductor package 100_V may efficiently arrange the external connection terminal 105_V through the redistribution layer 103_V.

In an embodiment, the redistribution layer 103_V may include a wiring pattern 103a_V and an insulation pattern 103b_V. The wiring pattern 103a_V may be electrically connected to the chip pad 113_V formed on the bottom surface 111_V of the semiconductor chip 101_V. The wiring pattern 103a_V may provide an electrical connection path for electrically connecting the chip pad 113_V to an external device. The insulating pattern 103b_V may protect the wiring pattern 103a_V electrically connected to the chip pad 113_V from external shock and prevent a short circuit. The insulating pattern 103b_V may include, for example, a photosensitive material such as polyimide or epoxy. However, the present invention is not limited thereto, and the insulating pattern 103b_V may include a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

In an embodiment, the semiconductor package 100_V may include an external connection terminal 105_V. The external connection terminal 105_V may be positioned on the bottom surface of the redistribution layer 103_V and may be electrically connected to the wiring pattern 103a_V of the redistribution layer 103_V. The semiconductor package 100_V may be electrically connected to an external device such as a system board or a main board by the external connection terminal 105_V. The external connection terminal 105_V may include solder balls, as shown in FIG. 94. The solder ball may include at least one of tin, silver, copper, and aluminum. In addition, the solder ball may have a ball shape shown in FIG. 94, but is not limited thereto. The solder ball may have various shapes such as a cylinder, a polygonal column, and a polyhedron.

Referring to FIG. 94, the semiconductor package 100_V may include a heat sink 107_V. The heat sink 107_V may be provided on the adhesive film 106_V and mounted on the semiconductor package 100_V. The heat sink 107_V may effectively discharge heat generated from the semiconductor chip 101_V in the semiconductor package 100_V to the outside.

In an embodiment, the width of the first direction X of the heat sink 107_V may be smaller than the width of the first direction X of the adhesive film 106_V. In addition, when looking down the semiconductor package 100_V from the top (ie, from the + Z direction to the -Z direction), the footprint of the heat sink 107_V may be smaller than the footprint of the adhesive film 106_V.

In an embodiment, the heat sink 107_V mounted on the semiconductor package 100_V may include a metal material, a ceramic material, a carbon material, and a polymer material having various thermal conductivity.

More specifically, the heat sink 107_V includes aluminum (Al) having a thermal conductivity of about 200 W / m · K, magnesium (Mg) having a thermal conductivity of about 150 W / m · K, and a thermal conductivity of about 380 W / m · K. Metal-based materials such as copper (Cu), nickel (Ni) having a thermal conductivity of about 90 W / m · K, and silver (Ag) having a thermal conductivity of about 410 W / m · K.

In one embodiment, the heat sink 107_V is boron nitride (BN) with a thermal conductivity of about 1800 W / mK, aluminum nitride (AlN) with a thermal conductivity of about 320 W / mK, about 30 W / m Aluminum oxide (Al ₂ O ₃ ) with a K thermal conductivity, silicon carbide (SiC) with a thermal conductivity of about 480 W / m · K, and beryllium oxide (BeO) with a thermal conductivity of about 270 W / m · K It may include a ceramic-based material.

In one embodiment, the heat sink 107_V is a diamond having a thermal conductivity of about 2500 W / mK, a carbon fiber having a thermal conductivity of about 100 W / mK, from about 5 W / mK to about 1950 W / m Carbon-based materials such as graphite having a thermal conductivity of K, carbon nanotubes having a thermal conductivity of about 1.5 W / m · K to about 3500 W / m · K, and graphene having a thermal conductivity of about 5000 W / m · K. It may include.

In one embodiment, the heat sink 107_V may comprise a polymeric material such as polyethylene having an ultra high molecular weight having a thermal conductivity of about 45 W / m · K to about 100 W / m · K.

However, the heat sink 107_V is not limited to the above-described metal-based material, cerium-based material, carbon-based material, and polymer-based material, and may include a combination of the above materials or other materials not shown.

In an embodiment, the heat sink 107_V of the semiconductor package 100_V may be formed to various thicknesses v_V. In one embodiment of the present disclosure, the thickness v_V of the heat sink 107_V may account for about 25 percent to about 40 percent of the thickness of the semiconductor package 100_V. In one embodiment, the thickness of the semiconductor package 100_V may be between about 1.1 millimeters and about 1.4 millimeters, wherein the thickness v_V of the heat sink 107_V may be between about 280 micrometers and about 560 micrometers. .

In an embodiment, the semiconductor package 100_V may efficiently release heat generated from the semiconductor chip 101_V in the semiconductor package 100_V by the metal frame 102_V and the heat sink 107_V.

More specifically, heat generated in the semiconductor chip 101_V may be emitted to the upper surface 112_V and the side surface (not shown) of the semiconductor chip 101_V. Heat emitted to the top surface of the semiconductor chip 101_V may be emitted to the outside through the encapsulant 104_V, the adhesive film 106_V, and the heat sink 107_V sequentially from the top surface 112_V of the semiconductor chip 101_V. . In addition, heat emitted to the side surface (not shown) of the semiconductor chip 101_V may be emitted to the outside through the encapsulant 104_V and the metal frame 102_V sequentially from the side surface of the semiconductor chip 101_V.

In one embodiment, the semiconductor package 100_V of the present disclosure is generated in the semiconductor chip 101_V since the heat sink 107_V and the outer wall 102a_V of the metal frame 102_V having relatively high thermal conductivity are exposed to the outside. Heat can be released to the outside more efficiently.

95 is a cross-sectional view of a semiconductor package 100a_V according to an embodiment of the present disclosure. The semiconductor package 100a_V includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 107_V. It may include. The technical concept of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V is illustrated in FIG. Since it is substantially the same as the technical idea described with reference to 94, detailed description thereof will be omitted.

Referring to FIG. 95, the encapsulant 104_V of the semiconductor package 100a_V may cover the side surface of the semiconductor chip 101_V and the inner wall 102b_V of the metal frame 102_V, but the upper surface ( 112_V) and the upper surface of the metal frame 102_V may not be covered. That is, the upper surface of the semiconductor chip 101_V may be exposed by the encapsulant 104_V.

In an embodiment, the top surface of the semiconductor chip 101_V and the top surface of the encapsulant 104_V may contact the adhesive film 106_V. Accordingly, the thickness of the semiconductor package 100_V may be reduced, and heat generated from the semiconductor chip 101_V may be disposed on the upper surface 112_V of the semiconductor chip 101_V without passing through the encapsulant 104_V. Pass through 106_V and the heat sink 107_V on the adhesive film 106_V may be emitted to the outside. Heat generated in the semiconductor chip 101_V may not pass through the encapsulant 104_V having a relatively lower thermal conductivity than the adhesive film 106_V and the heat sink 107_V. Accordingly, the heat transfer resistance of the heat may be reduced, and accordingly, heat dissipation performance of the semiconductor package 100b_V may be improved.

FIG. 96 is a plan view of the semiconductor package 100_V at the straight line a_V of FIG. 94. As described above, the metal frame 102_V of the semiconductor package 100_V may include a cavity 114_V formed by the inner wall 102b_V. The semiconductor chip 101_V may be disposed in the cavity 114_V of the metal frame 102_V. In order to prevent an electrical short circuit with the metal frame 102_V of the semiconductor chip 101_V, the semiconductor chip 101_V may be disposed to be spaced apart from the inner wall 102b_V of the metal frame 102_V by a predetermined distance d_V. An encapsulant 104_V may be formed in a space formed by separating the inner wall 102b_V of the metal frame 102_V from the semiconductor chip 101_V. The encapsulant 104_V may be configured to prevent an electrical short between the metal frame 102_V and the semiconductor chip 101_V, and fix the metal frame 102_V and the semiconductor chip 101_V on the redistribution layer 103_V. It can be configured to.

In one embodiment, as shown in FIG. 96, the metal frame 102_V may have a rectangular parallelepiped shape including a cavity 114_V therein. However, the present invention is not limited to the above-described shape, and the metal frame 102_V may have various shapes. For example, the metal frame 102_V may be in the shape of a cylinder or polygonal column including a cavity 114_V therein.

In an embodiment, the shorter the distance d_V between the semiconductor chip 101_V and the inner wall 102b_V of the metal frame 102_V, the better the heat dissipation effect of the semiconductor package 100_V. In other words, as the separation distance d_V is shorter, the volume of the space occupied by the encapsulant 104_V having a lower thermal conductivity than the metal frame 102_V may decrease. Accordingly, the heat transfer resistance of the heat generated in the semiconductor chip 101_V is reduced, so that the heat dissipation effect of the semiconductor package 100_V can be improved.

In the related art, a space between the semiconductor chip 101_V and the inner wall 102b_V of the metal frame 102_V may be filled with the encapsulant 104_V using a printing mold technique. In the case of the printing mold technique, air may be captured in a space spaced between the semiconductor chip 101_V and the metal frame 102_V during the mold process. Accordingly, a separate process was required to discharge the air trapped in the space. Therefore, in order to proceed with a separate process of discharging the trapped air, the separation distance d_V between the semiconductor chip 101_V and the inner wall 102b_V of the metal frame 102_V must be maintained at least 250 micrometers. did.

However, in an embodiment of the present disclosure, the spaced space between the semiconductor chip 101_V and the metal frame 102_V may be filled with the encapsulant 104_V using a vacuum compression mold technique. The vacuum pressing mold technique vacuums a space spaced between the semiconductor chip 101_V and the inner wall 102b_V of the metal frame 102_V, and then applies pressure to the encapsulant 104_V to encapsulate the space 104_V. ) Can be filled in. Unlike the conventional printing mold technique, the vacuum crimping mold technique is extremely unlikely to trap air in the space between the semiconductor chip 101_V and the metal frame 102_V, and thus does not require a separate process of releasing the air. You may not. Thus, in one embodiment of the present disclosure, the separation distance d_V between the inner wall 102b_V of the metal frame 102_V and the semiconductor chip 101_V may be about 50 micrometers to about 150 micrometers. In an embodiment of the present disclosure, the separation distance d_V between the inner wall 102b_V of the metal frame 102_V and the semiconductor chip 101_V may be about 100 micrometers, which is compared with the conventional distance d_V. When about 2 to about 3 times reduced distance.

In an embodiment, the separation distance d_V between the semiconductor chip 101_V and the inner wall 102b_V of the metal frame 102_V can be reduced to about 100 micrometers, so that the heat dissipation effect of the semiconductor package 100_V can be improved. have. In addition, as the separation distance d_V between the semiconductor chip 101_V and the metal frame 102_V decreases, in the process of forming the semiconductor chips 101_V on the semiconductor wafer, The interval can be reduced. Therefore, since more semiconductor chips 101_V may be disposed on the wafer than in the related art, the production yield of the semiconductor package 100_V may be increased.

97 is a cross-sectional view of a semiconductor package 100b_V according to an embodiment of the present disclosure. The semiconductor package 100b_V includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 107_V. It may include. The technical concept of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V is illustrated in FIG. Since it is substantially the same as the technical idea described with reference to 94, detailed description thereof will be omitted.

In an embodiment, the thickness of the metal frame 102_V of the semiconductor package 100b_V may be smaller than the thickness of the semiconductor chip 101_V. That is, the top surface of the metal frame 102_V may be at a height lower than the top surface of the semiconductor chip 101_V.

98 and 99 are cross-sectional views of semiconductor packages 200a_V and 200b_V according to an embodiment of the present disclosure. The semiconductor packages 200a_V and 200b_V include a semiconductor chip 101_V, a metal frame 201_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 107_V). The technical concepts of the semiconductor chip 101_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V are described with reference to FIG. 94. Since it is substantially the same as the idea, detailed description is abbreviate | omitted.

98 and 99, the metal frame 201_V of the semiconductor packages 200a_V and 200b_V may include a first region 202_V and a first region 202a_V forming the inner wall 202a_V of the metal frame 201_V. The second region may extend outwardly from 202_V and form the outer wall 203a_V of the metal frame 201_V. In an embodiment, the thickness of the first region 202_V and the thickness of the second region 203_V may be different. In other words, the top surface of the first region 202_V and the top surface of the second region 203_V may be at different heights. For example, the thickness of the first region 202_V may be greater than the thickness of the second region 203_V.

In an embodiment, the first region 202_V of the metal frame 201_V may be a region that is not cut during the individualization process of the semiconductor packages 200a_V and 200b_V, and the second region 203_V may be the semiconductor packages 200a_V. , 200b_V). In an embodiment of the present disclosure, the material of the first region 202_V and the material of the second region 203_V may be different. For example, the material of the second region 203_V may include a material having a weaker rigidity than the material of the first region 202_V. Accordingly, the flexibility of the cutting process of the semiconductor packages 200a_V and 200b_V may be increased in the individualization process of the semiconductor packages 200a_V and 200b_V. For example, the choice of cutting blades for cutting the second region 203_V can be widened, and the cutting process of the second region 203_V can proceed quickly.

In an embodiment, the first region 202_V of the metal frame 201_V may be located inside the semiconductor packages 200a_V and 200b_V and may not be exposed to the outside. In addition, the outer wall 203a_V of the second region 203_V of the metal frame 201_V may be coplanar with side surfaces of the semiconductor packages 200a_V and 200b_V. That is, the outer wall 203a_V of the second region 203_V may be self-aligned with the side surfaces of the semiconductor packages 200a_V and 200b_V. When the semiconductor packages 200a_V and 200b_V are observed from the side, the outer wall 203a_V of the metal frame 201_V may be exposed to the outside.

Referring to FIG. 98, the thickness of the first region 202_V of the metal frame 201_V may be greater than the thickness of the second region 203_V. In addition, the thickness of the first region 202_V may be substantially the same as the thickness of the semiconductor chip 101_V, and thus the upper surface of the first region 202_V and the upper surface of the semiconductor chip 101_V may have substantially the same height. There may be. An encapsulant 104_V may be provided on an upper surface of the first region 202_V and an upper surface of the semiconductor chip 101_V, and the encapsulant 104_V may contact the first region 202_V and the semiconductor chip 101_V. have.

Referring to FIG. 99, the thickness of the first region 202_V of the metal frame 201_V may be greater than the thickness of the second region 203_V. In addition, the thickness of the first region 202_V may be substantially the same as the thickness of the semiconductor chip 101_V, and thus the upper surface of the first region 202_V and the upper surface of the semiconductor chip 101_V may have substantially the same height. There may be. However, the encapsulant 104_V may not be provided on the upper surface of the first region 202_V and the upper surface of the semiconductor chip 101_V. An adhesive film 106_V may be provided on an upper surface of the first region 202_V and an upper surface of the semiconductor chip 101_V, and may contact the first region 202_V and the semiconductor chip 101_V.

In an embodiment, the thickness of the second region 203_V of the metal frame 201_V may be smaller than the thickness of the first region 202_V, so that the semiconductor packages 200a_V in the individualization process of the semiconductor packages 200a_V and 200b_V. , 200b_V) flexibility of the cutting process can be increased.

100 and 101 are cross-sectional views of semiconductor packages 200c_V and 200d_V according to example embodiments. The semiconductor packages 200c_V and 200d_V may include a semiconductor chip 101_V, a metal frame 201_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink. 107_V). The technical concepts of the semiconductor chip 101_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V are described with reference to FIG. 94. Since it is substantially the same as the idea, detailed description is abbreviate | omitted.

100 and 101, the metal frame 201_V of the semiconductor packages 200c_V and 200d_V may include a first region 202_V and a first region 202a_V forming the inner wall 202a_V of the metal frame 201_V. The second region 203_V extends outwardly from 202_V and forms the outer wall 203a_V of the metal frame 201_V. In an embodiment, the thickness of the first region 202_V and the thickness of the second region 203_V may be different. In other words, the top surface of the first region 202_V and the top surface of the second region 203_V may be at different heights. For example, the thickness of the first region 202_V may be greater than the thickness of the second region 203_V.

Referring to FIG. 100, the thickness of the first region 202_V of the metal frame 201_V may be greater than the thickness of the second region 203_V. For example, the thickness of the first region 202_V may be substantially the same as the length value from the top surface of the redistribution layer 103_V to the bottom surface of the adhesive film 106_V. Accordingly, the top surface of the first region 202_V may contact the adhesive film 106_V. In addition, the thickness of the second region 203_V may be substantially the same as the thickness of the semiconductor chip 101_V. Accordingly, the upper surface of the second region 203_V and the upper surface of the semiconductor chip 101_V may have substantially the same height. Can be in. An encapsulant 104_V may be provided on an upper surface of the second region 203_V.

Referring to FIG. 101, the thickness of the first region 202_V of the metal frame 201_V may be greater than the thickness of the second region 203_V. For example, the thickness of the first region 202_V may be substantially the same as the length value from the top surface of the redistribution layer 103_V to the bottom surface of the adhesive film 106_V. Accordingly, the top surface of the first region 202_V may contact the adhesive film 106_V. In addition, the thickness of the second region 203_V may be smaller than the thickness of the semiconductor chip 101_V. That is, the top surface of the second region 203_V may be at a height lower than the top surface of the semiconductor chip 101_V. In addition, an encapsulant 104_V may be provided on an upper surface of the second region 203_V.

In an embodiment, the thickness of the second region 203_V of the metal frame 201_V may be smaller than the thickness of the first region 202_V, so that the semiconductor packages 200c_V in the individualization process of the semiconductor packages 200c_V and 200d_V. , 200d_V) flexibility of the cutting process can be increased.

In one embodiment, the first region 202_V and the second region 203_V described above may be separate from each other, and the first region 202_V and the second region 203_V may be contacted and integrated with each other.

102 is a perspective view of a semiconductor package 300_V according to an embodiment of the present disclosure. The semiconductor package 300_V includes a semiconductor chip 101_V, a metal frame 102_V, an encapsulant 104_V, a redistribution layer 103_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 107_V. It may include. The technical concept of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 1104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V is illustrated in FIG. Since it is substantially the same as the technical idea described with reference to 94, a detailed description thereof will be omitted.

In an embodiment, the semiconductor package 300_V may further include a protrusion 301_V extending from the side surface of the heat sink 107_V to the side surface of the semiconductor package 300_V. The protrusion 301_V may be one region of the remaining connection region S_V after the connection region S_V of the group of heat sinks (FIGS. 103 and 350_V) to be described later is cut by the individualization process of the semiconductor package 300_V. have.

In one embodiment, the top surface of the protrusion 301_V may be at the same height as the top surface of the heat sink 107_V. In addition, the outer surface 301a_V of the protrusion 301_V may be self aligned with the side surface of the semiconductor package 300_V. In addition, the protrusion 301_V may be integrated with the heat sink 107_V.

In an embodiment, the plurality of protrusions 301_V may extend from one side of the heat sink 107_V to one side of the semiconductor package 300_V. For example, as illustrated in FIG. 102, two protrusions 301_V may extend from one side of the heat sink 107_V to one side of the semiconductor package 300_V. However, the number of protrusions 301_V formed extending from one side of the heat sink 107_V to one side of the semiconductor package 300_V may be various, without being limited to the above.

In an exemplary embodiment, when the number of protrusions 301_V extending from one side of the heat sink 107_V to one side of the semiconductor package 300_V is plural, the heat sinks between the plurality of protrusions 301_V may be formed. A step D1_V may be formed by a height difference between an upper surface of 107_V and an upper surface of the adhesive film 106_V. The number of steps D1_V formed at one side of the heat sink 107_V may be different depending on the number of protrusions 301_V formed at one side of the heat sink 107_V. For example, referring to FIG. 102, when the number of protrusions 301_V formed at one side of the heat sink 107_V is two, the number of steps D1_V formed at one side of the heat sink 107_V is shown. May be three.

In one embodiment, the number of protrusions 301_V extending from one side of the heat sink 107_V to one side of the semiconductor package 300_V may be one. When the number of protrusions 301_V formed at one side of the heat sink 107_V is one, the number of steps D1_V formed at one side of the heat sink 107_V may be two.

In one embodiment, the material of the protrusion 301_V may be different from the material of the heat sink 107_V. For example, the material of the protrusion 301_V may be less rigid than the material of the heat sink 107_V. In an embodiment, the protrusion 301_V may include a metal material, a ceramic material, a carbon material, and a polymer material. Accordingly, the connection region S_V may be easily cut in the process of individualizing the semiconductor package 300_V to be described later.

FIG. 103 is a plan view of a group 350_V of heat sinks to which a plurality of heat sinks 107_V are connected, according to an embodiment of the present disclosure. FIG. 104 is a cross sectional view at line b_V of FIG. 103 of a population 350_V of heat sinks as one embodiment of the present disclosure, and FIG. 105 is at line c_V of FIG. 103 of a group 350_V of heat sinks as an embodiment of the present disclosure. It is a cross section of.

103 to 105, the heat sinks 107_V may be interconnected with the other heat sinks 107_V by the connection region S_V to form a group 350_V of heat sinks. More specifically, the heat sink 107_V may be connected with the other heat sinks 107_V and the connection region S_V in four directions of the side surfaces of the heat sink 107_V to form the population 350_V of the heat sinks. have.

In an embodiment, the connection region S_V may have a first length w_V which is a length value of the first direction X, and is a length value of the second direction Y perpendicular to the first direction X. It may have two lengths t_V. The first length w_V and the second length t_V may be determined by various values.

In one embodiment, the population 350_V of heat sinks is positioned on the top surface of the adhesive film 106_V of the plurality of semiconductor packages 300_V before the plurality of semiconductor packages 300_V are cut into individual semiconductor packages 300_V. Can be fixed. The heat sinks 107_V may form the population 350_V of the heat sinks by the connection region S_V, so that the population of the heat sinks 350_V can be easily aligned and mounted on the upper surfaces of the semiconductor packages 300_V. have. In addition, after placing the group of heat sinks 350_V on the adhesive film 106_V, heat and pressure may be applied to the adhesive film 106_V. The adhesive film 106_V may stably fix the group 350_V of heat sinks on the plurality of semiconductor packages 300_V.

In one embodiment, when the population of heat sinks 350_V is stably mounted on the plurality of semiconductor packages 300_V, the plurality of semiconductor packages 300_V are cut into individual semiconductor packages 300_V through a cutting process. Can be cut. Referring to FIG. 103, the cutting line L_V may be formed on the plurality of connection regions S_V. Since the cutting line L_V may be formed on the connection region S_V having the first length w_V and the second length t_V, the first length w_V and the second length t_V of the connection region S_V are provided. ) Is smaller, the cutting process of cutting the plurality of semiconductor packages 300_V mounted with the group of heat sinks 350_V into individual semiconductor packages 300_V may be easier.

In addition, since the population of heat sinks 350_V can be handled integrally, embodiments of the present disclosure can provide ease in the process of processing, transporting, and cutting the population of heat sinks 350_V.

Referring to FIG. 104, the difference due to the height difference between the top surface of the heat sink 107_V and the top surface of the adhesive film 106_V in the space where the connection region S_V is not formed (that is, the space between the connection regions S_V). In addition, referring to FIG. 105, a step D1_V may not be formed in a portion where the connection region S_V is formed.

FIG. 106 is a cross-sectional view taken along the straight line b_V of FIG. 103 of the plurality of semiconductor packages 300_V mounted with a population 350_V of heat sinks according to one embodiment of the present disclosure. 107 is a cross-sectional view taken along the straight line c_V of FIG. 103 of the plurality of semiconductor packages 300_V mounted with a population 350_V of heat sinks, which is an embodiment of the present disclosure.

Referring to FIG. 106, in the cutting process of the semiconductor packages 300_V, the second region of the adhesive film 106_V, the encapsulant 104_V, and the metal frame 201_V may be formed at a portion where the connection region S_V is not formed. 203_V), and a step of sequentially cutting the redistribution layer 103_V. In addition, referring to FIG. 107, in the cutting process of the semiconductor packages 300_V, the connection region S_V, the adhesive film 106_V, the encapsulant 104_V, and the metal frame 201_V are formed at the portion where the connection region S_V is formed. And sequentially cutting the second region 203_V and the redistribution layer 103_V.

In an embodiment, when the rigidity of the material of the connection region S_V is weaker than the rigidity of the material of the heat sink 107_V, the cutting process of the semiconductor packages 300_V may be easy. In addition, the cutting process may be facilitated by minimizing the first length w_V and the second length t_V of the connection region S_V.

In an embodiment, the second region 203_V of the metal frame 201_V may include a material having a weaker rigidity than the material of the first region 202_V, so that the cutting process of the semiconductor packages 300_V may be easy. have. In an embodiment, the thickness of the second region 203_V of the metal frame 201_V may be smaller than the thickness of the first region 202_V, thereby facilitating the cutting of the semiconductor packages 300_V.

108 is a plan view of a semiconductor package 300a_V according to an embodiment of the present disclosure. The semiconductor package 300a_V includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 107_V. It may include. The technical concept of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V is illustrated in FIG. 94. Since it is substantially the same as the technical spirit described with reference to, detailed description thereof will be omitted.

Referring to FIG. 108, the footprint of the adhesive film 106_V may be smaller than the footprint of the semiconductor package 300a_V. In addition, the footprint of the adhesive film 106_V may be smaller than the footprint of the encapsulant 104_V. As illustrated in FIG. 108, the footprint of the adhesive film 106_V may be larger than the footprint of the heat sink 107_V and smaller than the footprint of the encapsulant 104_V.

In one embodiment, when the semiconductor package 300a_V is viewed from above, at least one of the adhesive film 106_V and the encapsulant 104_V may be exposed to the outside and observed. For example, as shown in FIG. 108, when the footprint of the adhesive film 106_V is larger than the footprint of the heat sink 107_V and smaller than the footprint of the encapsulant 104_V, the semiconductor package 300a_V is removed. When looking down from the top, both the adhesive film 106_V and the encapsulant 104_V may be exposed to the outside.

However, the present invention is not limited thereto, and as shown in FIG. 102, when the footprint of the adhesive film 106_V is larger than the footprint of the heat sink 107_V and is substantially the same as the footprint of the encapsulant 104_V, the semiconductor package When looking down (300_V) from above, the encapsulant 104_V is not exposed to the outside, only the adhesive film 106_V may be exposed to the outside.

In one embodiment, when the semiconductor packages 300_V and 300a_V are viewed from top to bottom, the exposed area of the adhesive film 106_V and the encapsulant 104_V is about 5% to the area of the top surface of the semiconductor packages 300_V and 300a_V. About 40%.

109 and 110 are perspective views of semiconductor packages 300b_V and 300c_V according to an embodiment of the present disclosure. The semiconductor packages 300b_V and 300c_V include the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V). The technical concept of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 107_V is illustrated in FIG. 94. Since it is substantially the same as the technical spirit described with reference to, detailed description thereof will be omitted.

109 and 110, the semiconductor packages 300b_V and 300c_V may include at least a portion of a side surface of the heat sink 107_V and at least a portion of an inner surface of the protrusion 301_V on the encapsulant 104_V. The heat dissipation molding part 310_V surrounding the heat sink 107_V may be further included to cover and expose the top surface of the heat sink 107_V and the top surface of the protrusion 301_V to the outside. The heat dissipation molding part 310_V may be self-aligned with the side surfaces of the semiconductor packages 300b_V and 300c_V.

The heat dissipation molding part 310_V of the semiconductor packages 300b_V and 300c_V of the present disclosure may firmly fix the heat sink 107_V onto the encapsulant 104_V, and heat the heat generated from the semiconductor chip 101_V. The heat dissipation effect of the semiconductor packages 300b_V and 300c_V may be improved by concentrating on the center portion of the region 107_V.

In one embodiment, the heat dissipation molding part 310_V may include various materials such as a metal material, a ceramic material, a carbon material, and a polymer material. In one embodiment, the heat dissipation molding part 310_V may be an epoxy molding compound.

As described above, the outer surface of the heat dissipation molding part 310_V may be self-aligned with the side surfaces of the semiconductor packages 300b_V and 300c_V. In addition, when the semiconductor packages 300b_V and 300c_V are viewed from the top to the bottom, the sum of the footprints of the heat dissipation molding part 310_V, the heat sink 107_V, and the protrusion 301_V of the semiconductor packages 300b_V and 300c_V is the semiconductor package ( 300b_V, 300c_V) may be substantially the same.

Referring to FIG. 109, the heat dissipation molding part 310_V of the semiconductor package 300b_V may cover all of side surfaces of the heat sink 107_V. Accordingly, the side surface of the heat sink 107_V may not be exposed to the outside. In addition, the heat dissipation molding part 310_V completely covers the inner side surface of the protrusion 301_V, and the outer side surface 301a_V may be exposed to the outside. The thickness of the heat dissipation molding part 310_V may be substantially the same as the thickness of the heat sink 107_V and the protrusion 301_V. That is, the top surface of the heat dissipation molding part 310_V may be self-aligned with the top surface of the heat sink 107_V and the top surface of the protrusion 301_V.

Referring to FIG. 110, the heat dissipation molding part 310_V of the semiconductor package 300c_V may cover only a portion of the side surface of the heat sink 107_V. Accordingly, one portion of the side surface of the heat sink 107_V may be exposed to the outside. In addition, the heat dissipation molding part 310_V may cover only a portion of the inner side surface of the protrusion 301_V, and the outer side surface 301a_V may be exposed to the outside. The heat dissipation molding part 310_V may have a thickness smaller than that of the heat sink 107_V and the protrusion 301_V. Accordingly, a step D2_V may be formed between the top surface of the heat sink 107_V and the top surface of the heat dissipation molding part 310_V.

111 is a perspective view of a semiconductor package 400_V according to an embodiment of the present disclosure. The semiconductor package 400_V may include a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, and an adhesive film 106_V. The technical concepts of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, and the adhesive film 106_V are described with reference to FIG. 94. Since it is substantially the same as a thought, detailed description is abbreviate | omitted.

In an embodiment, the semiconductor package 400_V may further include a heat sink 401_V. As illustrated in FIG. 111, the heat sink 401_V may include a first heat dissipation layer 402_V and a second heat dissipation layer 403_V on the first heat dissipation layer 402_V. The footprint of the second heat dissipation layer 403_V may be smaller than the footprint of the first heat dissipation layer 402_V. Due to the difference in the footprint of the first heat dissipation layer 402_V and the second heat dissipation layer 403_V and the height of the second heat dissipation layer 403_V, the heat sink 401_V is in the shape of an inverted T. Can be.

In one embodiment, the materials of the first heat dissipation layer 402_V and the second heat dissipation layer 403_V may be substantially the same. More specifically, the first heat dissipation layer 402_V and the second heat dissipation layer 403_V may be combined and integrated with each other using the same material.

In an embodiment, the materials of the first heat dissipation layer 402_V and the second heat dissipation layer 403_V may be different. For example, the material of the first heat dissipation layer 402_V may include a metal having a higher thermal conductivity than the material of the second heat dissipation layer 403_V. However, the present invention is not limited thereto, and the material of the second heat dissipation layer 403_V may include a metal having higher thermal conductivity than the material of the first heat dissipation layer 402_V.

In one embodiment, the first heat dissipation layer 402_V and the second heat dissipation layer 403_V may have substantially the same thickness. However, the present invention is not limited thereto, and the first heat dissipation layer 402_V and the second heat dissipation layer 403_V may have different thicknesses. The sum of the thicknesses of the first heat dissipation layer 402_V and the second heat dissipation layer 403_V may be about 280 micrometers to about 560 micrometers, and may be about 25 percent to about 40 percent of the thickness of the entire semiconductor package 400_V. have.

Referring to FIG. 111, the footprint of the first heat dissipation layer 402_V may be smaller than the footprint of the adhesive film 106_V, and the footprint of the second heat dissipation layer 403_V may be smaller than that of the first heat dissipation layer 402_V. It can be smaller than the footprint. Accordingly, the semiconductor package 400_V may include a step D3_V formed by the height difference between the top surface of the first heat dissipation layer 402_V and the top surface of the adhesive film 106_V. In addition, the semiconductor package 400_V may include a step D4_V formed by a height difference between an upper surface of the second heat dissipation layer 403_V and an upper surface of the first heat dissipation layer 402_V.

112 is a perspective view of a semiconductor package 400a_V according to an embodiment of the present disclosure. The semiconductor package 400a_V includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 401_V. It may include. The technical concept of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 401_V is illustrated in FIG. 94. Since it is substantially the same as the technical spirit described with reference to, detailed description thereof will be omitted.

In an embodiment, the semiconductor package 400a_V may further include a protrusion 301_V extending from the side surface of the first heat dissipation layer 402_V of the heat sink 401_V to the side surface of the semiconductor package 400a_V. The protrusion 301_V may be a region of the remaining connection area S_V after the connection area S_V of the group of heat sinks described with reference to FIG. 10 is cut by the individualization process of the semiconductor package 400a_V.

In an embodiment, the top surface of the protrusion 301_V may be at the same height as the top surface of the first heat dissipation layer 402_V. In addition, the outer surface 301a_V of the protrusion 301_V may be self-aligned with the side surface of the semiconductor package 400a_V.

In an embodiment, the plurality of protrusions 301_V may extend from one side of the first heat dissipation layer 402_V to one side of the semiconductor package 400a_V. For example, as illustrated in FIG. 112, two protrusions 301_V may extend from one side of the first heat dissipation layer 402_V to one side of the semiconductor package 400a_V. However, the number of protrusions 301_V formed to extend from one side of the first heat dissipation layer 402_V to one side of the semiconductor package 400a_V may be various, without being limited to the above.

Other technical concepts of the protrusion 301_V of the semiconductor package 400a_V disclosed in FIG. 112 are substantially the same as those of the protrusion 301_V of the semiconductor package 300_V described with reference to FIG. 102, and thus a detailed description thereof will be omitted.

Referring to FIG. 112, the semiconductor package 400a_V may include a step D3_V formed by a height difference between an upper surface of the first heat dissipation layer 402_V and an upper surface of the adhesive film 106_V, and the second heat dissipation layer 403_V. It may include a step (D4_V) formed by the difference in the height of the upper surface of the top surface and the first heat radiation layer (402_V).

In an embodiment, the height of the step D4_V formed by the height difference between the top surface of the first heat dissipation layer 402_V and the top surface of the adhesive film 106_V may be substantially the same as the height of the first heat dissipation layer 402_V. The height of the step D4_V formed by the height difference between the top surface of the second heat dissipation layer 403_V and the top surface of the first heat dissipation layer 402_V may be substantially the same as the height of the second heat dissipation layer 403_V.

In an embodiment, the height of the step D3_V formed by the height difference between the top surface of the first heat dissipation layer 402_V and the top surface of the adhesive film 106_V may be the top surface of the second heat dissipation layer 403_V and the first heat dissipation layer 402_V. It may be smaller than the height of the step D4_V formed by the height difference of the upper surface. In addition, the thickness of the protrusion 301_V may be substantially the same as the height of the step D3_V formed by the height difference between the top surface of the first heat dissipation layer 402_V and the top surface of the adhesive film 106_V. When the thickness of the protrusion 301_V is small, in the individualization process of the semiconductor package 400a_V, the strength of the external force required for cutting the semiconductor package 400a_V may be small. Accordingly, flexibility of the cutting process of the semiconductor packages 400a_V may be increased. However, the heights of the steps D3_V and D4_V are not limited to the above, but may have various height values. For example, the height of the step D3_V formed by the height difference between the top surface of the first heat dissipation layer 402_V and the top surface of the adhesive film 106_V is the top surface of the second heat dissipation layer 403_V and the top surface of the first heat dissipation layer 402_V. It may be greater than or equal to the height value of the step D4_V formed by the height difference of.

In addition, the sum of the heights of the steps D3_V and D4_V may be about 25 percent to about 40 percent of the total thickness of the semiconductor package 400a_V. Thus, when the total thickness of the semiconductor package 400a_V is about 1.1 millimeters to about 1.4 millimeters, the sum of the heights of the steps D3_V and D4_V may be about 280 micrometers to about 560 micrometers.

113 is a perspective view of a semiconductor package 400b_V according to an embodiment of the present disclosure. The semiconductor package 400a_V includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 401_V. It may include. The technical concept of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 401_V is illustrated in FIG. 111. Since it is substantially the same as the technical idea described with reference to, detailed description thereof will be omitted.

In an embodiment, the semiconductor package 400b_V may further include a heat dissipation molding part 410_V. The heat dissipation molding part 410_V can firmly fix the heat sink 401_V onto the encapsulant 104_V, and concentrate the heat generated from the semiconductor chip 101_V to the center of the heat sink 107_V to provide the semiconductor package 400b_V. Can improve the heat dissipation effect.

In one embodiment, the heat dissipation molding part 410_V may include various materials such as a metal material, a ceramic material, a carbon material, and a polymer material. For example, the heat dissipation molding part 410_V may include an epoxy molding compound.

In one embodiment, the heat dissipation molding part 410_V may surround the first heat dissipation layer 402_V to cover the top surface and the side surfaces of the first heat dissipation layer 402_V. In addition, the heat dissipation molding part 410_V may surround the side surface of the second heat dissipation layer 403_V and may expose the top surface of the second heat dissipation layer 403_V to cover the side surface of the second heat dissipation layer 403_V.

In an embodiment, the top surface of the heat dissipation molding part 410_V may be self-aligned with the top surface of the second heat dissipation layer 403_V. That is, the top surface of the heat dissipation molding part 410_V may be at the same height as the top surface of the second heat dissipation layer 403_V. In addition, the side surface of the heat dissipation molding part 410_V may be self-aligned with the side surface of the semiconductor package 400b_V.

114 is a cross-sectional view of a semiconductor package 500_V according to an embodiment of the present disclosure. Referring to FIG. 114, the semiconductor package 500_V includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, and a heat sink 107_V. It may include. The technical concepts of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, and the heat sink 107_V are described with reference to FIG. 94. Since it is substantially the same as, detailed description thereof will be omitted.

In an embodiment, the semiconductor package 500_V may further include an adhesive film 501_V. The footprint of the adhesive film 501_V may be larger than the footprint of the heat sink 107_V, and the width of the first direction X of the adhesive film 501_V is in the first direction X of the heat sink 107_V. It can be larger than the width.

In one embodiment, the adhesive film 501_V may extend upward to the side surface of the heat sink 107_V to cover at least a portion of the side surface of the heat sink 107_V. As the adhesive film 501_V extends upwardly to the side of the heat sink 107_V, the heat sink 107_V may be firmly coupled to the encapsulant 104_V.

In one embodiment, the adhesive film 501_V may include a conductive material and a non-conductive material. For example, the material of the adhesive film 501_V may include at least one of silver, aluminum, silicon dioxide, aluminum nitride, and boron nitride.

In an embodiment, the adhesive film 501_V of the semiconductor package 500_V may cover all of the side surfaces of the heat sink 107_V and may not expose the side surfaces of the heat sink 107_V to the outside. In addition, the adhesive film 501_V may expose the top surface of the heat sink 107_V to the outside.

115 is a cross-sectional view of a semiconductor package 500a_V according to an embodiment of the present disclosure. In an embodiment, the adhesive film 501_V of the semiconductor package 500a_V may cover at least a portion of the side surface of the heat sink 107_V. Accordingly, only a portion of the side surface of the heat sink 107_V may be exposed to the outside. As shown in FIG. 115, the adhesive film 501_V may cover only a portion of the side surface of the heat sink 107_V and expose the rest of the heat sink 107_V except for the portion of the top surface and the side surface to the outside. have.

114 and 115, the width of the first direction X of the adhesive film 501_V is smaller than the width of the first direction X of the semiconductor packages 500_V and 500a_V, and the width of the heat sink 107_V may be reduced. It may be larger than the width of one direction (X). When the semiconductor packages 500_V and 500a_V are viewed from above, the sum of the footprints of the heat sink 107_V and the adhesive film 501_V may be smaller than that of the semiconductor packages 500_V and 500a_V.

However, the present invention is not limited thereto, and unlike FIGS. 114 and 115, the width of the first direction X of the adhesive film 501_V is substantially the same as the width of the first direction X of the semiconductor package. The heat sink may be larger than the width of the first direction X of the heat sink 107_V. At this time, when looking down the semiconductor package 500a_V from the top, the sum of the footprints of the heat sink 107_V and the adhesive film 501_V may be substantially the same as the footprint of the semiconductor package.

116 is a view illustrating a heat sink 600a_V according to an embodiment of the present disclosure, and FIG. 117 is a view illustrating a manufacturing process of the heat sink 600a_V according to an embodiment of the present disclosure. 118 is a view illustrating a heat sink 600b_V according to an embodiment of the present disclosure, and FIG. 119 is a view illustrating a manufacturing process of a heat sink 600b_V according to an embodiment of the present disclosure. The heat sinks 600a_V and 600b_V of the present disclosure may be mounted on the adhesive film 106_V of the semiconductor package 100_V described with reference to FIG. 94.

In one embodiment, the heat sinks 600a_V and 600b_V may include a plurality of materials. For example, the heat sinks 600a_V and 600b_V may include a first metal 601_V and a second metal 602_V different from the first metal 601_V. The second metal 602_V may be a plating layer formed on the first metal 601_V by the plating method. The second metal 602_V is to prevent oxidation of the first metal 601_V, and the second metal 602_V may be a metal having a slower oxidation rate than the first metal 601_V. Since the second metal 602_V may be plated on the surface of the first metal 601_V, the phenomenon of deterioration of the heat radiation effect by the oxide film generated by oxidizing the first metal 601_V may be prevented.

In one embodiment, the first metal 601_V may be copper and the second metal 602_V may be nickel. In addition, the first metal 601_V may be aluminum, and the second metal 602_V may be nickel. However, the present disclosure is not limited thereto, and the first metal 601_V and the second metal 602_V may include various metal materials.

Referring to FIG. 116, the second metal 602_V of the heat sink 600a_V may cover the top and bottom surfaces of the first metal 601_V and may be exposed to the outside without covering the side surfaces of the first metal 601_V. Can be. Accordingly, when the heat sink 600a_V is viewed from the side, the first metal 601_V and the second metal 602_V may be exposed to the outside and observed.

Referring to FIG. 117, after the first metal 601_V is manufactured to a wafer level or panel level, the second metal 602_V may form a plating layer on the first metal 601_V by a plating method. have. After the second metal 602_V is plated on the first metal 601_V, individual heat sinks 600a_V may be formed through a cutting process. Accordingly, the second metal 602_V may not be plated on the side surface of the first metal 601_V.

Referring to FIG. 118, the second metal 602_V of the heat sink 600b_V may cover all of the top, bottom, and side surfaces of the first metal 601_V. Accordingly, the first metal 601_V may not be exposed to the outside. When the heat sink 600b_V is viewed from the side, only the second metal 602_V may be exposed to the outside and observed.

Referring to FIG. 119, after the first metal 601_V is individualized at the package level, the second metal 602_V may form the plating layer on the first metal 601_V by the plating method. Accordingly, the second metal 602_V may be plated on all of the top, bottom, and side surfaces of the first metal 601_V.

In one embodiment, when the second metal 602_V is plated on the surface of the first metal 601_V, the thickness of the first metal 601_V is about 10 times to about 1000 times the thickness of the second metal 602_V. Can be. As the second metal 602_V is plated on the surface of the first metal 601_V, the heat dissipation effect of the heat sinks 600a_V and 600b_V may be improved. In addition, the rigidity of the heat sinks 600a_V and 600b_V can be increased, thereby preventing damage to the heat sinks 600a_V and 600b_V from external shock.

In one embodiment, the heat sinks 600a_V and 600b_V may comprise metal oxides or metal nitrides. For example, the heat sinks 600a_V and 600b_V may include aluminum oxide or aluminum nitride.

120 and 121 are cross-sectional views of semiconductor packages 700_V and 700a_V according to example embodiments. The semiconductor packages 700_V and 700a_V include the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, the adhesive film 106_V, and the heat sink 750_V. ) May be included. The technical concepts of the semiconductor chip 101_V, the metal frame 102_V, the redistribution layer 103_V, the encapsulant 104_V, the external connection terminal 105_V, and the adhesive film 106_V are described with reference to FIG. 94. Since it is substantially the same as the idea, a detailed description is omitted.

The heat sinks 750_V of the semiconductor packages 700_V and 700a_V may have a shape of an uneven structure. The dictionary meaning of the irregularities is concave and convex. The heat sink 750_V may include a base portion (FIGS. 122 and 123 and 701_V) and a plurality of protrusions (FIGS. 122 and 123, 702a_V and 702b_V) on the base portion 701_V. More specifically, the heat sink 750_V may include a plurality of protrusions 702a_V and 702b_V which protrude from the upper surface of the base portion 701_V having a flat plate shape. The plurality of protrusions 702a_V and 702b_V may be repeatedly arranged at a predetermined distance. For this reason, the heat sink 750_V may have a shape of an uneven structure in which concave and convex are repeated.

In an embodiment, the bottom surface of the base portion 701_V of the heat sink 750_V may be fixed by the adhesive film 106_V on the encapsulant 104_V of the semiconductor packages 700_V and 700a_V.

Referring to FIG. 120, the thickness of the metal frame 102_V of the semiconductor package 700_V may be substantially the same as the thickness of the semiconductor chip 101_V. An encapsulant 104_V may be provided on an upper surface of the metal frame 102_V and an upper surface of the semiconductor chip 101_V. Accordingly, the adhesive film 106_V may contact the upper surface of the encapsulant.

Referring to FIG. 121, the thickness of the metal frame 102_V of the semiconductor package 700a_V may be substantially the same as the thickness of the semiconductor chip 101_V. The encapsulant 104_V may not be provided on the upper surface of the metal frame 102_V and the upper surface of the semiconductor chip 101_V. Accordingly, the adhesive film 106_V may contact the top surface of the semiconductor chip 101_V and the top surface of the metal frame 102_V. Accordingly, the thickness of the semiconductor package 700a_V illustrated in FIG. 121 may be smaller than the thickness of the semiconductor package 700_V illustrated in FIG. 120.

122 and 123 are cross-sectional views of heat sinks 750a_V and 750b_V according to one embodiment of the present disclosure.

Referring to FIGS. 122 and 123, the thickness f ₁ _ V of the base 701_V may occupy about 40% to about 60% of the total thickness f_V of the heat sinks 750a_V and 750b_V. For example, the thickness f ₁ _ V of the base 701_V of the heat sinks 750a_V and 750b_V may be half of the total thickness f_V of the heat sinks 750a_V and 750b_V. When the total thickness f_V of the heat sinks 750a_V and 750b_V is about 400 micrometers, the thickness of the base portion 701_V of the heat sinks 750a_V and 750b_V may be about 200 micrometers.

In an embodiment, the protrusions 702a_V and 702b_V of the heat sinks 750a_V and 750b_V may be formed to be spaced apart from the neighboring other protrusions 702a_V and 702b_V by a predetermined distance g_V. The separation distance g_V may be about 100 micrometers to about 300 micrometers. More specifically, the separation distance g_V may be about 200 micrometers.

In an embodiment, the width e_V formed by the protrusions 702a_V and 702b_V of the heat sinks 750a_V and 750b_V may be about 100 micrometers to about 300 micrometers. More specifically, the width e_V formed by the protrusions 702a_V and 702b_V may be about 200 micrometers.

In one embodiment, the thickness f ₂ _V formed by the protrusions 702a_V and 702b_V of the heat sinks 750a_V and 750b_V is about 40 percent to about 60 percent of the total thickness f_V of the heat sinks 750a_V and 750b_V. Can occupy. In an embodiment, the thickness f ₂ _ V of the protrusions 702a_V and 702b_V of the heat sinks 750a_V and 750b_V may be half the total thickness f_V of the heat sinks 750a_V and 750b_V. For example, when the total thickness f_V of the heat sinks 750a_V and 750b_V is about 400 micrometers, the thickness f ₂ _V of the protrusions 702a_V and 702b_V of the heat sinks 750a_V and 702b_V is about 200 micrometers.

In one embodiment, the heat sink (750a_V, 750b_V) Total thickness (f_V) has a base (701_V) thickness (f ₁ _V) and the projection sum (f_V = f of the thickness (f ₂ _V) of (702a_V, 702b_V) of ₁ _V + f ₂ _V). In one embodiment, when the total thickness f_V of the heat sinks 750a_V and 750b_V is about 400 micrometers, the thickness f ₁ _V of the base 701_V is the total thickness f_V of the heat sinks 750a_V and 750b_V. Can be about 160 micrometers, which is about 40 percent, wherein the thickness f ₂ _ of the protrusions 702a_V, 702b_V is about 240, about 60 percent of the thickness f_V of the heat sinks 750a_V, 750b_V. Micrometers. Further, when the thickness f ₁ _ V of the base portion 701_V is about 240 micrometers which is about 60 percent of the thickness f_V of the heat sinks 750a_V and 750b_V, the thickness f ₂ of the protrusions 702a_V and 702b_V _V may be about 160 micrometers, which is about 40 percent of the thickness f_V of the heat sinks 750a_V, 750b_V. In addition, the thickness f ₁ _ V of the base portion 701_V of the heat sinks 750a_V and 750b_V and the thickness f ₂ _V of the protrusions 702a_V and 702b_V may be substantially the same, and in some embodiments, about 200, respectively. Micrometers.

Referring to FIG. 122, the protrusion 702a_V of the heat sink 750a_V may include a flat plane thereon. In addition, referring to FIG. 123, the protrusion 702b_V of the heat sink 750b_V may include a curved surface that is convex from the top. However, the present invention is not limited thereto, and the protrusions of the heat sink may have various shapes.

In an embodiment, the heat sink 750a_V may include a plurality of protrusions 702a_V through a process of cutting a portion of a rectangular parallelepiped heat sink having a predetermined thickness f_V using a cutting device. . The cutting blade of the cutting device may have a separation width g_V between the plurality of protrusions 702a_V as the cutting width, and may have a thickness f ₂ _V of the plurality of the protrusions 702a_V as the cutting depth. . The cutting device may simultaneously cut a portion of the heat sink while moving along the cutting lane, such that the heat sink 750a_V may include the plurality of protrusions 702a_V described above.

Referring to FIG. 123, the heat sink 750b_V forms the protrusions 702a_V through the above-described cutting device, and then the upper surface of the heat sink 750a_V is convexly curved through the additional cutting process of smoothly cutting the upper portions of the protrusions 702a_V. The protrusions 702b_V may have a shape of.

In one embodiment, the heat sinks 750a_V and 750b_V shown in FIGS. 122 and 123 may be formed through an injection molding process rather than the above-described cutting process.

More specifically, the material to be formed as the heat sinks 750a_V and 750b_V may be injected into the injection molding heating chamber. The material of the heat sinks 750a_V and 750b_V injected into the heating chamber may be melted by the high temperature of the heating chamber. The molten material may be injected into an injection molding machine including an injection space having a shape of heat sinks 750a_V and 750b_V of FIGS. 122 and 123. The injected molten material may fill the injection space in the shape of the heat sinks 750a_V and 750b_V. Thereafter, the injection molding machine may cool the molten material in the injection space to finally form the heat sinks 750a_V and 750b_V shown in FIGS. 122 and 123. When the injection molding process is used, the shape of the uneven structure of the heat sinks 750a_V and 750b_V is not limited to those shown in FIGS. 122 and 123, and may be more varied according to the shape of the injection space of the injection molding machine. Can be.

The heat sinks 750a_V and 750b_V of FIGS. 122 and 123 are not limited to the above-described cutting process and injection molding process, and may form the uneven structure through various processes. In an embodiment, the uneven structures of the heat sinks 750a_V and 750b_V may be formed through a chemical reaction. In addition, in one embodiment, the heat sinks 750a_V and 750b_V may form an uneven structure through a process of physically bonding a plurality of protrusions 702a_V and 702b_V separately formed on the base 701_V. In this case, the materials of the protrusions 702a_V and 702b_V and the base 701_V of the heat sinks 750a_V and 750b_V may be different.

In an embodiment, the heat sinks 750a_V and 750b_V may have a concave-convex structure, so that heat dissipation performance of the semiconductor packages 700_V and 700a_V may be improved. More specifically, since the heat sinks 750a_V and 750b_V of the semiconductor packages 700_V and 700a_V form an uneven structure, the heat sinks 750a_V and 750b_V may have a large surface area in contact with external air. Accordingly, the semiconductor packages 700_V and 700a_V equipped with the heat sinks 750a_V and 750b_V may more quickly release heat emitted from the semiconductor chip 101_V in the semiconductor packages 700_V and 700a_V to the outside.

124 to 126 are plan views of heat sinks 800a_V, 800b_V, and 800c_V having a concave-convex structure including a marking area in which information of a semiconductor package is displayed, according to an exemplary embodiment. The semiconductor package includes a semiconductor chip 101_V, a metal frame 102_V, a redistribution layer 103_V, an encapsulant 104_V, an external connection terminal 105_V, an adhesive film 106_V, and a heat sink 800_V having the uneven structure. , 800a_V, 800b_V).

Referring to FIG. 124, as described above, the heat sink 800a_V may include a base 801_V and a protrusion 802_V. In addition, the heat sink 800a_V includes a marking area 804_V including marking of information on the semiconductor package on the base 801_V, and a protrusion area including a plurality of protrusions 802_V protruding from the base 801_V. 803_V).

In an embodiment, the protrusion 802_V may not be formed in the marking region 804_V. In other words, the heat sink 800a_V may not include a concave-convex structure at one portion, and the marking region 804_V may be formed on the surface of the base portion 801_V in which the protrusion 802_V is not formed. Therefore, the marking area 804_V may be lower than the upper surface of the protrusion 802_V.

The heat sink 800a_V illustrated in FIG. 124 may include a marking region 804_V in the plane of the base portion 801_V in which the protrusions 802_V are not formed at the upper left, and the marking region 804_V includes a semiconductor package. Information of the semiconductor chip mounted therein may be marked. However, the marking region 804_V is not limited to the position shown in FIG. 124, and may be formed at more various positions of the heat sink 800a_V.

In one embodiment, the marking area 804_V of the semiconductor package may be marked with information about the semiconductor chip, such as the type, number, performance, name and / or logo of the manufacturer, manufacturing date, serial number, and the like of the semiconductor chip.

More specifically, as a technique of ink marking, the information of the semiconductor chip may be marked by using a pad printing technique. The pad printing technique may mark the semiconductor information by pushing an ink-filled palette onto a pad of silicon rubber having an embossed or intaglio pattern formed thereon so that the ink in the palette contacts the surface of the marking area 804_V. The pad printing technique can mark the information of the semiconductor package at low cost, and since the pad of the silicone rubber is elastic, the semiconductor information can be cleanly marked even on the surface of the uneven heat sink.

In addition, the information of the semiconductor chip may be marked by a technique of laser marking. The laser marking technique focuses the laser light emitted from the laser device on the marking area 804_V of the heat sink 800a_V by using a laser device to dig a portion of the marking area 804_V to form letters or numbers. Inscribed can represent the information of the semiconductor chip. In addition, the laser device may adjust the intensity of the laser light by adjusting the intensity of the power supplied to the laser device, thereby adjusting the thickness of letters and numbers formed in the marking area 804_V of the heat sink 800a_V. Can be.

Laser devices used for marking semiconductor chip information in the marking region 804_V of the heat sink 800a_V of the present disclosure are not limited to the above-described CO ₂ laser device, YAG laser device, and diode laser device. Various laser devices may further be included.

Referring to FIG. 125, the heat sink 800b_V may include a base 801_V and protrusions 802_V. In addition, the heat sink 800b_V may include the above-described protrusion region 803_V and the marking region 805_V protruding from the base portion 801_V.

In one embodiment, the marking region 805_V may protrude from the top surface of the base portion 801_V of the heat sink 800b_V. More specifically, the marking region 805_V may protrude from the top surface of the base portion 801_V, and the top surface of the protruding marking region 805_V may have a planar shape. The width of the upper surface of the marking area 805_V may be larger than the width of the upper surface of the one protrusion 802_V and may be smaller than the footprint of the heat sink 800b_V. In one embodiment, the marking area 805_V of the heat sink 800b_V may occupy about 10 percent to about 80 percent of the footprint of the heat sink 800b_V.

In one embodiment, the height formed by the marking area 805_V protruding from the base 801_V may be substantially the same as the height of the protrusion 802_V. Accordingly, the top surface of the marking region 805_V may be coplanar with the top surfaces of the protrusions 802_V of the protrusion region 803_V. The height at which the marking area 805_V protrudes from the base 801_V and the height at which the protrusions 802_V protrude from the base 801_V may be between about 40 percent and about 60 percent of the total thickness of the heat sink 800b_V.

In an embodiment, the information of the semiconductor chip may be represented on the top surface of the marking region 805_V by the above-described ink marking technique or laser marking technique.

In FIG. 125, the marking region 805_V is illustrated as being formed on the upper left side of the heat sink 800b_V. However, the marking region 805_V is not limited to the above position and may be formed at more various positions of the heat sink 800b_V. .

The heat sink 800b_V of FIG. 125 may have a large cross-sectional area of the heat sink 800b_V in contact with the outside air due to the shape of the marking area 805_V protruding from the base 801_V, and thus may have excellent heat dissipation effect. .

As illustrated in FIG. 126, the heat sink 800c_V may include first protrusions 802a_V protruding on the base portion 801_V in the protrusion region 803_V, and the base portion 801_V in the marking region 806_V. ) May include second protrusions 802b_V protruding from each other. In other words, the region including the protrusion 802b_V where the information of the semiconductor package is marked among the plurality of protrusions may be the marking region 806_V, and the region including the protrusion 802a_V where the information of the semiconductor package is not marked. May be the protruding region 803_V.

In one embodiment, the marking area 806_V may include consecutive letters and numbers representing information of the semiconductor package on the top surface of the base portion 801_V and the second protrusions 802b_V. More specifically, the information of the semiconductor chip may be expressed on the upper surface of the base portion 801_V and the upper surface of the second protrusion 802b_V disposed under the marking region 806_V. The information of the semiconductor chip may be marked by marking a portion of the base portion 801_V and a portion of the second protrusion portion 802b_V by the laser device, and also a portion of the base portion 801_V and a portion of the second protrusion portion 802b_V. Ink can be painted and marked.

In an embodiment, the thicknesses of the first protrusions 802a_V and the second protrusions 802b_V formed on the heat sink 800c_V may be different from each other. More specifically, the thickness formed by the second protrusions 802b_V may be smaller in order to include consecutive letters and numbers on the upper surface and the base portion 801_V of the second protrusions 802b_V in the marking area 806_V. . The smaller the thickness of the second protrusions 802b_V, the smaller the change of the height of the point where the laser light is collected in the case of laser marking, so that the letters and numbers can be inscribed. In the case of ink marking, the silicon This is because the change in the length that the pad of rubber has to be stretched by elasticity can be small.

Therefore, the height formed by the second protrusions 802b_V in the marking area 806_V of the heat sink 800c_V of the present disclosure may be substantially smaller than the height formed by the second protrusions 802a_V of the protrusion area 803_V. have. In an embodiment, the height formed by the second protrusions 802b_V may be between about 1/4 and about 1/2 of the height formed by the first protrusions 802a_V. In an embodiment of the present disclosure, when the total thickness of the heat sink 800c_V is about 400 micrometers, the thickness of the base 801_V is about 200 micrometers, and the height of the first protrusions 802a_V is about 200 micrometers, The height of the second protrusions 802b_V may be about 2 times to about 4 times smaller than the height of the first protrusions 802a_V. Accordingly, the height of the second protrusions 802b_V may be about 50 micrometers to about 100 micrometers.

In one embodiment, due to the low height of the second protrusions 802b_V formed in the marking area 806_V of the heat sink 800c_V, the heat sink 800c_V is the base 801_V and the second of the marking area 806_V. Continuous letters and numbers may be formed on the upper surfaces of the protrusions 802b_V to represent information of the semiconductor package. For example, in the case of laser marking, the change in the height of the point where the laser light is collected in the marking area 806_V may be about 50 micrometers to about 100 micrometers. Accordingly, letters and numbers may be continuously marked in an ordered shape in the marking area 806_V without separately controlling the height of the light converging point of the laser light. In addition, even when controlling the height of the light collecting point of the laser light, only about 50 micrometers to about 100 micrometers of position control of the laser device may be necessary, so that energy consumption may be low when driving the laser device, and the laser device is driven. The control time of can be reduced.

In the case of ink marking, since the change in the length that the pad of the silicone rubber should be stretched by elasticity may be small from about 50 micrometers to about 100 micrometers, the upper surface of the second protrusions 802b_V of the marking region 806_V and Letters and numbers representing semiconductor information may be marked in a more ordered shape at the base portion 801_V.

127 is a view illustrating attaching a metal frame 201_V to a glass substrate 901_V according to an embodiment of the present disclosure. For example, the metal frame 201_V may be the metal frame 201_V described above.

In an embodiment, the method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a metal frame 201_V to an upper surface of the glass substrate 901_V. An adhesive layer (not shown) may be formed on an upper surface of the glass substrate 901_V. The metal frame 102_V may be physically attached to an upper surface of the glass substrate 901_V by the adhesive layer (not shown).

116 is a plan view of a plurality of metal frames 950_V attached to a glass substrate as an embodiment of the present disclosure. The plurality of metal frames 950_V attached to the upper surface of the glass substrate 901_V may be formed by connecting individual metal frames 201_V to each other. The plurality of metal frames 950_V may be formed at a wafer level or a panel level. After the semiconductor package generation process is completed, the plurality of metal frames 950_V may be separated into individual metal frames 201_V through a cutting process into individual semiconductor packages. The metal frame 201_V may include a cavity 114_V, and the semiconductor chip 101_V may be spaced apart from the inner wall 202a_V of the metal frame 201_V by a predetermined distance in the cavity 114_V.

129 is a view illustrating a step of mounting a semiconductor chip 101_V on a glass substrate 901_V according to an embodiment of the present disclosure. Referring to FIG. 129, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include mounting a semiconductor chip 101_V on a glass substrate 901_V. The semiconductor chip 101_V may be provided in the cavity 114_V formed by the inner wall 202a_V of the metal frame 201_V. The semiconductor chip 101_V and the inner wall 202a_V of the metal frame 201_V may be spaced apart from the predetermined distance d_V. The separation distance d_V may be about 50 micrometers to about 150 micrometers. In one embodiment, the separation distance d_V may be about 100 micrometers.

Considering that the separation distance d_V between the semiconductor chip 101_V and the inner wall 202a_V of the metal frame 201_V is about 250 micrometers, an embodiment of the present disclosure provides a separation distance d_V of about half or less. In this case, the plurality of semiconductor chips 101_V may be easily mounted on the glass substrate 901_V, so that the productivity of the semiconductor packages may be improved.

In addition, as the thickness of the metal frame 201_V is smaller, the accuracy of the mounting process on the glass substrate 901_V of the semiconductor chip 101_V may be improved, and the speed of the mounting process may be faster. Therefore, as described above, the height of the frame 201_V may be less than or equal to the thickness of the semiconductor chip 101_V. However, the present invention is not limited thereto, and the metal frame 201_V may have a thickness greater than that of the semiconductor chip 101_V. When the thickness of the metal frame 201_V is larger than the thickness of the semiconductor chip 101_V, the heat dissipation effect of the semiconductor package may be improved.

FIG. 130 is a view illustrating a step of covering and fixing the semiconductor chip 101_V and the metal frame 102_V with the encapsulant 104_V according to an embodiment of the present disclosure. Referring to FIG. 130, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include covering and fixing a semiconductor chip 101_V and a metal frame 201_V with an encapsulant 104_V. . The encapsulant 104_V fills a space formed by a predetermined distance d_V spaced apart between the semiconductor chip 101_V and the inner wall 202a_V of the metal frame 201_V to integrate the semiconductor chip 101_V and the metal frame 201_V. have. In addition, the encapsulant 104_V may cover the upper surfaces of the semiconductor chip 101_V and the metal frame 201_V. The encapsulant 104_V may cover and fix the semiconductor chip 101_V and the metal frame 201_V by using a vacuum pressing mold technique, which will be described in more detail with reference to FIG. 131.

Although not shown in FIG. 130, in an embodiment of the present disclosure, an upper surface of the encapsulant 104_V covering the upper surface of the semiconductor chip 101_V and the metal frame 201_V is ground to grind the upper surface of the semiconductor chip 101_V. The method may further include exposing to the outside.

FIG. 131 is a view illustrating mounting an encapsulant 104_V on a glass substrate 901_V using a vacuum crimp mold technique, which is an embodiment of the present disclosure. In the semiconductor package manufacturing method of the present disclosure, the encapsulant 104_V may be mounted on the glass substrate 901_V using the vacuum compression mold apparatus 1100_V to fix the semiconductor chip 101_V and the metal frame 201_V. .

Referring to FIG. 131, the vacuum pressing mold apparatus 1100_V may contact the lower surface of the glass substrate 901_V at the upper portion 1101_V of the vacuum pressing mold apparatus to fix the glass substrate 901_V in an inverted state. . The vacuum compression mold apparatus 1100_V may mount the film 1103_V at the lower portion 1102_V of the vacuum compression mold apparatus. An encapsulant 104_V may be disposed on an upper surface of the film 1103_V. Before being mounted on the glass substrate 901_V, the encapsulant 104_V on the top surface of the film 1103_V may be in a liquid or solid state. In addition, the encapsulant 104_V may be a polymer material such as a silicone-based material, a thermosetting material, a thermoplastic material, a UV treatment material, a resin, and the like, for example, an epoxy molding compound (EMC). It may include.

When the glass substrate 901_V is fixed to the vacuum pressing mold apparatus 1100_V and the encapsulant 104_V is disposed, the upper portion 1101_V and the lower portion 1102_V of the vacuum pressing mold apparatus 1100_V are in the vertical direction (Z direction). Can move relatively. Accordingly, a sealed space 1104_V may be formed between the semiconductor package and the lower portion 1102_V of the vacuum compression device. At this time, the vacuum compression mold apparatus 1100_V may discharge the gas in the sealed space 1104_V to the outside to make the sealed space 1104_V in a vacuum state. After the process of vacuuming the enclosed space 1104_V is completed, the vacuum crimping mold apparatus 1101_V may apply pressure to the encapsulant 104_V in the direction of the glass substrate 901_V. Therefore, the encapsulant 104_V may be provided in a space formed by being spaced apart from the semiconductor chip 101_V by a predetermined distance d_V between the inner wall 202a_V of the metal frame 201_V, and also the semiconductor chip 101_V and the metal frame. It may be provided on the upper surface of 201_V.

In the related art, the space formed by the separation distance d_V between the semiconductor chip 101_V and the metal frame 201_V may be filled with the encapsulant 104_V using a printing mold technique. More specifically, in the related art, the encapsulant 104_V is placed on a space between the semiconductor chip 101_V and the metal frame 201_V, and then a physical pressure is applied to the encapsulant 104_V using a pressure tool. The encapsulant 104_V may be provided in the spaced space between the 101_V and the metal frame 201_V.

In the case of the printing mold technique, a space formed by a separation distance d_V between the semiconductor chip 101_V and the metal frame 102_V or the inside of the semiconductor package 100_V during the process of inserting the encapsulant 104_V. The air present in the space could not be discharged to the outside and some air could be captured in the semiconductor package 100_V. Therefore, conventionally, a separate process is required to discharge the trapped air to the outside. In order to proceed with a separate process to discharge the air, the separation distance d_V between the semiconductor chip 101_V and the inner wall of the metal frame 201_V should be maintained at least 250 micrometers.

However, when using the vacuum crimping mold technique in an embodiment of the present disclosure, since the encapsulant 104_V may be mounted on the glass substrate 901_V in a vacuum state, a separate process of releasing air may not be necessary. have. Therefore, the separation distance d_V between the semiconductor chip 101_V and the inner wall 202a_V of the metal frame 201_V can be reduced to about 50 micrometers to about 150 micrometers, which is reduced by about half or less. Due to the reduced separation distance d_V, the heat transfer resistance of the heat generated from the semiconductor chip 101_V on the semiconductor package may be reduced, so that the heat dissipation effect of the semiconductor package may be improved. In addition, in the process of mounting the semiconductor chips 101_V on a wafer, more semiconductor chips 101_V may be disposed on the wafer, so that the productivity of the semiconductor package may be further improved.

In addition, the vacuum pressing mold technique may be applied without being restricted by the shape of the metal frame 201_V, so that the metal frame 201_V having various shapes may be applied as an embodiment of the present disclosure. In addition, the vacuum compression mold technique is shorter in the process time than the conventional printing mold technique, and thus the productivity of the semiconductor package may be further improved.

132 and 133 illustrate attaching a heat sink 107_V to a semiconductor package according to an embodiment of the present disclosure. 132 and 133, the method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching a heat sink 107_V onto the semiconductor package.

132 and 133, the heat sink 107_V may be attached to the top surface of the semiconductor chip 101_V or the top surface of the encapsulant 104_V. The method of arranging the heat sink 107_V in close contact with the top surface of the semiconductor chip 101_V or the top surface of the encapsulant 104_V may include a thermocompression bonding method. The thermal crimping method may be a method of applying heat and pressure to the adhesive film 106_V positioned below the heat sink 107_V using a compactor. Through the thermocompression method, the adhesive film 106_V may stably attach the heat sink 107_V to the top surface of the semiconductor chip 101_V and the encapsulant 104_V.

Referring to FIG. 132, the heat sink 107_V may be cut into a size corresponding to the size of the individual semiconductor package and then separately mounted on the semiconductor package. In an embodiment, when the semiconductor package is manufactured by mounting the heat sinks 107_V cut to the size of individual semiconductor packages, the semiconductor package 100_V described with reference to FIG. 94 may be produced.

Referring to FIG. 133, the population 350_V of the heat sinks described with reference to FIG. 103 may be seated on the semiconductor package. The population 350_V of heat sinks may be sized to correspond to wafer level or panel level. After the population of the heat sinks 350_V is seated, the process of individualizing the semiconductor packages may proceed. In this case, the semiconductor package 300_V described with reference to FIG. 102 may be produced.

134 is a view illustrating removing a glass substrate 901_V and flipping a semiconductor package according to an embodiment of the present disclosure. Referring to FIG. 134, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include separating a glass substrate 901_V and inverting the semiconductor package.

FIG. 135 illustrates a step of forming the redistribution layer 103_V and the external connection terminal 105_V and individualizing the semiconductor packages according to the exemplary embodiment of the present disclosure.

Referring to FIG. 135, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include forming a redistribution layer 103_V. The redistribution layer 103_V may include a wiring pattern 103a_V and an insulation pattern 103b_V. In an exemplary embodiment of the present disclosure, the insulating pattern 103b_V may include a non-photosensitive material, and after the insulating pattern 103b_V is formed on the bottom surface of the semiconductor chip 101_V, the insulating pattern 103b_V may be a semiconductor chip ( A portion of the chip pad 113_V of 101_V may be partially removed. After the insulating pattern 103b_V is formed, the wiring pattern 103a_V may be electrically connected to the chip pad 113_V exposed by the opening of the insulating pattern 103b_V. The wiring pattern 103a_V may be formed by plating, electroless plating, electroplating, or a combination thereof, and may be formed on the insulating pattern 103b_V through a plating process. When the wiring pattern 103a_V is formed, the insulating pattern 103b_V may be formed once again on the wiring pattern 103a_V. In this case, a part of the wiring pattern 103a_V may be partially exposed to be connected to the external connection terminal 105_V.

In addition, referring to FIG. 135, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include attaching an external connection terminal 105_V. In one embodiment, the external connection terminal 105_V may be a solder ball. The external connection terminal 105_V may be attached to the wiring pattern 1501_V exposed through the soldering process.

In addition, referring to FIG. 135, a method of manufacturing a semiconductor package according to an embodiment of the inventive concept may include individualizing a plurality of semiconductor packages.

The process of cutting the plurality of semiconductor packages into individual packages includes cutting the redistribution layer 103_V, the metal frame 102_V, the encapsulant 104_V, and the heat sink 107_V of the semiconductor package using the cutting blades. It may include. At this time, by controlling the thickness of the metal frame 102_V, which is relatively harder than the encapsulant 104_V, the cutting process may be easily provided.

In one embodiment, as described above, as the thickness of the second region 203_V of the metal frame 201_V is smaller, the cutting depth of the metal frame 201_V of the cutting blade may be shorter, so that the cutting process of the semiconductor package may be performed. Can be facilitated. In addition, since the material of the second region 203_V of the metal frame 201_V may be weaker than the material of the first region 202_V, the cutting process of the semiconductor package may be facilitated.

Referring to FIG. 136, the electronic system 1500_V may include at least one of semiconductor packages of various embodiments of the inventive concept. The electronic system 1500_V may be included in a mobile device or a computer. For example, the electronic system 1500_V may include a memory system 1501_V, a microprocessor 1502_V, a RAM 1503_V, and a user interface 1504_V that performs data communication.

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although embodiments have been described using specific terms herein, they are used only for the purpose of describing the technical spirit of the present disclosure and are not used to limit the scope of the present disclosure as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure will be defined by the technical spirit of the appended claims.

Claims

A semiconductor chip including a chip pad;

A redistribution layer electrically connected to the chip pad of the semiconductor chip;

An external connection terminal electrically connected to the redistribution layer;

An encapsulant configured to cover the semiconductor chip and to fix the semiconductor chip and the redistribution layer;

An adhesive film positioned on an upper surface of the encapsulant; And

A heat sink formed on an upper surface of the adhesive film and having a step at an edge thereof;

Semiconductor package comprising a.
According to claim 1,

The heat sink is a first heat radiation layer formed on the upper surface of the adhesive film;

A second heat dissipation layer formed on an upper surface of the first heat dissipation layer; And

Protrusions formed on the side of the first heat dissipation layer;

Semiconductor package comprising a.
The method of claim 2,

The protrusion

And self-aligning the side surface of the semiconductor package.
The method of claim 3, wherein

And a footprint of the first heat dissipation layer is larger than a footprint of the second heat dissipation layer.
The method of claim 4, wherein

The step of the heat sink is

A first step formed between the adhesive film and the first heat dissipation layer; And

A second step formed between the first heat dissipation layer and the second heat dissipation layer;

Semiconductor package comprising a.
The method of claim 5,

Further comprising a heat dissipation molding unit,

The heat dissipation molding part

Is formed on the upper surface of the adhesive film to cover the upper surface and the side of the first heat dissipation layer,

Cover the side of the second heat dissipation layer, the top surface is exposed,

A semiconductor package, characterized in that for covering the upper surface of the protrusion.
The method of claim 6,

The heat dissipation molding part

Exposing the side of the protrusion self-aligned with the side of the semiconductor package to the outside

The footprint formed by the heat sink and the heat dissipation molding unit is a semiconductor package, characterized in that the same as the footprint (footprint) of the semiconductor package.
The method of claim 7, wherein

The heat dissipation molding material is

The semiconductor package, characterized in that the rigidity is weaker than the material of the protrusion.
The method of claim 8,

The heat dissipation molding unit is a semiconductor package, characterized in that the epoxy molding compound (Epoxy Molding Compound).
The method of claim 9,

The height of the first step is a semiconductor package, characterized in that less than the height of the second step.
The method of claim 10,

And the sum of the heights of the first and second steps is from about 25 percent to about 40 percent of the thickness of the semiconductor package.
A semiconductor chip including a chip pad;

A redistribution layer electrically connected to the chip pad of the semiconductor chip;

An external connection terminal electrically connected to the redistribution layer;

An encapsulant configured to cover the semiconductor chip and to fix the semiconductor chip and the redistribution layer;

An adhesive film positioned on an upper surface of the encapsulant;

A heat sink positioned on an upper surface of the adhesive film; And

Including a heat dissipation molding portion surrounding the side of the heat sink,

The height of the heat dissipation molding portion is the same as the height of the heat sink,

And a top surface of the heat dissipation molding part is self-aligned with the top surface of the heat sink to expose the top surface of the heat sink to the outside.
The method of claim 12,

The side surface of the heat dissipation molding part is self-aligned with the side surface of the semiconductor package,

And a footprint formed by the heat dissipation molding part and the heat sink is the same as the footprint of the semiconductor package.
The method of claim 13,

And the heat sink has a rectangular parallelepiped shape, and the footprint of the heat sink is the same as that of the semiconductor chip.
The method of claim 14,

And the heat sink has a thickness of about 25 percent to about 40 percent of the thickness of the semiconductor package.
A semiconductor chip including a chip pad;

A redistribution layer electrically connected to the chip pad of the semiconductor chip;

An external connection terminal electrically connected to the redistribution layer;

An encapsulant configured to cover the semiconductor chip and to fix the semiconductor chip and the redistribution layer;

An adhesive film positioned on an upper surface of the encapsulant; And

And a heat sink located on an upper surface of the adhesive film.

The adhesive film extends to the side of the heat sink to cover the side of the heat sink,

The adhesive film is self-aligned with the top surface of the heat sink is a semiconductor package, characterized in that to expose the top surface of the heat sink.
The method of claim 16,

And a footprint formed by the heat sink and the adhesive film extending to the side surface of the heat sink is the same as the footprint of the semiconductor package.
The method of claim 17,

And the footprint of the heat sink is the same as the footprint of the semiconductor chip.
The method of claim 18,

And the thickness formed by the heat sink and the adhesive film is about 25 percent to about 40 percent of the thickness of the semiconductor package.