KR102131268B1 - Semiconductor Package - Google Patents

Abstract

A semiconductor package according to an exemplary embodiment of the present disclosure includes a semiconductor chip including a chip pad; A metal frame surrounding the semiconductor chip; A redistribution layer electrically connected to a chip pad of the semiconductor chip; An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And a heat sink having a concave-convex structure formed on the encapsulant.

Description

Semiconductor Package {Semiconductor Package}

The technical idea of the present disclosure relates to a semiconductor package equipped with a heat sink, and more particularly, to a semiconductor package equipped with a heat sink capable of effectively discharging heat generated from the semiconductor chip to the outside.

At the same time that the semiconductor memory storage capacity is increased, the electronic device including the semiconductor memory element is required to be thin and light. Since the high-capacity miniaturized semiconductor package generates a lot of heat from the semiconductor chip located inside the semiconductor package, the heat dissipation characteristics outside the semiconductor package are essential to ensure the operational stability and product reliability of the semiconductor package and electronic devices having the same. to be.

One technical problem to be solved by the technical concept of the present disclosure is to provide a semiconductor package capable of effectively dissipating heat generated in a semiconductor chip.

Another technical problem to be solved by the technical concept of the present disclosure is to provide a semiconductor package capable of visually providing information of a semiconductor chip mounted in a semiconductor package.

In order to achieve the above object, a semiconductor chip including a chip pad in one embodiment of the present disclosure; A metal frame surrounding the semiconductor chip; A redistribution layer electrically connected to a chip pad of the semiconductor chip; An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And a heat sink having an uneven structure formed on the encapsulant.

In exemplary embodiments, the heat sink of the concavo-convex structure of the semiconductor package includes a base portion on the encapsulant; And a plurality of protrusions protruding from the upper surface of the base and spaced apart from each other, wherein the protrusions are spaced from 100 micrometers to 300 micrometers from each other.

In exemplary embodiments, the protrusion of the heat sink of the semiconductor package is characterized by having a convex upper portion.

In exemplary embodiments, the protrusion of the semiconductor package is characterized in that it has a thickness between 40 and 60 percent of the thickness of the heat sink.

In exemplary embodiments, the thickness of the base portion of the semiconductor package and the thickness of the protrusion are the same.

In order to achieve the above object, a semiconductor chip including a chip pad in one embodiment of the present disclosure; A metal frame surrounding the semiconductor chip; A redistribution layer electrically connected to a chip pad of the semiconductor chip; An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And a heat sink formed on the encapsulant, wherein the heat sink comprises: a base portion of the encapsulant; A protruding area including a plurality of protruding parts protruding from the base part; And a marking region provided on the base portion, wherein the marking region on which information of the semiconductor chip is expressed is provided.

In exemplary embodiments, the marking area of the semiconductor package forms a plane, and the marking area is dug by a laser device to form information on the semiconductor chip.

In exemplary embodiments, the plane of the marking area of the semiconductor package is a part of an upper surface of the base.

In exemplary embodiments, the marking area of the semiconductor package protrudes from an upper surface of the base, and an upper surface of the marking area is coplanar with an upper surface of the protrusions of the protruding area.

In exemplary embodiments, the height of the marking region of the semiconductor package protruding from the base and the height of the protruding portion protruding from the base are between 40 and 60 percent of the thickness of the heat sink.

In order to achieve the above object, a semiconductor chip including a chip pad in one embodiment of the present disclosure; A metal frame surrounding the semiconductor chip; A redistribution layer electrically connected to a chip pad of the semiconductor chip; An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And a heat sink formed on an upper portion of the encapsulant, wherein the heat sink includes a base portion on the top of the encapsulant; A first region including a plurality of first protrusions protruding from the base portion; And a second region including a plurality of second protrusions having a height higher than the first protrusions protruding from the base portion, wherein the first region includes a portion of the base portion and a portion of the first protrusion portion to be excavated. It provides a semiconductor package characterized in that the information of the semiconductor chip is marked.

In example embodiments, the height of the first protrusions of the heat sink of the semiconductor package is between 1/4 and 1/2 of the height of the second protrusions.

Through the heat sink mounted in the semiconductor package according to embodiments of the present disclosure, heat generated in the semiconductor chip can be discharged to the outside more quickly to improve heat dissipation performance.

Due to the marking of the heat sink mounted on the semiconductor package according to the embodiments of the present disclosure, information on the semiconductor chip in the semiconductor package may be visually provided.

1 is a cross-sectional view illustrating a basic structure of a semiconductor package according to an embodiment of the present disclosure.
2 is a cross-sectional view illustrating a structure of a semiconductor package according to another embodiment of the present disclosure.
3A and 3B are cross-sectional views illustrating a structure of a heat sink of a semiconductor package according to an embodiment of the present disclosure.
3C is a plan view illustrating a structure of a heat sink of a semiconductor package according to an embodiment of the present disclosure.
4A and 4B are plan views illustrating heat sinks in which information of a semiconductor chip is marked according to an embodiment of the present disclosure.
5 is a plan view illustrating a heat sink in which information of a semiconductor chip is marked according to another embodiment of the present disclosure.
6 is a plan view illustrating a heat sink in which information of a semiconductor chip is marked according to another embodiment of the present disclosure.
7 is a view illustrating one step of a method of manufacturing a semiconductor package for attaching a metal frame on a glass substrate, which is an embodiment of the present disclosure.
8 is a view illustrating one step of a method of manufacturing a semiconductor package mounting a semiconductor chip on a glass substrate, which is an embodiment of the present disclosure.
9 is a view for explaining one step of a method of manufacturing a semiconductor package that covers and seals a semiconductor chip and a metal frame with an encapsulation material according to an embodiment of the present disclosure.
FIG. 10 is a view illustrating one step of a method of manufacturing a semiconductor package in which a heat sink, which is an embodiment of the present disclosure, is attached to a semiconductor package.
11 is a view for explaining one step of a semiconductor package manufacturing method of removing a glass substrate and flipping a semiconductor package according to an embodiment of the present disclosure.
12 is a view illustrating one step of a method of manufacturing a semiconductor package forming a redistribution layer and external connection terminals according to an embodiment of the present disclosure.
13 is a view illustrating a step of a semiconductor package manufacturing method of cutting a plurality of semiconductor packages into individual packages according to an embodiment of the present disclosure.
14 is a block diagram schematically illustrating an electronic system including a semiconductor package, which is an embodiment of the present disclosure.

Hereinafter, preferred embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the embodiments of the inventive concept can be modified in many different forms, and the scope of the inventive concept should not be interpreted as being limited by the embodiments described below. It is preferred that the embodiments of the inventive concept are interpreted as being provided to more fully explain the inventive concept to those skilled in the art. The same sign means the same element. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the concept of the present invention is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from other components. For example, a first component may be referred to as a second component, and a second component may be referred to as a first component without departing from the scope of the inventive concept.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the concept of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the expression "comprises" or "haves" is intended to indicate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, or one or more other features or It should be understood that the presence or addition possibilities of the number, operation, components, parts or combinations thereof are not excluded in advance.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used terms, as defined in the dictionary, should be interpreted as having meanings consistent with what they mean in the context of related technologies, and in excessively formal meanings unless explicitly defined herein. It will be understood that it should not be interpreted.

1 is a cross-sectional view illustrating a basic structure of a semiconductor package 100 according to an embodiment of the present disclosure. The semiconductor package 100 may be a fan-out wafer level package (FOWLP) or a panel level package (PLP).

Referring to FIG. 1, a semiconductor package 100 according to an embodiment of the present disclosure includes a semiconductor chip 101, a metal frame 102, a redistribution layer 103, an encapsulant 104, and an external connection terminal 105. , It may include an adhesive film 106 and the heat sink (107). The semiconductor package 100 may be a semiconductor package having a wafer level package (WLP) structure, or a semiconductor package having a fan-out wafer level package structure.

The total thickness d of the semiconductor package 100 may be from about 0.8 millimeters to about 1.8 millimeters. More specifically, according to an embodiment of the present disclosure, the total thickness d of the semiconductor package 100 may be about 1.1 millimeters to about 1.4 millimeters. However, the semiconductor package 100 of the present disclosure is not limited to the thickness d, and may have more various thicknesses d.

The semiconductor chip 101 illustrated in FIG. 1 may include a plurality of individual devices of various types. For example, the plurality of individual devices may be various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), a system such as a complementary metal-insulator-semiconductor transistor (CMOS transistor), a system large scale (LSI) integration), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, and the like.

In example embodiments, the semiconductor chip 101 may be a memory semiconductor chip. The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), or phase-change random access memory (PRAM), or magneto-resistive random access memory (MRAM). ), a nonvolatile memory semiconductor chip such as Ferroelectric Random Access Memory (FeRAM) or Resistive Random Access Memory (RRAM).

Alternatively, in example embodiments, the semiconductor chip 101 may be a logic chip. For example, the semiconductor chip 101 may be a central processor unit (CPU), a micro processor unit (MPU), a graphical processor unit (GPU), or an application processor (AP).

The semiconductor package 100 of FIG. 1 is illustrated as including one semiconductor chip, but the semiconductor package 100 may include two or more semiconductor chips. The two or more semiconductor chips included in the semiconductor package 100 may be the same type of semiconductor chip or a different type of semiconductor chip. In one embodiment, the semiconductor package 100 may be a system in package (SIP) in which semiconductor chips of different types are electrically connected to each other to operate as a system.

The semiconductor chip 101 may include a lower surface 111 and an upper surface 112 facing the lower surface 111. The semiconductor chip 101 may include a chip pad 113 on the lower surface 111. The chip pad 113 may be electrically connected to a plurality of individual elements of various types formed on the semiconductor chip 101. In addition, although not shown in FIG. 1, the semiconductor chip 101 may include a passivation layer covering the lower surface 111.

The semiconductor package 100 may include a metal frame 102. The metal frame 102 may be located on the redistribution layer 103 to include a cavity therein. The semiconductor chip 101 is positioned in the inner cavity of the metal frame 102, and the semiconductor chip 101 may be surrounded by the metal frame 102.

The metal frame 102 may be made of various metal-based materials. For example, the metal frame 102 is aluminum (Al) having a thermal conductivity of about 200 W/m·K, magnesium (Mg) having a thermal conductivity of about 150 W/m·K, and about 380 W/m·K. Metal materials such as copper (Cu) having thermal conductivity, nickel (Ni) having a thermal conductivity of about 90 W/m·K, and silver (Ag) having a thermal conductivity of about 410 W/m·K may be included.

Heat generated from the side surface of the semiconductor chip 101 may be transferred to the metal frame 102 and discharged to the outside. As illustrated in FIG. 1, the outer wall 102a of the metal frame 102 may be exposed on the same side as the side surface of the semiconductor package 100 and exposed to the outside. Therefore, the heat dissipation performance of the semiconductor package 100 may be improved by the metal frame 102.

The semiconductor package 100 may include an encapsulant 104. The encapsulant 104 may surround and protect the semiconductor chip 101. In addition, the encapsulant 104 is a space formed between the semiconductor chip 101 and the metal frame 102 to prevent electrical short circuit between the semiconductor chip 101 and the metal frame 102 as described above. Can be filled in. In addition, the encapsulant 104 may cover at least a portion of the semiconductor chip 101 and at least a portion of the metal frame 102. Therefore, the semiconductor chip 101 and the metal frame 102 may be integrated by the encapsulant 104 to contact the upper surface of the redistribution layer 103, which will be described later.

The encapsulant 104 may be formed of, for example, a silicone-based material, a thermosetting material, a thermoplastic material, a UV treatment material, etc., and may be formed of a polymer such as resin. For example, it may be formed of an epoxy molding compound (EMC).

In example embodiments, the encapsulant 104 may cover side and top surfaces 112 of the semiconductor chip 101 and side and top surfaces of the metal frame 102. The heights formed by the semiconductor chip 101 and the metal frame 102 are substantially the same, so that the top surface of the semiconductor chip 101 and the top surface of the metal frame 102 may be on the same plane. At this time, the distance (e) between the top surface of the semiconductor chip 101 and the metal frame 102 and the top surface of the encapsulant 104 may be about 1 micrometer to about 10 micrometers.

The semiconductor package 100 may include an adhesive film 106. The adhesive film 106 may contact the upper surface 112 of the semiconductor chip 101 or the upper surface of the encapsulant 104. The adhesive film 106 may include an epoxy resin having excellent adhesion to the encapsulant 104 and the semiconductor chip 101. In addition, a filler having excellent thermal conductivity, for example, silver, aluminum, silicon dioxide, aluminum nitride, boron nitride, and the like may be included, and aluminum oxide having thermal conductivity may be included to maintain rigidity. The adhesive film 106 may have adhesive properties on its own, and may also be provided by bonding with a separate thermal conductive adhesive tape. The adhesive tape may be a double-sided adhesive tape. The adhesive film 106 is interposed between the encapsulant 104 and the heat sink 107 to fix the heat sink 107. The thickness of the adhesive film 106 formed on the semiconductor package 100 may be about 5 micrometers to about 20 micrometers, and more specifically about 10 micrometers to about 14 micrometers.

The semiconductor package 100 may include a redistribution layer 103. The redistribution layer 103 may be formed on the lower surface 111 of the semiconductor chip 101 to electrically connect the chip pad 113 and the external connection terminal 105 of the semiconductor chip 101. The semiconductor package 100 may form an external connection terminal 105 in an area outside the footprint of the lower surface 111 of the semiconductor chip 101 through the redistribution layer 103. Through the redistribution layer 103, the efficient arrangement of the external connection terminal 105 in the semiconductor package 100 may be possible.

The redistribution layer 103 may include a wiring pattern 103a and an insulating pattern 103b. The wiring pattern 103a may be electrically connected to the chip pad 113 formed on the lower surface 111 of the semiconductor chip 101, and an electrical connection path for electrically connecting the chip pad 113 to an external device. Can provide. The insulating pattern 103b serves to protect a wiring pattern electrically connected to the chip pad 113 from external impact and to prevent a short circuit. The insulating pattern 103b may include, for example, a photosensitive material such as polyimide or epoxy. However, the present invention is not limited thereto, and may be made of a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

The semiconductor package may include an external connection terminal 105. The external connection terminal 105 is located on the lower surface of the redistribution layer 103 and can be electrically connected to the wiring pattern of the redistribution layer 103. The semiconductor package 100 may be electrically connected to an external device such as a system board or a main board by the external connection terminal 105. The external connection terminal 105 may include a solder ball, as shown in FIG. 1. The solder ball may include at least one of tin, silver, copper, and aluminum. In addition, the shape of the solder ball may be a ball shape shown in FIG. 1, but is not limited thereto, and may have various shapes such as a cylinder, a polygonal column, and a polyhedron.

The semiconductor package 100 may include a heat sink 107. The heat sink 107 may be located on the adhesive film 106 and mounted on the semiconductor package 100. The heat sink 107 may quickly dissipate heat generated from the semiconductor chip 101 in the semiconductor package 100 to the outside.

The heat sink 107 mounted on the semiconductor package 100 may include a metal-based material having various thermal conductivity, a ceramic-based material, a carbon-based material, and a polymer-based material.

More specifically, the heat sink 107 of the metal-based material includes aluminum (Al) having a thermal conductivity of about 200 W/m·K, magnesium (Mg) having a thermal conductivity of about 150 W/m·K, and about 380 W/m· Metal materials such as copper (Cu) with a thermal conductivity of K, nickel (Ni) with a thermal conductivity of about 90 W/m·K, and silver (Ag) with a thermal conductivity of about 410 W/m·K have.

The ceramic-based heat sink 107 is boron nitride (BN) having a thermal conductivity of about 1800 W/m·K, aluminum nitride (AlN) having a thermal conductivity of about 320 W/m·K, about 30 W/m· Ceramic materials such as aluminum oxide (Al2O3) having a thermal conductivity of K, silicon carbide (SiC) having a thermal conductivity of about 480 W/m·K, and beryllium oxide (BeO) having a thermal conductivity of about 270 W/m·K It may include.

The heat sink 107 of the carbon-based material is diamond having a thermal conductivity of about 2500W/m·K, carbon fiber having a thermal conductivity of about 100W/m·K, about 5W/m·K to about 1950W/m· Carbon-based materials such as graphite with a thermal conductivity of K, carbon nanotubes with a thermal conductivity of about 1.5 W/m·K to about 3500 W/m·K, and graphene with a thermal conductivity of about 5000 W/m·K It can contain.

The heat sink 107 of the polymer-based material may include a polymer-based material such as polyethylene having an ultra-high molecular weight having a thermal conductivity of about 45 W/m·K to about 100 W/m·K.

However, the heat sink 107 is not limited to the above-described metal-based material, cerium-based material, carbon-based material, and polymer-based material, and may include a combination of the above materials or other materials not shown.

The heat sink 107 mounted on the semiconductor package 100 may be formed in various thicknesses. In one embodiment of the present disclosure, the thickness f of the heat sink 107 may occupy about 25% to about 40% of the thickness of the semiconductor package. In one embodiment of the present disclosure, the thickness of the semiconductor package 100 may be from about 1.1 millimeters to about 1.4 millimeters, so that the thickness f of the heat sink 107 is from about 280 micrometers to about 560 micrometers. Can. More specifically, the thickness f of the heat sink 107 of the semiconductor package 100 may be about 400 micrometers.

The heat sink 107 mounted on the semiconductor package 100 may have an uneven structure as illustrated in FIG. 1. Through the shape of the uneven structure, the heat sink 107 may have an increased cross-sectional area in contact with external air. Therefore, the semiconductor package 100 including the heat sink 107 of the present disclosure may have a better heat dissipation effect than a semiconductor package equipped with a heat sink without an uneven structure. The shape of the uneven structure of the heat sink 107 and the method of forming the uneven structure of the heat sink 107 will be described later in detail with reference to FIGS. 3A to 3C.

In addition, information on the semiconductor chip 101 may be marked on some regions of the heat sink 107 of the semiconductor package 100. The marking of the heat sink 107 will be described later in detail with reference to FIGS. 4A to 6.

The semiconductor package 100 may quickly release heat generated from the semiconductor chip 101 to the outside by the metal frame 102 and the heat sink 107 of the uneven structure.

More specifically, heat generated in the semiconductor chip 101 may be emitted to the top surface 112 and the side surface (not shown) of the semiconductor chip 101. The heat emitted to the upper surface 112 of the semiconductor chip 101 is sequentially passed from the upper surface 112 of the semiconductor chip 101 through the encapsulant 104, the adhesive film 106, and the heat sink 107 to the outside. Can be released. In addition, heat emitted to the side surface (not shown) of the semiconductor chip 101 may be discharged to the outside through the encapsulant 104 and the metal frame 102 sequentially from the side surface of the semiconductor chip 101. At this time, the metal frame 102 and the heat sink 107 of the semiconductor package 100 may include a material having a relatively high thermal conductivity as described above, and also the surface of the heat sink 107 And the outer wall (102a) of the metal frame 102 may be exposed to the outside, the heat generated in the semiconductor chip 101 can be discharged to the outside more quickly.

2 is a cross-sectional view illustrating the structure of the semiconductor package 200 according to another embodiment of the present disclosure.

Referring to FIG. 2, the semiconductor package 200 includes a semiconductor chip 101, a metal frame 102, a redistribution layer 103, an encapsulant 104, an external connection terminal 105, and an adhesive film 106. And it may include a heat sink (107). Description of the semiconductor chip 101, the metal frame 102, the redistribution layer 103, the external connection terminal 105, the adhesive film 106, and the heat sink 107 is shown in Figure 1 With reference to the same as described above.

The encapsulant 104 of the semiconductor package 200 covers the side surface of the semiconductor chip 101 and the inner wall of the metal frame 102, and the top surface 112 and the metal frame 102 of the semiconductor chip 101 are covered. ) Can be exposed from the encapsulant 104. As the upper surface 112 of the semiconductor chip 101 and the upper surface of the metal frame 102 are exposed from the encapsulant 104, the overall thickness d′ of the semiconductor package 200 is the semiconductor package of FIG. 1. The semiconductor package 200 may be thinner and lighter than the total thickness d of 100.

In addition, heat generated from the upper surface 112 of the semiconductor chip 101 of the semiconductor package 200 is the adhesive film 106 and the upper surface of the adhesive film 106 positioned on the upper surface 112 of the semiconductor chip 101. It may be discharged to the outside by sequentially passing through the heat sink 107 located in. Therefore, the heat generated in the semiconductor chip 101 does not pass through the encapsulant 104 having a relatively low thermal conductivity, so that the heat transfer resistance in the heat transfer path may be reduced, and accordingly, the heat dissipation performance of the semiconductor package 200. This can be improved.

3A and 3B are cross-sectional views illustrating a structure of a heat sink of a semiconductor package according to an embodiment of the present disclosure. 3C is a plan view illustrating the structure of the heat sink illustrated in FIGS. 3A and 3B.

3A to 3C, heat sinks 300a and 300b of a semiconductor package according to embodiments of the present disclosure may have an uneven structure. The dictionary meaning of the irregularities is concave and convex. The heat sinks 300a and 300b may include a base 301 and a plurality of protrusions 302a and 302b. More specifically, the heat sinks 300a and 300b may include a plurality of protrusions 302a and 302b formed to protrude from the upper surface of the base portion 301 having the flat plate shape. Due to the shape in which the plurality of protrusions 302a and 302b are spaced apart at a predetermined distance and repeatedly arranged, the heat sinks 300a and 300b are repeatedly concave and convex in the upper surface of the base 301. It can have the shape of an uneven structure.

The bottom surface of the base portion 301 of the heat sinks 300a and 300b may be located on the top surface of the encapsulant of the semiconductor package and fixed by an adhesive film. The thickness f1 of the base 301 may occupy about 40% to about 60% of the total thickness f of the heat sinks 300a and 300b. In one embodiment of the present disclosure, the thickness f1 of the base 301 of the heat sinks 300a and 300b may be half of the total thickness f of the heat sinks 300a and 300b. Accordingly, when the total thickness f of the heat sinks 300a and 300b is about 400 micrometers, the thickness f1 of the base 301 of the heat sinks 300a and 300b may be about 200 micrometers. have.

The protrusions 302a and 302b of the heat sinks 300a and 300b may be formed to be spaced apart from other adjacent protrusions 302a and 302b by a predetermined distance (g). In one embodiment of the present disclosure, the separation distance g between the protrusions 302a and 302b may be about 100 micrometers to about 300 micrometers. More specifically, the separation distance g between the protrusions 302a and 302b may be about 200 micrometers.

The width e formed by the one protrusion 302a, 302b of the heat sinks 300a, 300b may be about 100 micrometers to about 300 micrometers. More specifically, the width e formed by the protrusions 302a and 302b may be about 200 micrometers.

The thickness f2 formed by the one protrusion 302a, 302b of the heat sinks 300a, 300b is about 40% to about 60% of the total thickness f of the heat sinks 300a, 300b. Can be occupied. In one embodiment of the present disclosure, the thickness f2 of the protrusions 302a and 302b of the heat sinks 300a and 300b may be half of the total thickness f of the heat sinks 300a and 300b. Therefore, when the total thickness f of the heat sinks 300a and 300b is about 400 micrometers, the thickness f2 of the one protrusions 302a and 302b of the heat sinks 300a and 300b is about 200 microns. It can be a meter.

The total thickness f of the heat sinks 300a, 300b may be equal to the sum (f=f1+f2) of the thickness f1 of the base 301 and the thickness f2 of the protrusions 302a, 302b. . In one embodiment of the present disclosure, when the total thickness f of the heat sinks 300a and 300b is about 400 micrometers, the thickness f1 of the base 301 is that of the heat sinks 300a and 300b. It may be about 160 micrometers, which is about 40 percent of the total thickness f, wherein the thickness f2 of the protrusions 302a, 302b is about 60 of the thickness f of the heat sinks 300a, 300b. The percentage may be about 240 micrometers. Further, when the thickness f1 of the base 301 is about 240 micrometers, which is about 60 percent of the thickness f of the heat sinks 300a, 300b, the thickness f2 of the protrusions 302a, 302b ) May be about 160 micrometers, which is about 40 percent of the thickness f of the heat sinks 300a and 300b. The thickness f1 of the base 301 of the heat sinks 300a and 300b of the present disclosure and the thickness f2 of the protrusions 302a and 302b may be substantially the same, and in one embodiment, about 200 microns each It can be a meter.

Referring to FIG. 3A, the protrusion 302a of the heat sink 300a may include a plane at the top, and when referring to FIG. 3B, the protrusion 302b of the heat sink 300b is convex from the top. It may include a curved surface. The shape of the protruding portion 302b of the heat sinks 300a and 300b is not limited to the shapes of FIGS. 3A and 3B and may have more various shapes.

The heat sink 300a of FIG. 3A may have a shape including the plurality of protrusions 302a through a process of cutting a portion of a rectangular parallelepiped heat sink having a predetermined thickness f through a cutting device. have. The cutting blade of the cutting device may have a spaced distance g between the plurality of protrusions 302a as a cutting width, and may also have a thickness f2 of the protrusion 302a as a cutting depth. The cutting device may cut a portion of the heat sink while moving along the cutting lane (L) shown in FIG. 3C, and accordingly, the heat sink 300a of FIG. 3A may include the plurality of protrusions described above. 302a.

The heat sink 300b of FIG. 3B has the shape of a convex curved surface from the top through an additional cutting process to smoothly cut the upper portion of the formed protrusion 302a after forming the protrusions 302a through the above-described cutting device. It may include the projections (302b) of Figure 3b.

Also, the heat sinks 300a and 300b illustrated in FIGS. 3A and 3B may be formed through an injection molding process other than the above-described cutting process.

More specifically, the material to be formed of the heat sinks 300a and 300b may be injected into an injection molding heating chamber. The material of the heat sinks 300a and 300b injected into the heating chamber may be melted due to the high temperature of the heating chamber. The molten material may be injected into an injection molding machine including an injection space in the shape of the heat sinks 300a and 300b of FIGS. 3A and 3B. The injected material in the molten state may fill the injection space of the shape of the heat sink (300a, 300b). Thereafter, the injection molding machine may cool the molten material in the injection space to finally form the heat sinks 300a and 300b shown in FIGS. 3A and 3B. When the injection molding process is used, the shape of the uneven structure of the heat sinks 300a and 300b is not limited to those shown in FIGS. 3a and 3b, and can be made into more various shapes according to the shape of the injection space of the injection molding machine. Can.

The heat sinks 300a and 300b of FIGS. 3A to 3C are not limited to the above-described cutting process and injection molding process, and may form an uneven structure through various processes. In one embodiment, the uneven structure of the heat sinks 300a and 300b may be formed through a chemical reaction. In addition, in one embodiment, the heat sinks 300a and 300b may form an uneven structure through a process of physically bonding a plurality of protrusions 301a and 301b separately formed to the base 301. In this case, materials of the protrusions 301a and 301b and the base 301 of the heat sinks 300a and 300b may be different.

The heat dissipation performance of the semiconductor packages may be improved due to the shape of the uneven structure of the heat sinks 300a and 300b. More specifically, by forming the concave-convex structure, the heat sinks 300a and 300b may have a larger surface area that contacts the outside air. Accordingly, the semiconductor package on which the heat sinks 300a and 300b are mounted can more quickly dissipate heat emitted from the semiconductor chip in the semiconductor package.

4A and 4B are plan views illustrating heat sinks 400a and 400b, respectively, of which information of a semiconductor chip is marked according to an embodiment of the present disclosure.

4A and 4B, the heat sinks 400a and 400b are positioned on the base 404 and the base 404 to be positioned on the top surface of the encapsulant, thereby marking information on the semiconductor chip. It may include a marking area (402a, 402b), and a protrusion area 403 including a plurality of protrusions 401 protruding from the base 404.

As shown in FIGS. 4A and 4B, protrusions 401 may not be formed in the marking regions 402a and 402b where the information of the semiconductor chip is expressed. In other words, the heat sinks 400a and 400b do not include an uneven structure in one portion, and may include a flat plane. Therefore, the marking regions 402a and 402b may be formed at a height lower than the upper surface of the protrusion 401. In one embodiment, the marking area may be formed on a portion of the top surface of the base 404.

The heat sink 400a illustrated in FIG. 4A may include a marking area 402a in a plane in which the protrusions 401 are not formed at the upper left, and the marking area 402a is mounted in the semiconductor package. The information of the semiconductor chip can be marked. In addition, the heat sink 400 illustrated in FIG. 4B may include a marking area 402b of a plane in which the protrusions 401 are not formed at the center, and the semiconductor chip information is also provided in the marking area 402b. Can be marked. The marking regions 402a and 402b on which the protrusions 401 are not formed are not limited to the positions illustrated in FIGS. 4A and 4B and may be formed at various positions of the heat sink.

In the marking areas 402a and 402b of the semiconductor package, information on the semiconductor chip such as the type, number, performance, name and/or logo of the manufacturing company, manufacturing date, and serial number may be marked.

An ink marking technique or a laser marking technique may be used for marking semiconductor information in the marking regions 402a and 402b.

More specifically, information on a semiconductor chip may be marked using a pad printing technique as a technique of ink marking in the marking regions 402a and 402b of the heat sinks 400a and 400b. . The pad printing technique may mark semiconductor information by pushing an ink-filled pallet with a pad of silicon rubber on which an embossed or negative pattern is formed to contact the ink in the pallet to the surfaces of the marking areas 402a and 402b. The pad printing technique can mark the information of the semiconductor package at a low cost, and since the pad of the silicone rubber is elastic, it can cleanly mark the semiconductor information even on the surface of an uneven heat sink.

In addition, information on the semiconductor chip may be marked on the marking regions 402a and 402b of the heat sinks 400a and 400b by a laser marking technique. The laser marking technique focuses a part of the marking regions 402a and 402b by focusing laser light emitted from the laser apparatus to the marking regions 402a and 402b of the heat sinks 400a and 400b using a laser apparatus. It can be digged into letters or numbers to express information on semiconductor chips. In addition, the laser device may control the intensity of laser light by controlling the intensity of power supplied to the laser device, and accordingly, letters and numbers formed in the marking areas 402a and 402b of the heat sinks 400a and 400b. You can adjust the thickness of the.

Conventional CO2 laser devices, YAG laser devices, and diode laser devices may be used as the laser marking technique. The CO2 laser device may include nitrogen (N2), carbon dioxide (CO2), and helium (He) inside a resonator. When high-frequency energy is transmitted to the interior of the resonator, the nitrogen molecule stimulates the carbon dioxide molecule, and at this time, the stimulated carbon dioxide molecule may be excited. The carbon dioxide molecule in the excited state emits energy to return to the ground state, and may emit infrared laser light having a wavelength of about 9 micrometers to about 11 micrometers.

The YAG laser device may use YAG (Yttrium Aluminum Garnet) crystal as a laser medium. The YAG crystal may be composed of yttrium (Yd) and aluminum (Al), and the crystal structure may have a structure similar to that of garnet. The YAG laser device may emit laser light by adding various rare elements such as neodymium (Nd) and ytterbium (Yb) to the YAG crystal.

In the diode laser device, when a forward bias is applied to the diode, electrons and holes may be injected into the P layer of the diode. The electrons may transition to the region of the valence band, and emit laser light when the electrons return to the ground state.

The laser devices used for marking the semiconductor chip information of the marking regions 402a and 402b of the heat sinks 400a and 400b of the present disclosure include the above-described CO2 laser device, YAG laser device, and diode laser device. It is not limited and may further include various laser devices.

5 is a plan view illustrating a heat sink 500 in which information of a semiconductor package is marked according to another embodiment of the present disclosure.

Referring to FIG. 5, the heat sink 500 is located on the base 503 and a protruding area 504 including a plurality of protrusions 501 protruding from the base 503 and the base 503. Accordingly, a marking area 502 in which information of the semiconductor chip is expressed may be included. The technical features of the protrusion 501 may be substantially the same as the protrusions 301a and 301b of FIGS. 3A to 3C, so a description thereof will be omitted.

The marking area 502 may be formed to protrude from the top surface of the base 503 of the heat sink 500. More specifically, the marking area 502 may protrude from the upper surface of the base 503, and the upper surface of the protruding marking area 502 may have a planar shape. The width of the upper surface of the marking area 502 may be greater than the width of the upper surface of the one protrusion 501, and may be smaller than the footprint of the heat sink 500. In one embodiment, the marking area 502 of the heat sink 500 may occupy about 10 percent to about 80 percent in the footprint of the heat sink 500.

In addition, the height formed by the marking area 502 protruding from the base portion may be substantially the same as the height of the protruding portion 501. Accordingly, the top surface of the marking area 502 may be on the same plane as the top surface of the protrusions 501 of the protrusion area 504. The height at which the marking area 502 protrudes from the base 503 and the height at which the protrusions 501 protrude from the base 503 are between about 40 percent to about 60 percent of the total thickness of the heat sink 500. It can be characterized by being.

The semiconductor chip information may be expressed on the upper surface of the marking area 502 by the above-described ink marking technique or laser marking technique.

The heat sink 500 may include a plurality of protrusions 501 by cutting a portion of a rectangular parallelepiped heat sink having a predetermined thickness through a cutting device, and in the remaining uncut portion, the marking area ( 502).

In FIG. 5, although the marking area 502 is illustrated as being formed on the upper left of the heat sink 500, it is not limited to the position and may be formed at various positions of the heat sink 500.

The heat sink 500 of FIG. 5 may have a larger cross-sectional area in contact with external air than the heat sinks 400a and 400b of FIGS. 4A and 4B due to the shape of the marking area 502 formed to protrude. Can be better.

6 is a plan view illustrating a heat sink 600 in which information of a semiconductor package is marked according to another embodiment of the present disclosure.

The heat sink 600 includes a base 602 to be located on an upper surface of the encapsulant of the semiconductor package, a first region 603 including first protrusions 601a protruding from the base, and the protrusion protruding from the base A second region 604 including second protrusions 601b may be included. The first protrusion 601a, the second protrusion 601b, and the base 602 are substantially identical to the technical idea of the protrusions 302a, 302b and the base 301 of the heat sinks 300a, 300b shown in FIG. 3C. It can be the same. However, the thicknesses of the first and second protrusions 601a and 601b formed in the heat sink 600 are protrusions 302a and 302b of the heat sinks 300a and 300b shown in FIG. 3A, as will be described later. It may be different from the thickness (f2).

As illustrated in FIG. 6, the heat sink 600 may include first protrusions 601a protruding on the base 602 in the first area 603, and the second area ( At 604, the second protrusions 601b protruding on the base 602 may be included.

The first region 603 may include consecutive letters and numbers representing information of the semiconductor package on the base 602 and the top surfaces of the first protrusions 601a. More specifically, information of the semiconductor chip may be expressed on an upper surface of the base portion 602 and an upper surface of the first protrusion 601a positioned under the first region 603. The information of the semiconductor chip may be marked by dividing a part of the base 602 and a part of the first protrusion 601a by a laser device, and also a part of the base 602 and the first protrusion 601a ), the ink may be painted and marked.

In order to include consecutive letters and numbers from the top surface of the first protrusions 601a in the first region 603 and the base 602, the thickness formed by the first protrusions 601 is smaller. good. This means that the smaller the thickness of the first protrusions 601, the smaller the change in the height of the point where the laser light is condensed in the case of laser marking, so that the letters and numbers engraved can be arranged, and in the case of ink marking, This is because the change in length that the pad of the silicone rubber has to be stretched by elasticity may be small.

Accordingly, the height formed by the first protrusions 601a in the first area 603 of the heat sink 600 of the present disclosure is the second area 604 in which the marking area 603 is not formed. 2 The protrusions 601b may be substantially smaller than the height formed. In one embodiment, the height formed by the first protrusions 601a may be between about 1/4 to about 1/2 of the height formed by the second protrusions 601b. In one embodiment of the present disclosure, the total thickness of the heat sink 600 is about 400 micrometers, the thickness of the base portion 602 is about 200 micrometers, and the height of the second protrusions 601b is about 200 micrometers. In this case, the height of the first protrusions 601a may be about 2 to about 4 times smaller than the height of the second protrusions 601b. Accordingly, the height of the first protrusions 601a may be about 50 micrometers to about 100 micrometers.

Due to the low height of the first protrusions 601a formed in the first region 603 of the heat sink 600, the heat sink 600 is the base 602 of the first region 603. And continuous letters and numbers formed on the upper surfaces of the first protrusions 601a to represent information of the semiconductor package. In the case of laser marking, a change in height of a point at which the laser light is collected in the first region 603 may be about 50 micrometers to about 100 micrometers. Therefore, the letters and numbers in the first region 603 may be continuously marked in an ordered shape without separately controlling the height of the condensing point of the laser light. In addition, even when controlling the height of the condensing point of the laser light, only position control of about 50 micrometers to about 100 micrometers of the laser device may be required, so energy consumption may be small in driving the laser device, and the laser device is driven. The control time of can be reduced.

In the case of ink marking, since the change in length of the pad of the silicone rubber to be stretched by elasticity may be small, from about 50 micrometers to about 100 micrometers, the first protrusions 601a of the first region 603 Letters and numbers representing semiconductor information may be marked in a more ordered shape on the upper surface and the base portion 602.

7 to 13 are diagrams for describing a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

7 illustrates one step of a method of manufacturing a semiconductor package attaching a metal frame on a glass substrate, which is an embodiment of the present disclosure. Referring to FIG. 7, a method of manufacturing a semiconductor package according to an embodiment of the technical spirit of the present disclosure may include attaching a metal frame 102 to an upper surface of a glass substrate 701. An adhesive layer (not shown) may be formed on the top surface of the glass substrate 701. The metal frame 102 may be physically attached to the top surface of the glass substrate 701 by the adhesive layer (not shown).

8 illustrates one step of a method for manufacturing a semiconductor package mounting a semiconductor chip on a glass substrate, which is an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the technical spirit of the present disclosure may include mounting the semiconductor chip 101 on the glass substrate 701. The semiconductor chip 101 may be placed in the cavity of the metal frame 102 attached to the glass substrate 701 and mounted on the glass substrate 701.

9 illustrates a step of a method of manufacturing a semiconductor package by sealing the semiconductor chip 101 and the metal frame 102 with the encapsulant 104, which is an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the technical spirit of the present disclosure may include sealing the encapsulant 104 by covering the semiconductor chip 101 and the metal frame 102. The encapsulant 104 may fill the space formed spaced apart between the semiconductor chip 101 and the inner wall of the metal frame 102 to integrate the semiconductor chip 101 and the metal frame 102. In addition, the encapsulant 104 may cover the upper surfaces of the semiconductor chip 101 and the metal frame 102.

Although not illustrated in FIG. 9, an embodiment of the present disclosure grinds the upper portions of the encapsulant 104 covering the upper surfaces of the semiconductor chip 101 and the metal frame 102 to grind the semiconductor chip 101. Alternatively, a process of exposing the top surface of the metal frame 102 may be further included.

10 illustrates one step of a method of manufacturing a semiconductor package in which the heat sink 107, which is an embodiment of the present disclosure, is attached to the semiconductor package. A method of manufacturing a semiconductor package according to an embodiment of the technical spirit of the present disclosure may include attaching a heat sink 107 on the semiconductor package. The heat sink 107 may have a shape of an uneven structure as described above, and the heat sink 107 of the uneven structure may include heat sinks described with reference to FIGS. 3A to 6 as an embodiment. . Accordingly, the heat sink 107 may include a marking area in which letters and numbers representing information of the semiconductor package described above are formed.

The heat sink 107 may be attached to the top surface of the semiconductor chip 101 or the top surface of the encapsulant 104. The method of arranging the heat sink 107 in close contact with the upper surface of the semiconductor chip 101 may include a thermal compression method. The thermal compression method is to apply heat and pressure to the adhesive film positioned below the heat sink 107 using a compactor. Through the thermal compression method, the adhesive film can stably attach the heat sink 107 to the upper surfaces of the semiconductor chip 101 and the encapsulant 104.

11 illustrates one step of a method of manufacturing a semiconductor package that removes the glass substrate 701 and flips the semiconductor package according to an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the technical spirit of the present disclosure may include separating the glass substrate 701 and overturning the semiconductor package.

12 illustrates one step of a method of manufacturing a semiconductor package forming a redistribution layer and external connection terminals according to an embodiment of the present disclosure. A method of manufacturing a semiconductor package according to an embodiment of the technical spirit of the present disclosure may include forming a redistribution layer 103. The redistribution layer 103 may include a wiring pattern 1201 and an insulating pattern 1202. In an exemplary embodiment of the present disclosure, the insulating pattern 1202 may include a non-photosensitive material, and after the insulating pattern 1202 is formed on the bottom surface of the semiconductor chip 101, the insulating pattern 1202 is a semiconductor It may be partially removed to expose the chip pad 113 of the chip 101. After the insulating pattern 1202 is formed, the wiring pattern 1201 may be electrically connected to the chip pad 113 exposed by the opening of the insulating pattern 1202. The wiring pattern 1201 may be formed by plating, electroless plating, electroplating, or a combination thereof, and may be formed on the insulating pattern 1202 through a plating process. When the wiring pattern 1201 is formed, the insulating pattern 1202 may be formed on the wiring pattern 1201 once again. At this time, a part of the wiring pattern 1201 may be partially exposed to be connected to the external connection terminal 105.

Also, referring to FIG. 12, a method of manufacturing a semiconductor package according to an embodiment of the technical spirit of the present disclosure may include attaching an external connection terminal 105. The external connection terminal 105 may be a solder ball. The external connection terminal 105 may be attached to the exposed wiring pattern 1201 through a soldering process.

13 illustrates a step of a semiconductor package manufacturing method of cutting a plurality of semiconductor packages into individual packages according to an embodiment of the present disclosure. In the process of cutting the plurality of semiconductor packages into individual packages, the redistribution layer 103, the metal frame 102, the encapsulant 104, and the heat sink 107 of the semiconductor package are sequentially used using a cutting blade. Can cut

14 is a block diagram schematically illustrating an electronic system 1400 including a semiconductor package, which is an embodiment of the present disclosure. The electronic system 1400 may include at least one of semiconductor packages of various embodiments of the technical spirit of the present disclosure. The electronic system 1400 may be included in a mobile device or computer. For example, the electronic system 1400 may include a memory system 1401, a microprocessor 1402, a RAM 1403, and a user interface 1404 performing data communication.

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although the embodiments have been described using specific terminology in this specification, they are only used for the purpose of illustrating the technical spirit of the present disclosure and are not used to limit the scope of the present disclosure as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (12)

delete delete delete delete delete A semiconductor chip including a chip pad;
A metal frame surrounding the semiconductor chip;
A redistribution layer electrically connected to a chip pad of the semiconductor chip;
An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And
Includes; heat sink formed on the encapsulant;
The heat sink
A base portion of the top of the encapsulant;
A protruding area including a plurality of protruding parts protruding from the base part; And
And a marking area provided on the base portion, wherein the marking area on which information of the semiconductor chip is expressed is included.
The marking area protrudes from the upper surface of the base, and the upper surface of the marking area forms a plane,
The upper surface of the marking area is a semiconductor package, characterized in that on the same plane as the upper surface of the protrusions of the projection area. The method of claim 6,
A semiconductor package, characterized in that the semiconductor chip is formed in the marking area by dipping the plane by a laser device. delete delete The method of claim 6,
The height of the marking region protruding from the base portion and the height of the protruding portion protruding from the base portion is a semiconductor package, characterized in that between 40 and 60 percent of the thickness of the heat sink. A semiconductor chip including a chip pad;
A metal frame surrounding the semiconductor chip;
A redistribution layer electrically connected to a chip pad of the semiconductor chip;
An encapsulant covering at least a portion of the semiconductor chip and at least a portion of the metal frame; And
Includes; heat sink formed on the top of the encapsulant,
The heat sink
A base portion of the top of the encapsulant;
A first region including a plurality of first protrusions protruding from the base portion; And
It includes; a second region including a plurality of second protrusions of a height greater than the first protrusions protruding from the base;
The height of the first protrusions is 50 micrometers to 100 micrometers,
A semiconductor package according to claim 1, wherein a portion of the base portion and a portion of the first protrusion are cut into the first region to mark information of the semiconductor chip. The method of claim 11,
The semiconductor package, characterized in that the height of the first protrusions of the heat sink is between 1/4 and 1/2 of the height of the second protrusions.

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