JP6797234B2 - Semiconductor package structure and its manufacturing method - Google Patents

Semiconductor package structure and its manufacturing method Download PDF

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JP6797234B2
JP6797234B2 JP2019067076A JP2019067076A JP6797234B2 JP 6797234 B2 JP6797234 B2 JP 6797234B2 JP 2019067076 A JP2019067076 A JP 2019067076A JP 2019067076 A JP2019067076 A JP 2019067076A JP 6797234 B2 JP6797234 B2 JP 6797234B2
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spacer plate
semiconductor package
electronic circuit
package structure
circuit board
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JP2020096153A (en
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業展 邱
業展 邱
坤基 徐
坤基 徐
柏樫 傅
柏樫 傅
榮棋 陳
榮棋 陳
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力成科技股▲分▼有限公司
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/181—Encapsulation
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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Description

本発明は、半導体パッケージ構造体及びその製造方法に関し、特に反り及び層間剥離を抑えることができる半導体パッケージ構造体及びその製造方法に関する。 The present invention relates to a semiconductor package structure and a method for manufacturing the same, and more particularly to a semiconductor package structure capable of suppressing warpage and delamination and a method for manufacturing the same.

薄型化半導体パッケージ構造体は、パッケージング過程で反りが発生しやすいことが知られている。これに対し、図８に示すように、電子回路基板７０と、電子回路基板７０上に設置されるスペーサ板７１と、スペーサ板７１上に設置される複数のチップ７２と、スペーサ板７１及びチップ７２を覆う封止体７３とを備える半導体パッケージ構造体が提案されている。スペーサ板７１の設置によって半導体パッケージ構造体の構造強度が向上されるため、パッケージング過程での反りを抑えることが可能になる。 It is known that a thin semiconductor package structure is likely to warp during the packaging process. On the other hand, as shown in FIG. 8, the electronic circuit board 70, the spacer plate 71 installed on the electronic circuit board 70, the plurality of chips 72 installed on the spacer plate 71, the spacer plate 71, and the chips A semiconductor package structure including a sealing body 73 covering 72 has been proposed. Since the structural strength of the semiconductor package structure is improved by installing the spacer plate 71, it is possible to suppress warpage in the packaging process.

ところで、スペーサ板７１を備えたこのような半導体パッケージ構造体１は、高温、高湿での信頼性試験においてスペーサ板７１及び封止体７３の層間剥離が発生することで、故障することがある。その原因は、スペーサ板７１として、ウェハをそのまま切断して形成されたものが使用されていることにあると考えられている。ウェハから作製されたスペーサ板７１は平滑面を有しており、この平滑面に応力が集中すると、スペーサ板７１と封止体７３との間に層間剥離が発生しやすくなる。 By the way, such a semiconductor package structure 1 provided with a spacer plate 71 may fail due to delamination of the spacer plate 71 and the sealing body 73 in a reliability test at high temperature and high humidity. .. It is considered that the cause is that a spacer plate 71 formed by cutting a wafer as it is is used. The spacer plate 71 made of a wafer has a smooth surface, and when stress is concentrated on the smooth surface, delamination easily occurs between the spacer plate 71 and the sealing body 73.

本発明は、前述した従来の半導体パッケージ構造体において層間剥離が発生しやすいという課題に鑑みてなされたものであり、その主な目的は、反り及び層間剥離の発生を抑えられる新たな半導体パッケージ構造体、及びその製造方法を提供することにある。 The present invention has been made in view of the problem that delamination is likely to occur in the conventional semiconductor package structure described above, and its main purpose is a new semiconductor package structure capable of suppressing the occurrence of warpage and delamination. The purpose is to provide a body and a method for producing the body.

上記目的を達成するための本発明に係る半導体パッケージ構造体の特徴は、
複数の金属接点が形成された第１表面を有する電子回路基板と、
前記電子回路基板の前記第１表面上に設置され、接合層が形成されているスペーサ板と、
前記スペーサ板上に設置され、且つ前記電子回路基板の前記第１表面における前記金属接点に電気的に接続されている少なくとも１つの第１チップと、
前記スペーサ板及び各前記第１チップを覆い且つ前記スペーサ板における前記接合層と接触するように前記電子回路基板の前記第１表面上に形成された封止体とを備え、
前記接合層と前記封止体の接合強度が、ウェハと前記封止体の接合強度より大きい点にある。 The features of the semiconductor package structure according to the present invention for achieving the above object are:
An electronic circuit board having a first surface on which a plurality of metal contacts are formed,
A spacer plate installed on the first surface of the electronic circuit board and having a bonding layer formed therein.
With at least one first chip installed on the spacer plate and electrically connected to the metal contacts on the first surface of the electronic circuit board.
The spacer plate and the sealant formed on the first surface of the electronic circuit board so as to cover the spacer plate and each of the first chips and to be in contact with the bonding layer in the spacer plate are provided.
The bonding strength between the bonding layer and the sealing body is higher than the bonding strength between the wafer and the sealing body.

以上のように、本発明において使用されるスペーサ板は接合層を有しており、当該接合層と封止体との接合強度は、ウェハと封止体との接合強度より大きい。その結果、本発明において使用されるスペーサ板と封止体の接合強度を効果的に向上させることができるため、反りだけでなく、高温、高湿環境での層間剥離の発生をも抑制することができる。 As described above, the spacer plate used in the present invention has a bonding layer, and the bonding strength between the bonding layer and the sealing body is larger than the bonding strength between the wafer and the sealing body. As a result, the bonding strength between the spacer plate and the sealing body used in the present invention can be effectively improved, so that not only warpage but also delamination in a high temperature and high humidity environment can be suppressed. Can be done.

上記目的を達成するための本発明に係る半導体パッケージ構造体の製造方法の特徴は、
複数のスペーサ板を用意するステップ（ａ）と、
載置板を用意し、複数電子回路基板を有する基板を前記載置板上に設置するステップ（ｂ）と、
各前記電子回路基板上に前記スペーサ板を設置し、各前記スペーサ板は接合層を有するステップ（ｃ）と、
各前記スペーサ板上に少なくとも１つの第１チップを設置するステップ（ｄ）と、
前記少なくとも１つの第１チップを、対応する前記電子回路基板に電気的に接続するステップ（ｅ）と、
複数の前記スペーサ板と複数の前記第１チップを覆うように、前記基板上に封止体を形成し、前記接合層と前記封止体の接合強度が、ウェハと前記封止体の接合強度より大きいステップ（ｆ）と、
電子回路基板の位置に対応して前記封止体及び前記基板を切断し、複数の独立した半導体パッケージ構造体とするステップ（ｇ）とを含む点にある。 The features of the method for manufacturing a semiconductor package structure according to the present invention for achieving the above object are:
Step (a) to prepare a plurality of spacer plates,
Step (b) of preparing a mounting plate and installing a substrate having a plurality of electronic circuit boards on the above-mentioned mounting plate,
The spacer plate is installed on each of the electronic circuit boards, and each of the spacer plates has a bonding layer in step (c).
In step (d) of installing at least one first chip on each of the spacer plates,
A step (e) of electrically connecting the at least one first chip to the corresponding electronic circuit board.
An encapsulant is formed on the substrate so as to cover the plurality of spacer plates and the plurality of first chips, and the bonding strength between the bonding layer and the sealing body is the bonding strength between the wafer and the sealing body. Larger step (f) and
It is a point including a step (g) of cutting the sealing body and the substrate according to the position of the electronic circuit board to form a plurality of independent semiconductor package structures.

以上のように、本発明に係る半導体パッケージ構造体の製造方法では、接合層を有するスペーサ板が使用され、当該接合層と封止体との接合強度は、ウェハと封止体との接合強度より大きい。その結果、スペーサ板と、当該スペーサ板を覆う封止体との接合強度を良好なものとすることができ、反りだけでなく、高温、高湿環境での層間剥離の発生をも抑制することができる。 As described above, in the method for manufacturing a semiconductor package structure according to the present invention, a spacer plate having a bonding layer is used, and the bonding strength between the bonding layer and the sealing body is the bonding strength between the wafer and the sealing body. Greater. As a result, the bonding strength between the spacer plate and the sealing body covering the spacer plate can be improved, and not only warpage but also delamination in a high temperature and high humidity environment can be suppressed. Can be done.

本発明に係る半導体パッケージ構造体の第１実施形態の断面図である。It is sectional drawing of 1st Embodiment of the semiconductor package structure which concerns on this invention. 本発明に係る半導体パッケージ構造体の第２実施形態の断面図である。It is sectional drawing of the 2nd Embodiment of the semiconductor package structure which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係る製造方法におけるステップを示す模式図である。It is a schematic diagram which shows the step in the manufacturing method which concerns on this invention. 本発明に係るスペーサ板を部分的に示す外観斜視図である。It is an external perspective view which partially shows the spacer plate which concerns on this invention. 本発明に係る半導体パッケージ構造体の第３実施形態の断面図である。It is sectional drawing of the 3rd Embodiment of the semiconductor package structure which concerns on this invention. 本発明に係るスペーサ板の異なる形態を示す平面視である。It is a plan view which shows the different form of the spacer plate which concerns on this invention. 本発明に係る半導体パッケージ構造体の第４実施形態の断面図である。It is sectional drawing of the 4th Embodiment of the semiconductor package structure which concerns on this invention. 本発明に係る半導体パッケージ構造体の第５実施形態の断面図である。It is sectional drawing of the 5th Embodiment of the semiconductor package structure which concerns on this invention. 従来の半導体パッケージ構造体の断面図である。It is sectional drawing of the conventional semiconductor package structure.

本発明は、高温、高湿環境において発生する層間剥離による歩留りの低下を抑えることができる半導体パッケージ構造体及びその製造方法を提供する。以下、複数実施形態を用いて図面を参照しながら本発明の内容を詳細に説明する。 The present invention provides a semiconductor package structure capable of suppressing a decrease in yield due to delamination that occurs in a high temperature and high humidity environment, and a method for manufacturing the same. Hereinafter, the contents of the present invention will be described in detail with reference to the drawings using a plurality of embodiments.

図１は本発明に係る半導体パッケージ構造体の第１実施形態の断面図である。図１に示すように、半導体パッケージ構造体は、電子回路基板（ｃｉｒｃｕｉｔ ｂｏａｒｄ）１０と、スペーサ板２０と、複数の第１チップ３０ａ、３０ｂ、３０ｃ、３０ｄと、封止体４０とを備えている。各第１チップ３０ａ、３０ｂ、３０ｃ、３０ｄは、電子回路基板１０に電気的に接続されている。スペーサ板２０は、各第１チップ３０ａ、３０ｂ、３０ｃ、３０ｄと電子回路基板１０との間に設置されている。封止体４０は、スペーサ板２０と各第１チップ３０ａ、３０ｂ、３０ｃ、３０ｄを覆うように電子回路基板１０上に形成されている。 FIG. 1 is a cross-sectional view of a first embodiment of the semiconductor package structure according to the present invention. As shown in FIG. 1, the semiconductor package structure includes an electronic circuit board (circuit board) 10, a spacer plate 20, a plurality of first chips 30a, 30b, 30c, 30d, and a sealing body 40. There is. The first chips 30a, 30b, 30c, and 30d are electrically connected to the electronic circuit board 10. The spacer plate 20 is installed between the first chips 30a, 30b, 30c, and 30d and the electronic circuit board 10. The sealing body 40 is formed on the electronic circuit board 10 so as to cover the spacer plate 20 and the first chips 30a, 30b, 30c, and 30d, respectively.

前記電子回路基板１０は、予め成型された配線板（ｗｉｒｉｎｇ ｂｏａｒｄ）又は再配線層である。電子回路基板１０は、複数の金属接点１１１が形成された第１表面１１と、複数の金属接点１２１が形成された第２表面１２とを有する。 The electronic circuit board 10 is a pre-molded wiring board or rewiring layer. The electronic circuit board 10 has a first surface 11 on which a plurality of metal contacts 111 are formed, and a second surface 12 on which a plurality of metal contacts 121 are formed.

スペーサ板２０は電子回路基板１０の第２表面１２上に設置され、接合層２２を有している。本実施形態において、スペーサ板２０の上表面２１は、接合層２２を構成する、平滑面ではない粗面２２１を有している。具体的には、スペーサ板２０の上表面２１における周縁部には、複数の溝２２２が形成されている。 The spacer plate 20 is installed on the second surface 12 of the electronic circuit board 10 and has a bonding layer 22. In the present embodiment, the upper surface 21 of the spacer plate 20 has a rough surface 221 that is not a smooth surface and constitutes the bonding layer 22. Specifically, a plurality of grooves 222 are formed on the peripheral edge of the upper surface 21 of the spacer plate 20.

本実施形態において、第１チップ３０ａ、３０ｂ、３０ｃ、３０ｄは、スペーサ板２０における溝２２２を覆うことなく露出させるように、当該スペーサ板２０の上表面２１に積層して配置されている。本実施形態において、第１チップ３０ｂ、３０ｄにおける接点３０１は、ワイヤーボンディングにより、電子回路基板１０の第２表面１２における金属接点１２１に金属ワイヤー３３を介して接続されている。第１チップ３０ａ、３０ｃにおける接点３０１は、同様にワイヤーボンディングにより、第１チップ３０ｂ、３０ｄにおける接点３０１に金属ワイヤー３３を介して接続されている。 In the present embodiment, the first chips 30a, 30b, 30c, and 30d are arranged so as to be laminated on the upper surface 21 of the spacer plate 20 so as to be exposed without covering the groove 222 of the spacer plate 20. In the present embodiment, the contacts 301 in the first chips 30b and 30d are connected to the metal contacts 121 on the second surface 12 of the electronic circuit board 10 via the metal wires 33 by wire bonding. The contacts 301 in the first chips 30a and 30c are similarly connected to the contacts 301 in the first chips 30b and 30d via wire bonding via a metal wire 33.

封止体４０は、スペーサ板２０及び第１チップ３０を覆い且つスペーサ板２０における接合層２２と接触するように、電子回路基板１０の第２表面１２に形成されている。接合層２２と封止体４０の接合強度は、ウェハと封止体４０の接合強度より大きい。本実施形態において、封止体４０は溝２２２内にも形成されている。これにより、封止体４０とスペーサ板２０の接合強度がより良好なものとなるため、層間剥離の現象が抑えられる。 The sealing body 40 is formed on the second surface 12 of the electronic circuit board 10 so as to cover the spacer plate 20 and the first chip 30 and to be in contact with the bonding layer 22 in the spacer plate 20. The bonding strength between the bonding layer 22 and the sealing body 40 is greater than the bonding strength between the wafer and the sealing body 40. In the present embodiment, the sealing body 40 is also formed in the groove 222. As a result, the bonding strength between the sealing body 40 and the spacer plate 20 becomes better, so that the phenomenon of delamination can be suppressed.

図１Ｂは、本発明の第２実施形態に係る半導体パッケージ構造体の断面図である。第２実施形態に係る半導体パッケージ構造体は、上述した第１実施形態と構造が概ね共通しているが、電子回路基板１０の第２表面１２上に設置されている第２チップ３１を更に備えている。第２チップ３１上にはスペーサ板２０が設置され、スペーサ板２０の上表面２１には第１チップ３０が積層して配置されている。第１実施形態と同様に、本実施形態におけるスペーサ板２０は、上表面の周縁部に溝２２２が形成されている。第１チップ３０、第２チップ３１及びスペーサ板２０を覆う封止体４０は、溝２２２内にも形成されている。 FIG. 1B is a cross-sectional view of the semiconductor package structure according to the second embodiment of the present invention. The semiconductor package structure according to the second embodiment has substantially the same structure as the first embodiment described above, but further includes a second chip 31 installed on the second surface 12 of the electronic circuit board 10. ing. A spacer plate 20 is installed on the second chip 31, and the first chip 30 is laminated and arranged on the upper surface 21 of the spacer plate 20. Similar to the first embodiment, the spacer plate 20 in the present embodiment has a groove 222 formed on the peripheral edge of the upper surface. The sealing body 40 that covers the first chip 30, the second chip 31, and the spacer plate 20 is also formed in the groove 222.

図２Ａ〜図２Ｉは、図１Ａに示される半導体パッケージ構造体の製造方法の第１実施形態を示す図である。本発明に係る製造方法には、以下のステップ（ａ）〜ステップ（ｇ）が含まれている。 2A to 2I are diagrams showing a first embodiment of the method for manufacturing the semiconductor package structure shown in FIG. 1A. The production method according to the present invention includes the following steps (a) to (g).

ステップ（ａ）では、複数のスペーサ板２０を用意する。本実施形態において、図２Ａ〜図２Ｃに示すように、まず、複数のスペーサ板領域５１を有するウェハ５０を用意し、各スペーサ板領域５１の全体又は周縁部に粗面２２１を形成する。そして、隣接するスペーサ板領域５１の間に沿ってウェハ５０を切断し、それぞれに粗面２２１が形成された、互いに分離した複数のスペーサ板２０とする。具体的には、各スペーサ板２０における上表面２１の周縁部に複数の溝２２２が形成されている。 In step (a), a plurality of spacer plates 20 are prepared. In the present embodiment, as shown in FIGS. 2A to 2C, first, a wafer 50 having a plurality of spacer plate regions 51 is prepared, and a rough surface 221 is formed on the entire or peripheral edge of each spacer plate region 51. Then, the wafer 50 is cut along between the adjacent spacer plate regions 51 to form a plurality of spacer plates 20 separated from each other on which a rough surface 221 is formed. Specifically, a plurality of grooves 222 are formed on the peripheral edge of the upper surface 21 of each spacer plate 20.

ステップ（ｂ）では、図２Ｄに示すように、粘着層６１が形成された載置板６０を用意し、当該粘着層６１上に、複数の電子回路基板１０を有する基板１を設置する。本実施形態において、基板１として予め成型されたものを使用し得る。また、再配線によって粘着層６１上に形成された再配線層を基板１とすることもできる。 In step (b), as shown in FIG. 2D, a mounting plate 60 on which the adhesive layer 61 is formed is prepared, and a substrate 1 having a plurality of electronic circuit boards 10 is installed on the adhesive layer 61. In the present embodiment, a pre-molded substrate 1 can be used. Further, the rewiring layer formed on the adhesive layer 61 by rewiring can be used as the substrate 1.

ステップ（ｃ）では、図２Ｅに示すように、各スペーサ板２０を、基板１における対応の電子回路基板１０上に設置する。 In step (c), as shown in FIG. 2E, each spacer plate 20 is placed on the corresponding electronic circuit board 10 on the substrate 1.

ステップ（ｄ）では、図２Ｆに示すように、各スペーサ板２０上に、第１チップ３０を積層して配置する。 In step (d), as shown in FIG. 2F, the first chip 30 is laminated and arranged on each spacer plate 20.

ステップ（ｅ）では、図２Ｇに示すように、第１チップ３０を、ワイヤーボンディングにより、対応の電子回路基板１０に金属ワイヤー３３を介して電気的に接続する。 In step (e), as shown in FIG. 2G, the first chip 30 is electrically connected to the corresponding electronic circuit board 10 via the metal wire 33 by wire bonding.

ステップ（ｆ）では、図２Ｈに示すように、モールディングにより、基板１上にスペーサ板２０及び第１チップ３０を覆う封止体４０を形成する。モールディングによって各スペーサ板２０における溝２２２内に流し込まれた液状の封止材は、硬化すると溝２２２内に固定されることになる。 In step (f), as shown in FIG. 2H, a sealing body 40 covering the spacer plate 20 and the first chip 30 is formed on the substrate 1 by molding. The liquid encapsulant poured into the groove 222 of each spacer plate 20 by molding is fixed in the groove 222 when cured.

ステップ（ｇ）では、図２Ｉに示すように、電子回路基板１０の位置に対応して封止体４０及び基板１を切断し、複数の独立した半導体パッケージ構造体とする。 In step (g), as shown in FIG. 2I, the encapsulant 40 and the substrate 1 are cut according to the position of the electronic circuit board 10 to form a plurality of independent semiconductor package structures.

なお、図２Ｂ及び図３に示すように、前記ステップ（ａ）を以下のものとすることもできる。すなわち、ウェハ５０の表面における隣接するスペーサ板領域５１の間にレーザを照射することで、凹入した粗面２２１ａを形成する。その後、同様に、隣接するスペーサ板領域５１に沿って切断することで、複数の分離したスペーサ板２０とする。このように得られた各スペーサ板２０は、上表面の周縁部に外方に向くように傾斜した粗面２２１ａが形成されたものである。図４は、本発明に係る半導体パッケージ構造体の第３実施形態の断面図である。本実施形態では、半導体パッケージ構造体は図３に示すスペーサ板２０を備えている。スペーサ板２０の周縁部に外方に向くように傾斜した粗面２２１ａが形成されているため、同様にスペーサ板２０と封止体４０の接合強度を向上させる効果が得られる。 As shown in FIGS. 2B and 3, the step (a) can be as follows. That is, the recessed rough surface 221a is formed by irradiating the laser between the adjacent spacer plate regions 51 on the surface of the wafer 50. Then, similarly, by cutting along the adjacent spacer plate region 51, a plurality of separated spacer plates 20 are obtained. Each of the spacer plates 20 thus obtained has a rough surface 221a inclined outward so as to be formed on the peripheral edge of the upper surface. FIG. 4 is a cross-sectional view of a third embodiment of the semiconductor package structure according to the present invention. In this embodiment, the semiconductor package structure includes the spacer plate 20 shown in FIG. Since the rough surface 221a inclined so as to face outward is formed on the peripheral edge of the spacer plate 20, the effect of improving the joint strength between the spacer plate 20 and the sealing body 40 can be similarly obtained.

なお、図５の（Ａ）〜（Ｆ）に示すように、スペーサ板２０の上表面２１に対するレーザの照射によって様々な溝パターンを形成することで、上表面の粗さを増加させてもよい。例えば、図５の（Ａ）〜（Ｃ）に示すスペーサ板２０では、上表面２１の周縁部に、互いに平行である複数の溝２２２を形成している。溝２２２は、縦、横又は斜めに延びるものであってよい。また、図５の（Ｄ）〜（Ｆ）に示すスペーサ板２０では、上表面２１の全体に、互いに平行である複数の溝２２２を形成している。この場合においても、溝２２２は、縦、横又は斜めに延びるものであってよい。 As shown in FIGS. 5A to 5F, the roughness of the upper surface may be increased by forming various groove patterns by irradiating the upper surface 21 of the spacer plate 20 with a laser. .. For example, in the spacer plates 20 shown in FIGS. 5A to 5C, a plurality of grooves 222 parallel to each other are formed on the peripheral edge of the upper surface 21. The groove 222 may extend vertically, horizontally or diagonally. Further, in the spacer plates 20 shown in FIGS. 5D to 5F, a plurality of grooves 222 parallel to each other are formed on the entire upper surface 21. Even in this case, the groove 222 may extend vertically, horizontally or diagonally.

図６は、本発明に係る半導体パッケージ構造体の第４実施形態の断面図である。本実施形態では、半導体パッケージ構造体は図５の（Ｄ）に示すスペーサ板２０を備えている。スペーサ板２０の上表面における、第１チップ３０によって覆われていない溝２２２内にも封止体４０が形成されているため、同様にスペーサ板２０との接合強度を向上させる効果が得られる。 FIG. 6 is a cross-sectional view of a fourth embodiment of the semiconductor package structure according to the present invention. In the present embodiment, the semiconductor package structure includes the spacer plate 20 shown in FIG. 5D. Since the sealing body 40 is also formed in the groove 222 on the upper surface of the spacer plate 20 that is not covered by the first chip 30, the effect of improving the bonding strength with the spacer plate 20 can be similarly obtained.

図７は、本発明に係る半導体パッケージ構造体の第５実施形態の断面図である。第５実施形態に係る半導体パッケージ構造体は、上表面２１に溝が形成されていないスペーサ板２０を備えている点を除いて、上述した実施形態と構造が共通している。本実施形態において、スペーサ板２０の上表面２１の全体には、接合層２２としての材料層が形成されている。当該接合層２２は、封止体４０との接合強度がスペーサ板２０よりも良好なものである。すなわち、材料層と封止体４０の接合強度が、スペーサ板２０と封止体４０の接合強度よりも高い。なお、材料層は、スペーサ板２０の上表面２１の周縁部にのみ形成されてもよい。更に、材料コストが低減されるように、スペーサ板２０の上表面２１に、パターンを有する材料層を形成することもでき、パターンの形態は限定されず、任意のものであり得る。本実施形態において、材料層は、例えばエポキシ樹脂等からなる接着剤層２２３である。この場合、図２Ｅに示すステップ（ｃ）では、各電子回路基板１０にスペーサ板２０を設置した後、ディスペンシングによってゲル状エポキシ樹脂を、各スペーサ板２０の上表面２１全体又は周縁部に付着させるか、又は、形態が限定されないパターンを有する材料層を形成するように各スペーサ板２０の上表面２１に付着させる。これによって、スペーサ板２０上に接合層２２を形成する。また、材料層は、ソルダーマスク２２４であってもよい。ソルダーマスク２２４は、封止体４０との接合強度がスペーサ板２０よりも良好なものである。すなわち、ソルダーマスク２２４と封止体４０の接合強度が、スペーサ板２０と封止体４０の接合強度よりも高い。この場合においても、図２Ｅに示すステップ（ｃ）では、スペーサ板２０を対応の電子回路基板１０に設置した後、ソルダーマスク２２４を、スペーサ板２０の上表面２１全体又は周縁部に塗布するか、又は、形態が限定されないパターンを有する材料層を形成するようにスペーサ板２０の上表面２１に塗布する。 FIG. 7 is a cross-sectional view of a fifth embodiment of the semiconductor package structure according to the present invention. The semiconductor package structure according to the fifth embodiment has the same structure as the above-described embodiment except that the spacer plate 20 having no groove formed on the upper surface 21 is provided. In the present embodiment, a material layer as a bonding layer 22 is formed on the entire upper surface 21 of the spacer plate 20. The bonding layer 22 has a stronger bonding strength with the sealing body 40 than the spacer plate 20. That is, the bonding strength between the material layer and the sealing body 40 is higher than the bonding strength between the spacer plate 20 and the sealing body 40. The material layer may be formed only on the peripheral edge of the upper surface 21 of the spacer plate 20. Further, a material layer having a pattern can be formed on the upper surface 21 of the spacer plate 20 so as to reduce the material cost, and the form of the pattern is not limited and may be arbitrary. In the present embodiment, the material layer is an adhesive layer 223 made of, for example, an epoxy resin. In this case, in step (c) shown in FIG. 2E, after the spacer plate 20 is installed on each electronic circuit board 10, the gel epoxy resin is adhered to the entire upper surface 21 or the peripheral edge of each spacer plate 20 by dispensing. Alternatively, it is attached to the upper surface 21 of each spacer plate 20 so as to form a material layer having a pattern having an unlimited form. As a result, the bonding layer 22 is formed on the spacer plate 20. Further, the material layer may be a solder mask 224. The solder mask 224 has a better bonding strength with the sealing body 40 than the spacer plate 20. That is, the bonding strength between the solder mask 224 and the sealing body 40 is higher than the bonding strength between the spacer plate 20 and the sealing body 40. Also in this case, in step (c) shown in FIG. 2E, after the spacer plate 20 is installed on the corresponding electronic circuit board 10, the solder mask 224 is applied to the entire upper surface 21 or the peripheral edge of the spacer plate 20. Or, it is applied to the upper surface 21 of the spacer plate 20 so as to form a material layer having a pattern having an unlimited form.

更に、ソルダーマスク２２４と封止体４０の接着性が良好であることから、前述したステップ（ａ）ではウェハ５０を用いて複数のスペーサ板２０を作製していたが、ウェハ５０の代りに電子回路基板用樹脂基板（例えばＦＲ４基板）を使用してもよい。この場合では、表面にソルダーマスクが形成されている樹脂基板をステップ（ａ）でそのまま切断すれば、ソルダーマスクを有する複数のスペーサ板が得られるため、ステップ（ｃ）においてソルダーマスクを形成する作業を省略できる。なお、ここで使用される樹脂基板は、内部に金属配線層が形成されていないものである。 Further, since the adhesiveness between the solder mask 224 and the sealing body 40 is good, a plurality of spacer plates 20 were produced using the wafer 50 in the above-mentioned step (a), but instead of the wafer 50, electrons are used. A resin substrate for a circuit board (for example, a FR4 substrate) may be used. In this case, if the resin substrate on which the solder mask is formed on the surface is cut as it is in step (a), a plurality of spacer plates having the solder mask can be obtained. Therefore, the work of forming the solder mask in step (c). Can be omitted. The resin substrate used here has no metal wiring layer formed inside.

また、封止体との接合強度が最も良好なのは、同一材質の封止材そのものであることから、前述したステップ（ａ）では、ウェハ５０の代りに、予め硬化成型された封止材ブロックを用いてもよい。この場合においても、ステップ（ａ）で封止材ブロックをそのまま切断すれば、ステップ（ｃ）で使用される複数スペーサ板が得られる。 Further, since the sealing material itself having the same material has the best bonding strength with the sealing body, in the step (a) described above, a pre-cured sealing material block is used instead of the wafer 50. You may use it. Even in this case, if the encapsulant block is cut as it is in step (a), the plurality of spacer plates used in step (c) can be obtained.

本発明に係る半導体パッケージ構造体の上述した複数の実施形態から分かるように、本発明において主に使用されるスペーサ板は、封止体との接合強度を向上させることができる表面を有している。例えば、ウェハを用いてスペーサ板を作製する場合、スペーサ板の表面に対する工具やレーザによる切削又はエッチングなどの表面処理によって、粗さを増加した表面を形成してもよい。又は、スペーサ板の表面上に、エポキシ樹脂からなる接着剤層やソルダーマスクなど、封止体との接合強度が比較的高い材料を形成してもよい。更に、ウェハの代りに、封止体との接合強度が比較的に高い材料を使用し、そのまま切断して複数のスペーサ板とすることもできる。このようなスペーサ板は、これを覆う封止体との間の接合強度が良好であるため、高温、高湿環境での層間剥離を抑えることができる。 As can be seen from the plurality of embodiments of the semiconductor package structure according to the present invention, the spacer plate mainly used in the present invention has a surface capable of improving the bonding strength with the sealing body. There is. For example, when a spacer plate is manufactured using a wafer, a surface with increased roughness may be formed by surface treatment such as cutting or etching with a tool or a laser on the surface of the spacer plate. Alternatively, a material having a relatively high bonding strength with the sealing body, such as an adhesive layer made of an epoxy resin or a solder mask, may be formed on the surface of the spacer plate. Further, instead of the wafer, a material having a relatively high bonding strength with the encapsulant can be used and cut as it is to form a plurality of spacer plates. Since such a spacer plate has good bonding strength with the sealing body covering the spacer plate, delamination in a high temperature and high humidity environment can be suppressed.

本発明を上記実施形態により説明したが、本発明はこれら開示された実施形態に限定されず、当業者であれば、本発明の技術的思想を逸脱することなく、様々な変更および修飾を加えて均等物とすることができる。したがって、上記実施形態に変更、改変および修飾を加えた内容もまた、本発明の技術的思想に含まれるものである。 Although the present invention has been described by the above embodiments, the present invention is not limited to these disclosed embodiments, and those skilled in the art can make various modifications and modifications without departing from the technical idea of the present invention. Can be equal. Therefore, the contents of the above-described embodiment modified, modified and modified are also included in the technical idea of the present invention.

１ 基板
１０ 電子回路基板
１１ 第１表面
１１１ 金属接点
１２ 第２表面
１２１ 金属接点
２０ スペーサ板
２１ 表面
２２ 接合層
２２１、２２１ａ 粗面
２２２ 溝
２２３ 接着剤層
２２４ ソルダーマスク
３０ａ、３０ｂ、３０ｃ、３０ｄ 第１チップ
３０１ 接点
３１ 第２チップ
３３ 金属ワイヤー
４０ 封止体
５０ ウェハ
５１ スペーサ板領域
６０ 載置板
６１ 粘着層
７０ 電子回路基板
７１ スペーサ板
７２ チップ
７３ 封止体 1 Substrate 10 Electronic circuit board 11 First surface 111 Metal contact 12 Second surface 121 Metal contact 20 Spacer plate 21 Surface 22 Bonding layer 221, 221a Rough surface 222 Groove 223 Adhesive layer 224 Solder mask 30a, 30b, 30c, 30d 1 Chip 301 Contact 31 Second Chip 33 Metal Wire 40 Encapsulant 50 Wafer 51 Spacer Plate Area 60 Mounting Plate 61 Adhesive Layer 70 Electronic Circuit Board 71 Spacer Plate 72 Chip 73 Encapsulant

Claims (10)

複数の金属接点が形成された第１表面を有する電子回路基板と、
前記電子回路基板の前記第１表面上に設置され、複数の溝が上部全体にわたって形成されているスペーサ板と、
前記スペーサ板上に設置され、且つ前記電子回路基板の前記第１表面における前記金属接点に電気的に接続されている少なくとも１つの第１チップと、
前記スペーサ板及び各前記第１チップを覆い、且つ前記第１チップによって覆われていない前記溝内に形成されるように前記電子回路基板の前記第１表面上に形成された封止体とを備えることを特徴とする半導体パッケージ構造体。 An electronic circuit board having a first surface on which a plurality of metal contacts are formed,
A spacer plate installed on the first surface of the electronic circuit board and having a plurality of grooves formed over the entire upper portion .
With at least one first chip installed on the spacer plate and electrically connected to the metal contacts on the first surface of the electronic circuit board.
Said spacer plate and covers each of said first chip, and a sealing member formed on the first surface of the electronic circuit board to be formed on the first said groove which is not covered by the chip the semiconductor package structure, characterized in that the Ru with. 前記電子回路基板と前記スペーサ板の間に設置され、且つ前記電子回路基板に電気的に接続されている第２チップを更に備えることを特徴とする、請求項１に記載の半導体パッケージ構造体。 The semiconductor package structure according to claim 1, further comprising a second chip installed between the electronic circuit board and the spacer plate and electrically connected to the electronic circuit board. 前記スペーサ板は、ＦＲ４基板を切断して形成されたものであることを特徴とする、請求項１又は２に記載の半導体パッケージ構造体。 The semiconductor package structure according to claim 1 or 2, wherein the spacer plate is formed by cutting an FR4 substrate. 前記スペーサ板は、前記封止体と同一材質である封止材ブロックを切断して形成されたものであることを特徴とする、請求項１又は２に記載の半導体パッケージ構造体。 The semiconductor package structure according to claim 1 or 2, wherein the spacer plate is formed by cutting a sealing material block made of the same material as the sealing body. 前記スペーサ板における前記複数の溝は、工具による切削、レーザによる切削、又はエッチングによって形成されていることを特徴とする、請求項１から４のいずれか一項に記載の半導体パッケージ構造体。 The semiconductor package structure according to any one of claims 1 to 4, wherein the plurality of grooves in the spacer plate are formed by cutting with a tool, cutting with a laser, or etching. 複数の溝が上部全体にわたって形成されている複数のスペーサ板を用意するステップ（ａ）と、
載置板を用意し、複数の電子回路基板を有する基板を前記載置板上に設置するステップ（ｂ）と、
各前記電子回路基板上に前記スペーサ板を設置するステップ（ｃ）と、
各前記スペーサ板上に少なくとも１つの第１チップを設置するステップ（ｄ）と、
前記少なくとも１つの第１チップを、対応する前記電子回路基板に電気的に接続するステップ（ｅ）と、
複数の前記スペーサ板と複数の前記第１チップを覆うように、前記基板上に封止体を形成し、前記封止体は、前記第１チップによって覆われていない前記溝内に形成されているステップ（ｆ）と、
電子回路基板の位置に対応して前記封止体及び前記基板を切断し、複数の独立した半導体パッケージ構造体とするステップ（ｇ）と、を含む半導体パッケージ構造体の製造方法。 In step (a) of preparing a plurality of spacer plates in which a plurality of grooves are formed over the entire upper portion ,
Step (b) of preparing a mounting plate and installing a substrate having a plurality of electronic circuit boards on the above-mentioned mounting plate,
And step (c) you established the said spacer plate to each of said electronic circuit board,
In step (d) of installing at least one first chip on each of the spacer plates,
A step (e) of electrically connecting the at least one first chip to the corresponding electronic circuit board.
An encapsulant is formed on the substrate so as to cover the plurality of spacer plates and the plurality of first chips, and the encapsulant is formed in the groove not covered by the first chip. and step (f) it is,
A method for manufacturing a semiconductor package structure, comprising a step (g) of cutting the sealing body and the substrate according to the position of an electronic circuit board to form a plurality of independent semiconductor package structures. 前記ステップ（ｂ）は、第２チップを対応する電子回路基板上に設置することを更に含み、
前記ステップ（ｃ）では、各前記スペーサ板を前記第２チップ上にそれぞれ設置することを特徴とする、請求項６に記載の半導体パッケージ構造体の製造方法。 The step (b) further comprises installing the second chip on the corresponding electronic circuit board.
The method for manufacturing a semiconductor package structure according to claim 6 , wherein in the step (c), each of the spacer plates is installed on the second chip. 前記ステップ（ａ）は、
複数のスペーサ板領域を有する樹脂基板を用意するステップ（ａ１）と、
隣接するスペーサ板領域の間に沿って前記樹脂基板を切断し、互いに分離した複数のスペーサ板とするステップ（ａ２）とを含むことを特徴とする、請求項６又は７に記載の半導体パッケージ構造体の製造方法。 The step (a) is
A step (a1) providing a resin substrate you have a plurality of spacer plates area,
The semiconductor package structure according to claim 6 or 7 , further comprising a step (a2) of cutting the resin substrate along between adjacent spacer plate regions to form a plurality of spacer plates separated from each other. How to make a body. 前記ステップ（ａ）は、
複数のスペーサ板領域を有する封止材ブロックを用意するステップ（ａ１）と、
隣接するスペーサ板領域の間に沿って前記封止材ブロックを切断し、互いに分離した複数のスペーサ板とするステップ（ａ２）とを含むことを特徴とする、請求項６又は７に記載の半導体パッケージ構造体の製造方法。 The step (a) is
Step (a1) of preparing a sealing material block having a plurality of spacer plate regions, and
The semiconductor according to claim 6 or 7 , further comprising a step (a2) of cutting the encapsulant block along between adjacent spacer plate regions to form a plurality of spacer plates separated from each other. Manufacturing method of package structure. 前記ステップ（ａ２）は、工具による切削、レーザによる切削、又はエッチングによって互いに平行である前記複数の溝を形成することを含む、請求項８又は９に記載の半導体パッケージ構造体の製造方法。 Wherein step (a2) is the cutting by the tool, cutting with laser, or comprises forming a plurality of grooves are parallel to each other by an etching method for manufacturing a semiconductor package structure according to claim 8 or 9.
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