JP6586036B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP6586036B2
JP6586036B2 JP2016051543A JP2016051543A JP6586036B2 JP 6586036 B2 JP6586036 B2 JP 6586036B2 JP 2016051543 A JP2016051543 A JP 2016051543A JP 2016051543 A JP2016051543 A JP 2016051543A JP 6586036 B2 JP6586036 B2 JP 6586036B2
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semiconductor chip
adhesive
adhesive layer
wire
connection electrode
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JP2017168586A (en
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直樹 岩政
直樹 岩政
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Kioxia Corp
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Toshiba Memory Corp
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Priority to TW106104226A priority patent/TWI621232B/en
Priority to CN201710133212.0A priority patent/CN107195589B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

本発明の実施形態は、半導体装置に関する。   Embodiments described herein relate generally to a semiconductor device.

近年、半導体パッケージにおいて、半導体チップにダイアタッチフィルム（ＤＡＦ：Die Attach Film）等の接着剤を用いてメモリチップを積層する構造（ＦＯＤ：Film On Die）が広く利用されている。しかしながら、ダイアタッチフィルムを用いて半導体チップ同士を接着させると、モールド加工をした際に、基板上に接着したチップにより半導体パッケージに凹凸が生じ、その凹凸に起因する半導体基板の反りが問題となる場合がある。さらに、Ａｌ（アルミニウム）電極パッド上にＡｕ（金）ボンディングワイヤが接続される場合、ソルダーレジストや接着剤に含まれるＣｌ（塩素）イオンにより、Ａｌが腐食し、Ａｌ電極パッドとＡｕボンディングワイヤがオープンとなる可能性がある。   In recent years, in a semiconductor package, a structure (FOD: Film On Die) in which a memory chip is laminated on a semiconductor chip using an adhesive such as a die attach film (DAF) is widely used. However, when semiconductor chips are bonded to each other using a die attach film, when the mold process is performed, the semiconductor package has irregularities due to the chips adhered on the substrate, and warpage of the semiconductor substrate due to the irregularities becomes a problem. There is a case. Further, when an Au (gold) bonding wire is connected on an Al (aluminum) electrode pad, Al corrodes due to Cl (chlorine) ions contained in the solder resist or adhesive, and the Al electrode pad and the Au bonding wire are May be open.

また、半導体チップを支柱チップにより支える構造もあるが、半導体チップと配線基板とを接続するワイヤが、支柱チップに接触することにより、半導体パッケージ内の配線がショートする可能性がある。このため、ワイヤの配置が制限され、すなわち、半導体チップのレイアウトが制限されることとなる。   In addition, there is a structure in which the semiconductor chip is supported by the support chip, but there is a possibility that a wire in the semiconductor package may be short-circuited when a wire connecting the semiconductor chip and the wiring board contacts the support chip. For this reason, the arrangement of the wires is limited, that is, the layout of the semiconductor chip is limited.

特開２０１３−６２３２８号公報JP2013-62328A

そこで、本発明が解決しようとする課題は、パッドの腐食を低減させ、さらに半導体チップとワイヤの配置の自由度を向上する構造を提案することである。   Therefore, the problem to be solved by the present invention is to propose a structure that reduces the corrosion of the pad and further improves the degree of freedom of arrangement of the semiconductor chip and the wire.

実施形態によれば、接続端子を有する基板上に第１半導体チップを設け、接続端子と、
第１半導体チップ上の接続電極とをワイヤにて接続し、矩形状の第１接着層と、第１接着
層の四隅に位置し第１接着層における２対の対辺のうち少なくとも１対の対辺のそれぞれ
の下部に開口部が形成された柱状の第２接着層と、を有する接着部をフィルム状の絶縁材
料の接着剤をスタンプすることで形成し、接着部を第２接着層の一部がワイヤ及び接続端
子に接触し、接続電極とは接触しないように第１半導体チップの上に設け、接着部の上に
第２半導体チップを設け、接着部と第１半導体チップとの間を含む領域をモールド材で封
止し、ワイヤの接続電極からの最大高さが接続電極と第１接着層との間隔よりも小さくな
る。 According to the embodiment, the first semiconductor chip is provided on the substrate having the connection terminal, the connection terminal, and
A connection electrode on the first semiconductor chip is connected by a wire, a rectangular first adhesive layer, and a first adhesive
Each of at least one pair of opposite sides of the two opposite sides of the first adhesive layer located at the four corners of the layer;
And a columnar second adhesive layer having an opening formed in the lower portion thereof, and the adhesive portion having a film-like insulating material
It is formed by stamping the adhesive of the material, part of the second adhesive layer is the wire and the connection end
Provided on the first semiconductor chip so that it contacts the child and does not contact the connection electrode,
A second semiconductor chip is provided, and a region including a space between the adhesive portion and the first semiconductor chip is sealed with a molding material.
The maximum height of the wire from the connection electrode is smaller than the distance between the connection electrode and the first adhesive layer.
The

一実施形態に係る半導体装置を模式的に示す正面図。1 is a front view schematically showing a semiconductor device according to an embodiment. 一実施形態に係る半導体装置を模式的に示す平面図。1 is a plan view schematically showing a semiconductor device according to an embodiment. 一実施形態に係る半導体装置を模式的に示す平面断面図。1 is a plan sectional view schematically showing a semiconductor device according to an embodiment. 一変形例に係る半導体装置を模式的に示す正面図。The front view which shows typically the semiconductor device which concerns on one modification. 図４Ａに係る半導体装置のＡ−Ａ断面図。4A is a cross-sectional view of the semiconductor device according to FIG. 一変形例に係る半導体装置を模式的に示す正面図。The front view which shows typically the semiconductor device which concerns on one modification. 図５Ｂに係る半導体装置のＡ−Ａ断面図AA sectional view of the semiconductor device concerning Drawing 5B. 一変形例に係る半導体装置を模式的に示す正面図。The front view which shows typically the semiconductor device which concerns on one modification. 図６Ｂに係る半導体装置のＡ−Ａ断面図。FIG. 6B is a cross-sectional view of the semiconductor device according to FIG.

以下、図面を参照して、本発明の実施形態について説明する。本実施形態は、本発明を限定するものではない。   Embodiments of the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

本発明の実施形態に係る半導体装置は、第１半導体チップと接触せずに、第１半導体チップを覆うように設置された机状の第２接着剤を介して第２半導体チップを設置することにより、半導体装置の反りを抑制するとともに、第１半導体チップの電極とボンディングワイヤの接続部分における腐食を抑制するとともに、第１半導体チップに接続されるボンディングワイヤと接着剤との位置関係の自由度を向上するものである。より詳しく、以下に説明する。   In a semiconductor device according to an embodiment of the present invention, a second semiconductor chip is installed through a desk-like second adhesive that is installed so as to cover the first semiconductor chip without contacting the first semiconductor chip. Accordingly, the warpage of the semiconductor device is suppressed, corrosion at the connection portion between the electrode of the first semiconductor chip and the bonding wire is suppressed, and the degree of freedom in the positional relationship between the bonding wire connected to the first semiconductor chip and the adhesive Is to improve. More detailed description will be given below.

図１は、本実施形態に係る半導体装置１を模式的に示す正面図である。この図１に示すように、半導体装置１は、例えば、半導体パッケージであり、基板１０と、第１接着剤１２と、第１半導体チップ１４と、第１接続端子１６と、第１接続電極１８と、第１ワイヤ２０と、接着部２２と、第２半導体チップ２４と、第２接着剤２６と、第２接続端子２８と、第２接続電極３０と、第２ワイヤ３２と、モールド材３４と、を備えて構成される。なお、以下、全ての図において、各構成要素の大きさの比や、細かい配置などは、実施形態を理解しやすいように示されているため、実際の比や配置とは異なる。また、模式的に示す図であるので、チップや基板上の配線等は、省略している。   FIG. 1 is a front view schematically showing a semiconductor device 1 according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 is, for example, a semiconductor package, and includes a substrate 10, a first adhesive 12, a first semiconductor chip 14, a first connection terminal 16, and a first connection electrode 18. The first wire 20, the bonding portion 22, the second semiconductor chip 24, the second adhesive 26, the second connection terminal 28, the second connection electrode 30, the second wire 32, and the molding material 34. And comprising. Hereinafter, in all the drawings, the ratio of the size of each component, the fine arrangement, and the like are shown so that the embodiments can be easily understood, and thus are different from the actual ratio and arrangement. Moreover, since it is a figure shown typically, the wiring on a chip | tip, a board | substrate, etc. are abbreviate | omitted.

基板１０は、所謂ウエハやダイであり、シリコン等により形成される。半導体装置１である半導体パッケージは、この基板１０上に形成される。   The substrate 10 is a so-called wafer or die, and is formed of silicon or the like. A semiconductor package which is the semiconductor device 1 is formed on the substrate 10.

第１接着剤１２は、第１半導体チップ１４を基板１０上に固定するための絶縁材料の接着剤である。この第１接着剤１２は、例えば、接着剤をフィルム状に加工したダイアタッチフィルムであり、第１半導体チップ１４の基板１０と接着させる面に装着し、その後基板１０へと固定される。   The first adhesive 12 is an insulating material adhesive for fixing the first semiconductor chip 14 on the substrate 10. The first adhesive 12 is, for example, a die attach film obtained by processing an adhesive into a film shape. The first adhesive 12 is attached to a surface of the first semiconductor chip 14 to be bonded to the substrate 10 and then fixed to the substrate 10.

第１半導体チップ１４は、所謂インターフェースチップやコントローラチップであり、基板１０上に第１接着剤１２を介して設置される。この第１半導体チップ１４は、半導体装置１と外部を接続するインターフェースを構成するチップであり、データの書込及び読出を制御するチップである。   The first semiconductor chip 14 is a so-called interface chip or controller chip, and is installed on the substrate 10 via the first adhesive 12. The first semiconductor chip 14 is a chip that constitutes an interface that connects the semiconductor device 1 to the outside, and is a chip that controls writing and reading of data.

第１接続端子１６は、基板１０上の配線と第１半導体チップ１４上の配線とを接続するために基板１０上に形成される接続端子である。この第１接続端子１６は、例えば、Ｃｕ（銅）の端子にＮｉ（ニッケル）やＡｕをめっきしたものである。図１に示すように、第１接続端子１６は、基板１０上に複数個設置されている。   The first connection terminal 16 is a connection terminal formed on the substrate 10 in order to connect the wiring on the substrate 10 and the wiring on the first semiconductor chip 14. For example, the first connection terminal 16 is obtained by plating a Cu (copper) terminal with Ni (nickel) or Au. As shown in FIG. 1, a plurality of first connection terminals 16 are installed on the substrate 10.

第１接続電極１８は、第１半導体チップ１４上に設置された電極であり、第１半導体チップ１４上の配線と、基板１０上の配線とを接続する電極である。この第１接続電極１８は、例えば、Ａｌにより形成されるパッド状の電極である。第１接続電極１８は、第１半導体チップ１４上に複数個配置されている。   The first connection electrode 18 is an electrode installed on the first semiconductor chip 14 and is an electrode that connects the wiring on the first semiconductor chip 14 and the wiring on the substrate 10. The first connection electrode 18 is a pad-like electrode made of, for example, Al. A plurality of first connection electrodes 18 are arranged on the first semiconductor chip 14.

第１ワイヤ２０は、所謂ボンディングワイヤであり、基板１０上の配線と第１半導体チップ１４上の配線とを、第１接続端子１６及び第１接続電極１８とを介して接続するワイヤである。すなわち、本実施形態においては、複数の第１接続端子１６と複数の第１接続電極１８との間を、複数の第１ワイヤ２０が電気的に接続している。この第１ワイヤ２０は、例えば、ＡｕやＣｕにより形成される。   The first wire 20 is a so-called bonding wire, and is a wire that connects the wiring on the substrate 10 and the wiring on the first semiconductor chip 14 through the first connection terminal 16 and the first connection electrode 18. That is, in the present embodiment, the plurality of first wires 20 are electrically connected between the plurality of first connection terminals 16 and the plurality of first connection electrodes 18. The first wire 20 is made of, for example, Au or Cu.

接着部２２は、第２半導体チップ２４を基板上に固定するための絶縁材料の接着剤である。この接着部２２も、第１接着剤１２と同様に、例えば、接着剤をフィルム状に加工したダイアタッチフィルムの一種である。接着部２２は、図１に示すように、第２半導体チップ２４と接する上部の第１接着層２２ａと、基板１０と接する下部の第２接着層２２ｂとを備えて構成される。また、第２接着層２２ｂは、その一部にモールド材３４を通過させるための開口部２２ｃを有している。   The bonding part 22 is an adhesive made of an insulating material for fixing the second semiconductor chip 24 on the substrate. The adhesive portion 22 is also a kind of die attach film obtained by processing an adhesive into a film, for example, like the first adhesive 12. As shown in FIG. 1, the bonding portion 22 includes an upper first bonding layer 22 a that contacts the second semiconductor chip 24 and a lower second bonding layer 22 b that contacts the substrate 10. The second adhesive layer 22b has an opening 22c for allowing the molding material 34 to pass therethrough.

第１接着層２２ａは、第２半導体チップ２４との接触面とほぼ同等の面積を有する、矩形状の薄い接着層である。一方の第２接着層２２ｂは、第１接着層２２ａに比べて厚い接着層である。この第２接着層２２ｂの厚さは、第１半導体チップ１４の上方において、第１ワイヤ２０と第１接着層２２ａとが接触しない程度の高さとなるように、その厚さが確保されている。本実施形態においては、第１接続電極１８に接続する第１ワイヤ２０が最も高くなる箇所で、第１ワイヤ２０が第１接着層２２ａに接触しない程度の厚さを有している。言い換えると、第１ワイヤ２０の第１接続電極１８からの最大高さが、第１接着層２２ａと第１接続電極１８との間隔より小さい。なお、第１接着剤１２と、接着部２２を構成する接着剤とは、接着作用のある同じ絶縁材料から構成されていてもよいし、違う絶縁材料から構成されていてもよい。   The first adhesive layer 22 a is a rectangular thin adhesive layer having an area substantially equal to the contact surface with the second semiconductor chip 24. One second adhesive layer 22b is a thicker adhesive layer than the first adhesive layer 22a. The thickness of the second adhesive layer 22b is secured above the first semiconductor chip 14 so that the first wire 20 and the first adhesive layer 22a are not in contact with each other. . In the present embodiment, the first wire 20 connected to the first connection electrode 18 has a thickness at which the first wire 20 does not contact the first adhesive layer 22a at the highest point. In other words, the maximum height of the first wire 20 from the first connection electrode 18 is smaller than the distance between the first adhesive layer 22 a and the first connection electrode 18. In addition, the 1st adhesive agent 12 and the adhesive agent which comprises the adhesion part 22 may be comprised from the same insulating material with an adhesive effect, and may be comprised from a different insulating material.

第２半導体チップ２４は、所謂メモリチップであり、接着部２２上に複数設置される。この第２半導体チップ２４は、データの書込や読出をするメモリチップである。図１に示すように、第２半導体チップ２４は、この第２半導体チップ２４上の第２接続電極３０の領域を確保できる程度にずらして積層され、全体として１つのメモリアレイを構成する。なお、構成によっては、第２半導体チップ２４を１枚とすることもできる。   The second semiconductor chip 24 is a so-called memory chip, and a plurality of second semiconductor chips 24 are installed on the bonding portion 22. The second semiconductor chip 24 is a memory chip for writing and reading data. As shown in FIG. 1, the second semiconductor chip 24 is stacked with a shift so as to ensure a region of the second connection electrode 30 on the second semiconductor chip 24, and constitutes one memory array as a whole. Depending on the configuration, the number of the second semiconductor chips 24 may be one.

第２接着剤２６は、第２半導体チップ２４同士を接着する接着剤である。すなわち、複数の第２半導体チップ２４が、第２接着剤２６を介して、積層される。この第２接着剤２６も、第１接着剤１２や接着部２２と同様に、ダイアタッチフィルムで構成されていてもよい。   The second adhesive 26 is an adhesive that bonds the second semiconductor chips 24 together. That is, the plurality of second semiconductor chips 24 are stacked via the second adhesive 26. The second adhesive 26 may also be formed of a die attach film, like the first adhesive 12 and the adhesive portion 22.

第２接続端子２８は、基板１０上の配線と第２半導体チップ２４上の配線とを接続するために基板１０上に設置される接続端子である。この第２接続端子２８は、例えば、Ｃｕの端子にＮｉやＡｕをめっきしたものである。第１接続端子１６と同様に、第２接続端子２８は、第２半導体チップ２４との接続をするために複数個設置されている。   The second connection terminal 28 is a connection terminal installed on the substrate 10 in order to connect the wiring on the substrate 10 and the wiring on the second semiconductor chip 24. The second connection terminal 28 is, for example, a Cu terminal plated with Ni or Au. Similar to the first connection terminal 16, a plurality of second connection terminals 28 are provided for connection to the second semiconductor chip 24.

第２接続電極３０は、第２半導体チップ２４上に設置された電極であり、第２半導体チップ２４上の配線と、基板１０上の配線とを接続する電極である。この第２接続電極３０は、例えば、Ａｌにより形成されるパッド状の電極である。また、第２接続電極３０も、第２半導体チップ２４上に複数個設置されている。   The second connection electrode 30 is an electrode installed on the second semiconductor chip 24 and is an electrode for connecting the wiring on the second semiconductor chip 24 and the wiring on the substrate 10. The second connection electrode 30 is a pad-like electrode made of, for example, Al. A plurality of second connection electrodes 30 are also provided on the second semiconductor chip 24.

第２ワイヤ３２は、所謂ボンディングワイヤであり、基板１０上の配線と第２半導体チップ２４上の配線とを、第２接続端子２８及び第２接続電極３０とを介して接続するワイヤである。すなわち、本実施形態においては、複数の第２接続端子２８と複数の第２接続電極３０との間を、複数の第２ワイヤ３２が電気的に接続している。この第２ワイヤ３２は、例えば、ＡｕやＣｕにより形成される。   The second wire 32 is a so-called bonding wire, and connects the wiring on the substrate 10 and the wiring on the second semiconductor chip 24 via the second connection terminal 28 and the second connection electrode 30. That is, in the present embodiment, the plurality of second wires 32 are electrically connected between the plurality of second connection terminals 28 and the plurality of second connection electrodes 30. The second wire 32 is formed of, for example, Au or Cu.

モールド材３４は、第１半導体チップ１４と、第２半導体チップ２４とを基板１０に封止する絶縁材料のモールド材であり、例えば、エポキシ樹脂、シリカの粉末、カーボンブラック等を主体とするモールド樹脂である。なお、この図１においては、説明の便宜上、モールド材３４は、一部を省略して図示されているが、モールド材３４は、基板１０上に、基板１０上に設置された種々の半導体チップや接続ワイヤを覆うような形で配置されている。   The molding material 34 is a molding material of an insulating material that seals the first semiconductor chip 14 and the second semiconductor chip 24 to the substrate 10. For example, the molding material 34 is mainly composed of epoxy resin, silica powder, carbon black, or the like. Resin. In FIG. 1, for convenience of explanation, a part of the molding material 34 is omitted, but the molding material 34 is provided on the substrate 10 and various semiconductor chips installed on the substrate 10. It is arranged so as to cover the connecting wire.

図２は、図１に示す半導体装置１の平面図である。なお、この図２においては、モールド材３４は説明のために図示していない。また、以下で示す平面断面図においても、説明の便宜上、モールド材３４の図示は省略している。   FIG. 2 is a plan view of the semiconductor device 1 shown in FIG. In FIG. 2, the molding material 34 is not shown for explanation. Also, in the plan sectional views shown below, the illustration of the molding material 34 is omitted for convenience of explanation.

この図２に示すように、半導体装置１を平面からみると、複数の第２半導体チップ２４がずらして積層されている。また、これらの第２半導体チップ２４の端部において、複数の第２接続電極３０を介して複数の第２ワイヤ３２が、基板１０上の複数の第２接続端子２８と接続することにより、第２半導体チップ２４と基板１０とが接続されている。   As shown in FIG. 2, when the semiconductor device 1 is viewed from the top, a plurality of second semiconductor chips 24 are stacked while being shifted. Further, at the end portions of the second semiconductor chips 24, the plurality of second wires 32 are connected to the plurality of second connection terminals 28 on the substrate 10 via the plurality of second connection electrodes 30, thereby 2 The semiconductor chip 24 and the substrate 10 are connected.

破線は、第２半導体チップ２４の下方にある、第１半導体チップ１４を示す。このように、平面視において、第１半導体チップ１４は、第２半導体チップ２４により覆われるように設置されている。   A broken line indicates the first semiconductor chip 14 below the second semiconductor chip 24. Thus, the first semiconductor chip 14 is installed so as to be covered with the second semiconductor chip 24 in plan view.

図３は、半導体装置１の第１半導体チップ１４を上方から見た平面断面図であり、図１のＡ−Ａ断面図に相当する。図３に示すように、第１半導体チップ１４は、その上面に、複数の第１接続電極１８が配置され、複数の第１ワイヤ２０と複数の第１接続端子１６を介して、基板１０と接続されている。   FIG. 3 is a plan sectional view of the first semiconductor chip 14 of the semiconductor device 1 as viewed from above, and corresponds to the AA sectional view of FIG. As shown in FIG. 3, the first semiconductor chip 14 has a plurality of first connection electrodes 18 disposed on the top surface thereof, and the substrate 10 via the plurality of first wires 20 and the plurality of first connection terminals 16. It is connected.

図中の破線は、図示されない接着部２２の第１接着層２２ａが存在する領域を示している。第２接着層２２ｂは、この図３に示すように、矩形状の第１接着層２２ａの４隅において、柱状となるように配置されている。さらに、第２接着層２２ｂ同士の間には、接着層を有しない開口部２２ｃがそれぞれ配置されている。接着部２２は、この開口部２２ｃにおいて、第１接着層２２ａの下部には接着層を有しないように形成されている。すなわち、接着部２２は、第１接着層２２ａを天板とし、第２接着層２２ｂを脚とするような机状に形成されている。また、第２接着層２２ｂは、図３に示すように、その一部において、第１接続端子１６及び第１ワイヤ２０と接触していてもよい。   A broken line in the drawing indicates a region where the first adhesive layer 22a of the bonding portion 22 (not shown) exists. As shown in FIG. 3, the second adhesive layer 22b is arranged in a columnar shape at the four corners of the rectangular first adhesive layer 22a. Furthermore, an opening 22c that does not have an adhesive layer is disposed between the second adhesive layers 22b. The adhesive portion 22 is formed in the opening 22c so as not to have an adhesive layer below the first adhesive layer 22a. That is, the bonding portion 22 is formed in a desk shape having the first bonding layer 22a as a top plate and the second bonding layer 22b as legs. Further, as shown in FIG. 3, the second adhesive layer 22 b may be in contact with the first connection terminal 16 and the first wire 20 in a part thereof.

このように構成された半導体装置１は、例えば、基板１０の下方に設けられた図示しないはんだボール等のインターフェースを介して、外部と接続される。外部から入力された信号は、第１半導体チップ１４により処理され、メモリにアクセスするための制御信号へと変換される。この第１半導体チップ１４が出力したメモリアクセスの制御信号により、第２半導体チップ２４上に配置されているメモリのデータの書込及び読出を行う。そして、このデータを外部とやりとりすることにより、本実施形態に係る半導体装置１は、例えば、メモリとして作用する。   The semiconductor device 1 configured as described above is connected to the outside via an interface such as a solder ball (not shown) provided below the substrate 10. An externally input signal is processed by the first semiconductor chip 14 and converted into a control signal for accessing the memory. In accordance with the memory access control signal output from the first semiconductor chip 14, the data in the memory arranged on the second semiconductor chip 24 is written and read. Then, by exchanging this data with the outside, the semiconductor device 1 according to the present embodiment functions as a memory, for example.

以上のように、本実施形態に係る半導体装置１の構造によれば、第１半導体チップ１４と第２半導体チップ２４との間に、机状の接着部２２を設置することにより、半導体パッケージが形成される。第１半導体チップ１４と、第１ワイヤ２０とが接続する領域に、接着部２２が接触しないことにより、この第１半導体チップ１４と第１ワイヤ２０との接続部における腐食を抑制することが可能となる。   As described above, according to the structure of the semiconductor device 1 according to the present embodiment, the desk-like bonding portion 22 is installed between the first semiconductor chip 14 and the second semiconductor chip 24, whereby the semiconductor package is formed. It is formed. Since the bonding portion 22 does not come into contact with the region where the first semiconductor chip 14 and the first wire 20 are connected, corrosion at the connecting portion between the first semiconductor chip 14 and the first wire 20 can be suppressed. It becomes.

例えば、第１接続電極１８は、ＡｕとＡｌの合金やＣｕとＡｌの合金で形成され、第１ワイヤ２０は、Ａｌで形成されるが、これらが接続する部分は、接着剤に含まれるＣｌイオン等の不純物により腐食する。本実施形態によれば、この第１接続電極１８と第１ワイヤ２０とが接続されている箇所は、接着部２２を構成する接着剤とは接触しないため、接触によるＣｌ等に起因する腐食を防ぐことができる。この結果、接着部２２を構成する接着剤のＣｌイオン濃度を低く抑える必要性が下がるため、素材の選択の自由度が高くなる。   For example, the first connection electrode 18 is formed of an alloy of Au and Al or an alloy of Cu and Al, and the first wire 20 is formed of Al, but a portion to which these are connected is Cl contained in an adhesive. Corrosion caused by impurities such as ions. According to the present embodiment, the portion where the first connection electrode 18 and the first wire 20 are connected does not come into contact with the adhesive constituting the bonding portion 22, so that corrosion caused by Cl or the like due to contact is prevented. Can be prevented. As a result, since it is necessary to keep the Cl ion concentration of the adhesive constituting the adhesive portion 22 low, the degree of freedom in selecting a material is increased.

また、第１接着層２２ａと第１半導体チップ１４との間がモールド材３４によって封止され、第１接着層２２ａと第１半導体チップ１４とが直接接触しないため、第１半導体チップ１４により押し上げられた接着部２２により第２半導体チップ２４に凹凸が生じることを抑制できる。すなわち、モールド形成をした後においても、基板１０の反りや凹凸を抑制することが可能となる。この結果、接着部２２を構成する接着剤の粘度を低く抑える必要がなくなり、半導体チップ同士を接着するために、粘度の高い接着剤、例えば、フィルム状の接着剤等を用いることが可能となる。   Further, the space between the first adhesive layer 22a and the first semiconductor chip 14 is sealed by the molding material 34, and the first adhesive layer 22a and the first semiconductor chip 14 are not in direct contact with each other. It is possible to prevent the second semiconductor chip 24 from being uneven due to the bonded portion 22. That is, even after the mold is formed, it is possible to suppress warpage and unevenness of the substrate 10. As a result, it is not necessary to keep the viscosity of the adhesive constituting the bonding part 22 low, and it is possible to use a high-viscosity adhesive, for example, a film-like adhesive, for bonding the semiconductor chips together. .

さらに、接着部２２は、絶縁材料からなる接着剤により構成されるので、第１半導体チップ１４と基板１０とを接続する第１ワイヤ２０と接触しても電気的にショートすることがない。この結果、第１半導体チップ１４と、第１接続端子１８と、第１ワイヤ２０と、接着部２２との位置関係を選択する自由度を高めることが可能となる。   Further, since the bonding portion 22 is made of an adhesive made of an insulating material, even if the bonding portion 22 contacts the first wire 20 that connects the first semiconductor chip 14 and the substrate 10, there is no electrical short circuit. As a result, it is possible to increase the degree of freedom in selecting the positional relationship among the first semiconductor chip 14, the first connection terminal 18, the first wire 20, and the bonding portion 22.

なお、接着部２２は、例えば、フィルム状の接着剤にスタンプ処理を施すことにより第１接着層２２ａと第２接着層２２ｂを形成することもできるし、フィルム状の接着剤をブレード加工などにより必要な箇所だけ薄膜化することにより形成することもできる。また、別々に作成された第１接着層２２ａと第２接着層２２ｂとを接着することにより接着部２２を形成することもできる。   In addition, the adhesive part 22 can also form the 1st adhesive layer 22a and the 2nd adhesive layer 22b, for example by giving a stamp process to a film-form adhesive, or a film-form adhesive is carried out by a blade process etc. It can also be formed by thinning only necessary portions. Moreover, the adhesion part 22 can also be formed by adhere | attaching the 1st contact bonding layer 22a and the 2nd contact bonding layer 22b produced separately.

（変形例）
以下、図を用いて開口部２２ｃの配置や大きさの違いによる、いくつかの変形例を示す。以下、図中において、図１乃至図３と同じ符号は同じものを示す符号であるので、詳しい説明は省略する。 (Modification)
Hereinafter, some modified examples depending on the arrangement and size of the opening 22c will be described with reference to the drawings. In the drawings, the same reference numerals as those in FIGS. 1 to 3 denote the same components, and detailed description thereof will be omitted.

図４Ａは、一変形例であり、上述した実施形態とは開口の大きさが異なる半導体装置１の正面図である。また、図４Ｂは、図４Ａに示すＡ−Ａ断面図である。この図４Ａに示すように、図１と比較すると、第２接着層２２ｂの正面から見た幅が狭くなり、開口部２２ｃの幅が広くなっている。上面から見たのが図４Ｂである。図３と比較すると、それぞれの第２接着層２２ｂの断面が、左右方向に狭くなり、上下方向に広くなっている。このような構造としても、上述した実施形態と同様の効果を得ることが可能である。   FIG. 4A is a front view of the semiconductor device 1 which is a modified example and has a different opening size from the above-described embodiment. 4B is a cross-sectional view taken along line AA shown in FIG. 4A. As shown in FIG. 4A, compared with FIG. 1, the width of the second adhesive layer 22b viewed from the front is narrower, and the width of the opening 22c is wider. FIG. 4B is a view from the top. Compared with FIG. 3, the cross section of each second adhesive layer 22b is narrower in the left-right direction and wider in the vertical direction. Even with such a structure, it is possible to obtain the same effects as those of the above-described embodiment.

図５Ａは、別の変形例であり、第１接着層２２ａの２対の対辺のうち、一方の対辺のそれぞれの下部において、開口部２２ｃを有しない構造とした半導体装置１の正面図である。この図５Ａに示すように、正面視において、接着部２２は、開口部２２ｃを有しない。図５Ｂは、図５Ａに示すＡ−Ａ断面図である。この図５Ｂに示すように、もう一方の対辺のそれぞれの下部において、開口部２２ｃを有している構造としている。すなわち、第１接着層２２ａの４隅の下部にある柱状の第２接着層２２ｂのうち、一方の対辺にあるそれぞれの第２接着層２２ｂの幅が広くなり、接続したものとなる。   FIG. 5A is another modification, and is a front view of the semiconductor device 1 having a structure in which the opening 22c is not provided in the lower part of one of the two pairs of opposite sides of the first adhesive layer 22a. . As shown in FIG. 5A, in the front view, the bonding portion 22 does not have the opening 22c. 5B is a cross-sectional view taken along the line AA shown in FIG. 5A. As shown in FIG. 5B, an opening 22c is provided at the lower portion of the other opposite side. That is, among the columnar second adhesive layers 22b at the bottom of the four corners of the first adhesive layer 22a, the width of each of the second adhesive layers 22b on one side is widened and connected.

図６Ａ及び図６Ｂは、さらに別の変形例であり、図５Ａ及び図５Ｂに示す半導体装置１とは、逆の対辺の下部において開口部２２ｃを有しない構造となっている。この図５Ａ、図５Ｂ、図６Ａ及び図６Ｂに示す半導体装置１のように、第１接着層２２ａの２対の対辺のうち、いずれかの対辺のそれぞれの下部に開口部２２ｃを有していれば、他方の対辺の下部には、開口部２２ｃを有しなくてもよい。   6A and 6B show still another modification example, and the semiconductor device 1 shown in FIGS. 5A and 5B has a structure that does not have the opening 22c in the lower part of the opposite side. Like the semiconductor device 1 shown in FIGS. 5A, 5B, 6A, and 6B, an opening 22c is provided at the lower part of one of the two opposite sides of the first adhesive layer 22a. If so, it is not necessary to have the opening 22c in the lower part of the other side.

なお、いずれの場合においても、第２接着層２２ｂは、第１接続端子１６上に重なるように構成されているが、これは一例であり、必ずしもこのように重なっている必要はない。また、上述したように変形例を示したが、いずれの場合においても、第１接着層２２ａの２対の対辺のうち、少なくとも一方の対辺のそれぞれの下部には、開口部２２ｃを有している。このようにすることにより、モールド材３４をウエハ上に流し込む際に、モールド材が隅々まで行き渡ることが可能となる。   In any case, the second adhesive layer 22b is configured to overlap the first connection terminal 16, but this is an example, and it is not always necessary to overlap in this manner. Moreover, although the modification was shown as mentioned above, in any case, the opening 22c is provided in each lower part of at least one of the two pairs of opposite sides of the first adhesive layer 22a. Yes. In this way, when the molding material 34 is poured onto the wafer, the molding material can reach every corner.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。また、当然のことながら、本発明の要旨の範囲内で、これらの実施の形態を部分的に適宜組み合わせることも可能である。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof. Of course, it is possible to appropriately combine these embodiments partially within the scope of the present invention.

１：半導体装置、１０：基板、１４：第１導電体チップ、１６：第１接続端子、１８：第１接続電極、２０：第１ワイヤ、２２：接着部、２２ａ：第１接着層、２２ｂ：第２接着層、２２ｃ：開口部、２４：第２導電体チップ、２８：第２接続端子、３０：第２接続電極、３２：第２ワイヤ、３４：モールド材 DESCRIPTION OF SYMBOLS 1: Semiconductor device, 10: Board | substrate, 14: 1st conductor chip, 16: 1st connection terminal, 18: 1st connection electrode, 20: 1st wire, 22: adhesion part, 22a: 1st adhesion layer, 22b : Second adhesive layer, 22c: opening, 24: second conductor chip, 28: second connection terminal, 30: second connection electrode, 32: second wire, 34: molding material

Claims (2)

接続端子を有する基板上に第１半導体チップを設け、
前記接続端子と、前記第１半導体チップ上の接続電極とをワイヤにて接続し、
矩形状の第１接着層と、前記第１接着層の四隅に位置し前記第１接着層における２対の
対辺のうち少なくとも１対の対辺のそれぞれの下部に開口部が形成された柱状の第２接着
層と、を有する接着部をフィルム状の絶縁材料の接着剤をスタンプすることで形成し、
前記接着部を、前記第２接着層の一部が前記ワイヤ及び前記接続端子に接触し、前記接
続電極とは接触しないように前記第１半導体チップの上に設け、
前記接着部の上に第２半導体チップを設け、
前記接着部と前記第１半導体チップとの間を含む領域をモールド材で封止し、
前記ワイヤの前記接続電極からの最大高さが前記接続電極と前記第１接着層との間隔よ
りも小さくなる、半導体装置の製造方法。 Providing a first semiconductor chip on a substrate having connection terminals;
Connecting the connection terminal and the connection electrode on the first semiconductor chip with a wire;
A rectangular first adhesive layer and columnar first adhesives located at the four corners of the first adhesive layer and having openings formed at the lower portions of at least one pair of opposite sides of the first adhesive layer. Forming an adhesive portion having two adhesive layers by stamping an adhesive of a film-like insulating material;
The bonding portion is provided on the first semiconductor chip so that a part of the second bonding layer is in contact with the wire and the connection terminal and is not in contact with the connection electrode.
A second semiconductor chip is provided on the adhesive portion,
A region including a space between the adhesive portion and the first semiconductor chip is sealed with a molding material,
A method for manufacturing a semiconductor device, wherein a maximum height of the wire from the connection electrode is smaller than a distance between the connection electrode and the first adhesive layer. 接続端子を有する基板上に第１半導体チップを設け、
前記接続端子と、前記第１半導体チップ上の接続電極とをワイヤにて接続し、
矩形状の第１接着層と、前記第１接着層の四隅に位置し前記第１接着層における２対の
対辺のうち少なくとも１対の対辺のそれぞれの下部に開口部が形成された柱状の第２接着
層と、を有する接着部をフィルム状の接着剤をブレード加工により必要な箇所だけ薄膜化
することで形成し、
前記接着部を、前記第２接着層の一部が前記ワイヤ及び前記接続端子に接触し、前記接
続電極とは接触しないように前記第１半導体チップの上に設け、
前記接着部の上に第２半導体チップを設け、
前記接着部と前記第１半導体チップとの間を含む領域をモールド材で封止し、
前記ワイヤの前記接続電極からの最大高さが前記接続電極と前記第１接着層との間隔よ
りも小さくなる、半導体装置の製造方法。 Providing a first semiconductor chip on a substrate having connection terminals;
Connecting the connection terminal and the connection electrode on the first semiconductor chip with a wire;
A rectangular first adhesive layer and columnar first adhesives located at the four corners of the first adhesive layer and having openings formed at the lower portions of at least one pair of opposite sides of the first adhesive layer. 2 Adhesive layer, and adhesive part with film-like adhesive is thinned only where necessary by blade processing
To form,
The bonding portion is provided on the first semiconductor chip so that a part of the second bonding layer is in contact with the wire and the connection terminal and is not in contact with the connection electrode.
A second semiconductor chip is provided on the adhesive portion,
A region including a space between the adhesive portion and the first semiconductor chip is sealed with a molding material,
A method for manufacturing a semiconductor device, wherein a maximum height of the wire from the connection electrode is smaller than a distance between the connection electrode and the first adhesive layer.
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