KR20110055985A - Stack package - Google Patents

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KR20110055985A
KR20110055985A KR1020090112634A KR20090112634A KR20110055985A KR 20110055985 A KR20110055985 A KR 20110055985A KR 1020090112634 A KR1020090112634 A KR 1020090112634A KR 20090112634 A KR20090112634 A KR 20090112634A KR 20110055985 A KR20110055985 A KR 20110055985A
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South Korea
Prior art keywords
bonding
semiconductor chip
bump
stack package
substrate
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KR1020090112634A
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Korean (ko)
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이웅선
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주식회사 하이닉스반도체
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Priority to KR1020090112634A priority Critical patent/KR20110055985A/en
Publication of KR20110055985A publication Critical patent/KR20110055985A/en

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Abstract

PURPOSE: A stack package is provided to improve the degree of freedom of bonding a wire by reducing the length and height of the bonding wire. CONSTITUTION: In a stack package, a connection pad(312) and a ball land(314) are formed on the top and bottom of a substrate. A first semiconductor chip(320) comprises a first bonding pad(322) in the top side. A second semiconductor chip(330) comprises a second bonding pad(332) in the top side. A third semiconductor chip(340) comprises a third bonding pad(342) in top side. A fourth semiconductor chip(350) comprises a fourth bonding pad(352) in top side.

Description

스택 패키지{STACK PACKAGE}Stack Package {STACK PACKAGE}

본 발명은 스택 패키지에 관한 것으로, 보다 상세하게는 본딩 와이어의 길이를 줄이기에 적합한 스택 패키지에 관한 것이다.The present invention relates to a stack package, and more particularly to a stack package suitable for reducing the length of the bonding wire.

전기·전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. 고용량의 반도체 모듈을 제공하기 위한 방법으로는 메모리 칩의 용량 증대, 다시 말해 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. 그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등 고난도의 기술과 많은 개발시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(stack) 기술이 제안되었다.As miniaturization of electric and electronic products and high performance are required, various technologies for providing high capacity semiconductor modules have been researched and developed. A method for providing a high-capacity semiconductor module may include increasing the capacity of a memory chip, that is, high integration of the memory chip, and this high integration may be realized by integrating a larger number of cells in a limited space of a semiconductor chip. Can be. However, the high integration of such a memory chip requires a high level of technology and a lot of development time, such as requiring precise fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

이러한 스택 기술은, 적어도 2개 이상의 반도체 칩을 수직으로 쌓아 올리는 것으로서, 이러한 스택 기술에 의한 스택 패키지는 메모리 용량 증대는 물론, 실장 밀도 및 실장 면적 사용의 효율성 측면에서 이점이 있다.The stack technology stacks at least two semiconductor chips vertically, and the stack package by the stack technology has advantages in terms of increasing memory capacity, as well as efficiency of mounting density and mounting area.

도 1은 종래 기술에 따른 스택 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a stack package according to the prior art.

도 1을 참조하면, 스택 패키지는 적어도 2개 이상의 반도체 칩(110)들이 기판(120) 상에 접착제(114)를 매개로 스택되고, 각 반도체 칩(110)의 본딩 패드(112)와 기판(120)의 접속 패드(122)가 본딩 와이어(116)를 통해 전기적으로 연결된다.Referring to FIG. 1, a stack package includes at least two semiconductor chips 110 stacked on the substrate 120 through an adhesive 114, and bonding pads 112 and substrates (eg, each semiconductor chip 110). The connection pads 122 of 120 are electrically connected through the bonding wires 116.

그리고, 반도체 칩(110)들을 포함한 기판(120) 상부면은 봉지부(190)에 의해 밀봉되고, 기판(120) 하부면에 형성된 볼랜드(124)에는 솔더볼(170)이 장착된다.The upper surface of the substrate 120 including the semiconductor chips 110 is sealed by the encapsulation portion 190, and the solder ball 170 is mounted on the ball land 124 formed on the lower surface of the substrate 120.

본딩 와이어(116)는 반도체 칩(110)들 측면과의 숏트를 방지하기 위한 공간을 마련하기 위하여 반도체 칩(110) 상부에 루프(loop)를 갖는다. 스택되는 반도체 칩(110)의 개수가 늘어나면 본딩 패드(112)와 접속 패드(122)간 높이 차이가 커지게 되므로, 루프(loop)의 높이를 증가시켜야 한다. The bonding wire 116 has a loop on the semiconductor chip 110 to provide a space for preventing a short with the side surfaces of the semiconductor chips 110. As the number of stacked semiconductor chips 110 increases, the height difference between the bonding pads 112 and the connection pads 122 increases, so the height of the loop must be increased.

하지만, 루프의 높이가 증가되면 루프가 상부에 위치하는 반도체 칩과 접촉되는 불량이 발생되는 바, 루프의 높이를 높이는 대신에 본딩 와이어(116)를 반도체 칩(110)의 측면으로 길게 형성하여 본딩 와이어(116)가 반도체 칩(110)의 측면과 숏트되는 문제를 방지하고 있다.However, when the height of the loop is increased, defects in contact with the semiconductor chip positioned at the upper part of the loop may occur. Instead of increasing the height of the loop, the bonding wire 116 is formed to be long on the side of the semiconductor chip 110 to bond the same. The problem that the wire 116 is shorted with the side surface of the semiconductor chip 110 is prevented.

그러나, 이와 같이 반도체 칩(110) 측면으로 본딩 와이어(116)를 길게 형성하면, 본딩 와이어(116)가 지나가는 면적을 확보해야 하므로 패키지의 사이즈가 증가되고, 본딩 와이어(116)가 꼬이거나 본딩 와이어(116)들끼리 숏트(short)되는 등의 전기적인 불량(fail)이 유발된다.However, when the bonding wire 116 is formed long on the side of the semiconductor chip 110 as described above, the size of the package is increased because the area where the bonding wire 116 passes is increased, and the bonding wire 116 is twisted or bonded to the bonding wire 116. Electrical failures such as shorting between the 116 are caused.

본 발명은, 본딩 와이어로 인한 패키지 사이즈 증가를 감소시키어 경박단소한 새로운 형태를 갖는 스택 패키지를 제공하는데, 그 목적이 있다.It is an object of the present invention to provide a stack package having a novel form that is light and thin by reducing the increase in package size due to the bonding wire.

본 발명의 다른 목적은, 본딩 와이어 결선의 자유도를 높이고 본딩 와이어들이 숏트되는 불량을 방지할 수 있는 스택 패키지를 제공하는데, 있다.Another object of the present invention is to provide a stack package capable of increasing the degree of freedom of bonding wire connection and preventing a defect in which the bonding wires are shorted.

본 발명의 실시예에 따른 스택 패키지는, 상면에 접속 패드가 형성된 기판과, 상면에 본딩 패드를 구비하며 상기 접속 패드 일측의 상기 기판 상면에 상기 본딩 패드가 노출되도록 계단 형태로 스택된 적어도 2개 이상의 반도체 칩들과, 상기 반도체 칩들 중 최상부에 위치하는 반도체 칩을 제외한 나머지 반도체 칩들의 상기 본딩 패드들 및 상기 기판의 상기 접속 패드상에 각각 형성되며 적어도 1개 이상의 범프가 적층된 구조의 범프군(群)들과, 상기 최상부에 위치하는 반도체 칩의 본딩 패드와 상기 범프군들을 전기적으로 연결하는 본딩 와이어를 포함하는 것을 특징으로 한다.According to an embodiment of the present invention, a stack package includes a substrate having a connection pad formed on an upper surface thereof, and a bonding pad disposed on an upper surface thereof, and at least two stacked stacks in a step shape such that the bonding pads are exposed on an upper surface of the substrate on one side of the connection pad. A bump group having a structure in which at least one bump is stacked and formed on the bonding pads of the semiconductor chips and the connection pads of the substrate except for the semiconductor chips and the semiconductor chips positioned at the top of the semiconductor chips. Iii) and a bonding wire for electrically connecting the bonding pad of the semiconductor chip positioned at the top and the bump groups.

상기 범프군들은, 상기 접속 패드 상에 형성된 것이 가장 높은 높이로 형성되고, 상층으로 갈수록 점차 감소되는 높이로 형성되어, 상기 최상부에 위치하는 반도체 칩 바로 아래에 있는 반도체 칩의 본딩 패드 상에 형성된 것이 가장 낮은 높이로 형성된 것을 특징으로 한다. The bump groups are formed on the connection pads at the highest height, and are formed at a height that gradually decreases toward the upper layer, and are formed on the bonding pads of the semiconductor chip directly below the semiconductor chip located at the top. Characterized in the lowest height.

상기 범프 및 상기 본딩 와이어는 동일한 물질로 형성되는 것을 특징으로 한 다.The bump and the bonding wire are formed of the same material.

상기 물질은, 금, 은, 솔더 및 구리로 이루어진 군으로부터 선택된 적어도 하나를 포함하는 것을 특징으로 한다.The material is characterized in that it comprises at least one selected from the group consisting of gold, silver, solder and copper.

상기 범프는, 금, 은, 솔더 및 구리로 이루어진 군으로부터 선택된 적어도 하나를 포함하는 것을 특징으로 한다.The bump is characterized in that it comprises at least one selected from the group consisting of gold, silver, solder and copper.

상기 본딩 와이어는, 금, 은, 솔더 및 구리로 이루어진 군으로부터 선택된 적어도 하나를 포함하는 것을 특징으로 한다.The bonding wire is characterized in that it comprises at least one selected from the group consisting of gold, silver, solder and copper.

본 발명에 따르면, 본딩 와이어의 길이 및 루프 높이가 감소되므로 본딩 와이어 결선의 자유도가 향상되고, 본딩 와이어들간 접촉에 따른 불량이 방지된다. 또한, 본딩 와이어로 인한 스택 패키지의 사이즈 증가가 감소되므로 스택 패키지의 경박단소화를 이룰 수 있다.According to the present invention, since the length of the bonding wire and the loop height are reduced, the degree of freedom of bonding wire connection is improved, and defects due to contact between the bonding wires are prevented. In addition, since the size increase of the stack package due to the bonding wire is reduced, the stack package can be made thin and light.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도이다.2 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도 2를 참조하면, 본 발명의 실시예에 따른 스택 패키지는, 기판(310), 제 1 내지 제 4 반도체 칩(320, 330, 340, 350), 제 1 내지 제 4 범프군(群)(360, 370, 380, 390) 및 본딩 와이어(400)를 포함한다. 2, a stack package according to an exemplary embodiment of the present invention may include a substrate 310, first to fourth semiconductor chips 320, 330, 340, and 350, and a first to fourth bump group ( 360, 370, 380, 390 and bonding wires 400.

그 외에, 봉지부(410) 및 외부접속단자(420)를 더 포함할 수 있다.In addition, the sealing unit 410 and the external connection terminal 420 may be further included.

기판(310)은 플레이트 형상을 가질 수 있다. 플레이트 형상을 갖는 기판(310)은 상면 및 상면과 대향하는 하면을 갖는다.The substrate 310 may have a plate shape. The substrate 310 having a plate shape has an upper surface and a lower surface opposing the upper surface.

기판(310)의 상면에는 접속 패드(312)가 형성되고, 하면에는 볼랜드(314)가 형성된다. The connection pad 312 is formed on the upper surface of the substrate 310, and the ball land 314 is formed on the lower surface of the substrate 310.

제 1 반도체 칩(320)은 상면에 제 1 본딩 패드(322)를 구비하며, 기판(310)의 접속 패드(312)가 노출되도록 제 1 접착부재(324)를 매개로 기판(310) 상면에 부착된다. The first semiconductor chip 320 includes a first bonding pad 322 on an upper surface of the first semiconductor chip 320 and an upper surface of the substrate 310 through the first adhesive member 324 to expose the connection pad 312 of the substrate 310. Attached.

제 2 반도체 칩(330)은 상면에 제 2 본딩 패드(332)를 구비하며, 제 1 반도체 칩(320)의 제 1 본딩 패드(322)가 노출되도록 제 2 접착부재(334)를 매개로 제 1 반도체 칩(320) 상면에 부착된다.The second semiconductor chip 330 includes a second bonding pad 332 on an upper surface thereof, and is formed through the second adhesive member 334 to expose the first bonding pad 322 of the first semiconductor chip 320. 1 is attached to the upper surface of the semiconductor chip 320.

제 3 반도체 칩(340)은 상면에 제 3 본딩 패드(342)를 구비하며, 제 2 반도체 칩(330)의 제 2 본딩 패드(332)가 노출되도록 제 3 접착부재(344)를 매개로 제 2 반도체 칩(330) 상면에 부착된다.The third semiconductor chip 340 includes a third bonding pad 342 on an upper surface thereof, and is formed through the third adhesive member 344 to expose the second bonding pad 332 of the second semiconductor chip 330. 2 is attached to the upper surface of the semiconductor chip 330.

제 4 반도체 칩(350)은 상면에 제 4 본딩 패드(352)를 구비하며, 제 3 반도체 칩(340)의 제 3 본딩 패드(342)가 노출되도록 제 4 접착부재(354)를 매개로 제 3 반도체 칩(340) 상면에 부착된다.The fourth semiconductor chip 350 includes a fourth bonding pad 352 on an upper surface thereof, and is formed through the fourth adhesive member 354 to expose the third bonding pad 342 of the third semiconductor chip 340. 3 is attached to the upper surface of the semiconductor chip 340.

제 1 범프군(360)은 기판(310)의 접속 패드(312) 상에 형성된다. The first bump group 360 is formed on the connection pad 312 of the substrate 310.

그리고, 제 2 내지 제 4 범프군(370, 380, 390)은 각각 제 1 내지 제 3 반도체 칩(320, 330, 340)의 제 1 내지 제 3 본딩 패드(322, 332, 342) 상에 형성된다.The second to fourth bump groups 370, 380, and 390 are formed on the first to third bonding pads 322, 332, and 342 of the first to third semiconductor chips 320, 330, and 340, respectively. do.

제 1 내지 제 4 범프군(360, 370, 380, 390)은 접속 패드, 제 1 내지 제3 본딩 패드(312, 322, 332, 342)와 제 4 반도체 칩(350)의 제 4 본딩 패드(352)간 높이 차이를 보상하기 위한 것으로, 가장 하층에 형성되는 제 1 범프군(360)이 가장 높은 높이로 형성되고, 그 다음으로 제 2 범프군(370), 제 3 범프군(380)으로 갈수록 높이가 낮아져, 가장 상층에 위치하는 제 4 범프군(390)이 가장 낮은 높이로 형성된다.The first to fourth bump groups 360, 370, 380, and 390 may include connection pads, first to third bonding pads 312, 322, 332, and 342, and fourth bonding pads of the fourth semiconductor chip 350 ( 352 to compensate for the difference in height, and the first bump group 360 formed at the lowest layer is formed at the highest height, and then the second bump group 370 and the third bump group 380. As the height is lowered gradually, the fourth bump group 390 positioned at the uppermost layer is formed at the lowest height.

제 1 내지 제 4 범프군(360, 370, 380, 390)은 적어도 하나 이상의 범프가 수직하게 스택된 구조를 갖는다.The first to fourth bump groups 360, 370, 380, and 390 have a structure in which at least one bump is vertically stacked.

예컨데, 제 1 내지 제 2 반도체 칩(320, 330, 340, 350)의 두께가 50㎛이고, 범프 하나의 높이가 40㎛인 경우에, 제 1 범프군(360)은 수직하게 스택된 4개의 범프들로 구성되고, 제 2 범프군(370)는 수직하게 스택된 3개의 범프들로 구성되고, 제 3 범프군(380)은 수직하게 스택된 2개의 범프들로 구성되며, 제 4 범프군(390)는 1개의 범프로 구성될 수 있다.For example, when the thicknesses of the first to second semiconductor chips 320, 330, 340, and 350 are 50 μm, and the height of one bump is 40 μm, the first bump groups 360 may be vertically stacked into four groups. The second bump group 370 consists of three bumps vertically stacked, and the third bump group 380 consists of two bumps vertically stacked, and the fourth bump group 390 may consist of one bump.

본 실시예에서, 제 1 내지 제 4 범프군(360, 370, 380, 390)을 구성하는 범프는 금(Au), 은(Ag), 솔더(solder) 및 구리(Cu) 중 적어도 어느 하나로 형성될 수 있다.In the present embodiment, the bumps constituting the first to fourth bump groups 360, 370, 380, and 390 are formed of at least one of gold (Au), silver (Ag), solder, and copper (Cu). Can be.

본딩 와이어(400)는 최상부에 위치하는 제 4 반도체 칩(350)의 제 4 본딩 패드(352)와 제 1 내지 제 4 범프군(360, 370, 380, 390)을 전기적으로 연결한다.The bonding wire 400 electrically connects the fourth bonding pads 352 of the fourth semiconductor chip 350 and the first to fourth bump groups 360, 370, 380, and 390 positioned at the top thereof.

본 실시예에서 본딩 와이어(400)는, 금(Au), 은(Ag), 솔더(solder) 및 구리(Cu) 중 적어도 어느 하나로 형성될 수 있다.In the present embodiment, the bonding wire 400 may be formed of at least one of gold (Au), silver (Ag), solder, and copper (Cu).

상기 범프 및 본딩 와이어(400)는 동일한 물질로 형성될 수 있다. The bump and bonding wire 400 may be formed of the same material.

예컨데, 범프 및 본딩 와이어(400)는 금(Au), 은(Ag), 솔더(solder) 및 구리(Cu) 중 적어도 어느 하나로 형성될 수 있다.For example, the bump and bonding wires 400 may be formed of at least one of gold (Au), silver (Ag), solder, and copper (Cu).

제 1 내지 제 4 범프군(360, 370, 380, 390)에 의해 칩 스택에 따른 연결 단자들(접속 패드, 제 1 내지 제 4 본딩 패드)간 높이 차이가 보상됨에 따라서, 본딩 와이어(400)의 루프 높이 및 본딩 와이어(400)의 길이는 종래에 비해 감소된다.As the height difference between the connection terminals (connection pads and the first to fourth bonding pads) according to the chip stack is compensated by the first to fourth bump groups 360, 370, 380, and 390, the bonding wire 400 The loop height and the length of the bonding wire 400 is reduced compared to the prior art.

그리고, 제 1 내지 제 4 반도체 칩(320, 330, 340, 350)을 포함한 기판(310) 상부면은 봉지부(410)에 의해 몰딩되고, 기판(310) 하면의 볼랜드(314)에는 외부와의 전기적 접속을 이루기 위하여 솔더볼(solder ball)과 같은 외부접속단자(420)가 부착된다.In addition, the upper surface of the substrate 310 including the first to fourth semiconductor chips 320, 330, 340, and 350 is molded by the encapsulation portion 410, and the ball land 314 on the lower surface of the substrate 310 has an external surface. An external connection terminal 420, such as a solder ball, is attached to achieve electrical connection of the same.

전술한 실시예에서는, 기판 상에 적층되는 반도체 칩의 개수가 4개인 경우에 한하여 설명하였으나, 본 발명은 이에 한정되지 않으며 기판 상에 적층되는 반도체 칩의 개수가 2개 이상인 모든 경우에 적용 가능하다.In the above-described embodiment, the present invention has been described only in the case where the number of semiconductor chips stacked on the substrate is four, but the present invention is not limited thereto, and the present invention is applicable to all cases in which the number of semiconductor chips stacked on the substrate is two or more. .

이상에서 상세하게 설명한 바에 의하면, 본딩 와이어의 길이 및 루프 높이가 감소되므로 본딩 와이어 결선의 자유도가 향상되고, 본딩 와이어들간 접촉에 따른 불량이 방지된다. 또한, 본딩 와이어로 인한 스택 패키지의 사이즈 증가가 감소되므로 스택 패키지의 경박단소화를 이룰 수 있다.As described above in detail, since the length and the loop height of the bonding wire are reduced, the degree of freedom of bonding wire connection is improved, and defects due to contact between the bonding wires are prevented. In addition, since the size increase of the stack package due to the bonding wire is reduced, the stack package can be made thin and light.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

도 1은 종래 기술에 따른 스택 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a stack package according to the prior art.

도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도이다.2 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

<도면의 주요부분에 대한 설명><Description of main parts of drawing>

310 : 기판310: substrate

320, 330, 340, 350 : 제 1 내지 제 4 반도체 칩320, 330, 340, 350: first to fourth semiconductor chips

360, 370, 380, 390 : 제 1 내지 제 4 범프군360, 370, 380, 390: first to fourth bump groups

400 : 도전성 연결부재400: conductive connecting member

410 : 봉지부410: encapsulation

420 : 외부접속단자420: external connection terminal

Claims (6)

상면에 접속 패드가 형성된 기판;A substrate having a connection pad formed on an upper surface thereof; 상면에 본딩 패드를 구비하며 상기 접속 패드 일측의 상기 기판 상면에 상기 본딩 패드가 노출되도록 계단 형태로 스택된 적어도 2개 이상의 반도체 칩들;At least two semiconductor chips having a bonding pad on an upper surface thereof and stacked in a step shape such that the bonding pad is exposed on an upper surface of the substrate on one side of the connection pad; 상기 반도체 칩들 중 최상부에 위치하는 반도체 칩을 제외한 나머지 반도체 칩들의 상기 본딩 패드들 및 상기 기판의 상기 접속 패드상에 각각 형성되며 적어도 1개 이상의 범프가 적층된 구조의 범프군(群)들;Bump groups having a structure in which at least one bump is formed on the bonding pads of the remaining semiconductor chips and the connection pads of the substrate except for the semiconductor chip positioned at the top of the semiconductor chips; 상기 최상부에 위치하는 반도체 칩의 본딩 패드와 상기 범프군들을 전기적으로 연결하는 본딩 와이어;A bonding wire electrically connecting the bonding pad of the semiconductor chip positioned at the uppermost portion with the bump groups; 를 포함하는 것을 특징으로 하는 스택 패키지.Stack package comprising a. 제 1항에 있어서,The method of claim 1, 상기 범프군들은, 상기 접속 패드 상에 형성된 것이 가장 높은 높이로 형성되고, 상층으로 갈수록 점차 감소되는 높이로 형성되어, 상기 최상부에 위치하는 반도체 칩 바로 아래에 있는 반도체 칩의 본딩 패드 상에 형성된 것이 가장 낮은 높이로 형성된 것을 특징으로 하는 스택 패키지.The bump groups are formed on the connection pads at the highest height, and are formed at a height that gradually decreases toward the upper layer, and are formed on the bonding pads of the semiconductor chip directly below the semiconductor chip located at the top. Stack package, characterized in that formed at the lowest height. 제 1항에 있어서,The method of claim 1, 상기 범프 및 상기 본딩 와이어는 동일한 물질로 형성되는 것을 특징으로 하 는 스택 패키지.And the bump and the bonding wire are formed of the same material. 제 3항에 있어서,The method of claim 3, wherein 상기 물질은, 금, 은, 솔더 및 구리로 이루어진 군으로부터 선택된 적어도 하나를 포함하는 것을 특징으로 하는 스택 패키지.And the material comprises at least one selected from the group consisting of gold, silver, solder and copper. 제 1항에 있어서,The method of claim 1, 상기 범프는, 금, 은, 솔더 및 구리로 이루어진 군으로부터 선택된 적어도 하나를 포함하는 것을 특징으로 하는 스택 패키지.The bumps may include at least one selected from the group consisting of gold, silver, solder, and copper. 제 1항에 있어서,The method of claim 1, 상기 본딩 와이어는, 금, 은, 솔더 및 구리로 이루어진 군으로부터 선택된 적어도 하나를 포함하는 것을 특징으로 하는 스택 패키지.The bonding wire, stack package, characterized in that it comprises at least one selected from the group consisting of gold, silver, solder and copper.
KR1020090112634A 2009-11-20 2009-11-20 Stack package KR20110055985A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952549B2 (en) 2012-02-08 2015-02-10 Samsung Electronics Co., Ltd. Semiconductor packages and methods of manufacturing the same
CN107611099A (en) * 2016-07-12 2018-01-19 晟碟信息科技（上海）有限公司 Semiconductor device is fanned out to including multiple semiconductor bare chips
CN109860165A (en) * 2018-12-29 2019-06-07 广东晶科电子股份有限公司 A kind of LED component and preparation method thereof
US11450634B2 (en) 2020-07-10 2022-09-20 Samsung Electronics Co., Ltd. Package substrate and semiconductor package with elevated bonding pad, and comprising the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952549B2 (en) 2012-02-08 2015-02-10 Samsung Electronics Co., Ltd. Semiconductor packages and methods of manufacturing the same
US9171821B2 (en) 2012-02-08 2015-10-27 Samsung Electronics Co., Ltd. Semiconductor packages and methods of manufacturing the same
CN107611099A (en) * 2016-07-12 2018-01-19 晟碟信息科技（上海）有限公司 Semiconductor device is fanned out to including multiple semiconductor bare chips
CN109860165A (en) * 2018-12-29 2019-06-07 广东晶科电子股份有限公司 A kind of LED component and preparation method thereof
US11450634B2 (en) 2020-07-10 2022-09-20 Samsung Electronics Co., Ltd. Package substrate and semiconductor package with elevated bonding pad, and comprising the same

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