KR101195460B1 - Stacked semiconductor package - Google Patents

Stacked semiconductor package Download PDF

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Publication number
KR101195460B1
KR101195460B1 KR1020100000778A KR20100000778A KR101195460B1 KR 101195460 B1 KR101195460 B1 KR 101195460B1 KR 1020100000778 A KR1020100000778 A KR 1020100000778A KR 20100000778 A KR20100000778 A KR 20100000778A KR 101195460 B1 KR101195460 B1 KR 101195460B1
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South Korea
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substrate
semiconductor chip
protrusions
semiconductor
bonding
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KR1020100000778A
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Korean (ko)
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KR20110080515A (en
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양경모
김재면
김승지
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에스케이하이닉스 주식회사
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

적층 반도체 패키지가 개시되어 있다. 개시된 적층 반도체 패키지는, 상면에 접속 패드들이 형성된 기판과, 상기 기판 상면에 상기 접속 패드들이 노출되도록 적층되며, (ⅰ)상기 기판과 대향하는 일면, 상기 기판과 대응하는 타면, 상기 일면 및 상기 타면을 연결하는 측면을 가지며 상기 측면 중 적어도 일부분이 톱니 형태로 절단되어 가장자리를 따라서 복수개의 돌출부들이 형성된 반도체 칩 몸체, (ⅱ)상기 돌출부들의 상기 일면에 형성되는 본딩 패드들을 포함하는 적어도 2개 이상의 반도체 칩들과, 상기 기판의 상기 접속 패드들과 상기 기판과 인접한 반도체 칩의 상기 본딩 패드들 사이 및 인접하는 상기 반도체 칩들의 본딩 패드들 사이를 연결하는 본딩 와이어들을 포함하며, 상기 인접하는 반도체 칩들 중 상부에 위치하는 반도체 칩의 돌출부들과 하부의 반도체 칩의 돌출부들은 상호 엇갈리도록 형성된 것을 특징으로 한다. 본 발명에 따르면, 본딩 와이어의 길이가 감소되고, 본딩 와이어로 인한 패키지의 사이즈 증가가 감소되므로, 경박단소화된 새로운 형태의 적층 반도체 패키지를 제공할 수 있다.Laminated semiconductor packages are disclosed. The disclosed stacked semiconductor package includes a substrate having connection pads formed on an upper surface thereof, and stacked so that the connection pads are exposed on an upper surface of the substrate, and (i) one surface facing the substrate, the other surface corresponding to the substrate, the one surface and the other surface. At least two semiconductors, each having a side surface connecting at least a portion of the side surface and having a plurality of protrusions formed along the edge thereof, and (ii) bonding pads formed on one surface of the protrusions. Chips and bonding wires connecting between the connection pads of the substrate and the bonding pads of the semiconductor chip adjacent to the substrate and between the bonding pads of the adjacent semiconductor chips, an upper portion of the adjacent semiconductor chips. The protrusions of the semiconductor chip and the protrusions of the lower semiconductor chip are located at It is characterized in that the arc is formed staggered. According to the present invention, since the length of the bonding wire is reduced and the increase in size of the package due to the bonding wire is reduced, it is possible to provide a new type of laminated semiconductor package which is light and short.

Description

적층 반도체 패키지{STACKED SEMICONDUCTOR PACKAGE}Multilayer Semiconductor Packages {STACKED SEMICONDUCTOR PACKAGE}

본 발명은 적층 반도체 패키지에 관한 것으로, 보다 상세하게는 경박단소한 새로운 형태의 적층 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated semiconductor package, and more particularly, to a laminated semiconductor package of a novel form that is light and simple.

전기?전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. 고용량의 반도체 모듈을 제공하기 위한 방법으로는 메모리 칩의 용량 증대, 다시 말해, 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. 그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등 고난도의 기술과 많은 개발시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 적층(stack) 기술이 제안되었다.As miniaturization of electric and electronic products and high performance is required, various technologies for providing high capacity semiconductor modules have been researched and developed. A method for providing a high-capacity semiconductor module includes increasing the capacity of the memory chip, that is, high integration of the memory chip, which can be realized by integrating a larger number of cells in a limited semiconductor chip space. Can be. However, the high integration of such a memory chip requires a high level of technology and a lot of development time, such as requiring precise fine line width. Therefore, a stacking technique has been proposed as another method for providing a high capacity semiconductor module.

적층 기술은 적어도 2개 이상의 반도체 칩 또는 반도체 패키지를 수직으로 쌓아 올리는 것으로서, 이러한 적층 기술에 의한 적층 반도체 패키지는 메모리 용량 증대는 물론, 실장 밀도 및 실장 면적 사용의 효율성 측면에서 이점이 있다.The stacking technology stacks at least two semiconductor chips or semiconductor packages vertically, and the stacking semiconductor package by the stacking technology has advantages in terms of increasing memory capacity and efficiency of mounting density and mounting area.

도 1은 종래 기술에 따른 적층 반도체 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a laminated semiconductor package according to the prior art.

도 1을 참조하면, 적층 반도체 패키지는 적어도 2개 이상의 반도체 칩(110)들이 기판(120) 상에 접착제(114)를 매개로 적층되고, 각 반도체 칩(110)의 본딩 패드(112)와 기판(120)의 접속 패드(122)가 본딩 와이어(116)를 통해 전기적으로 연결된다.Referring to FIG. 1, at least two semiconductor chips 110 are stacked on the substrate 120 through an adhesive 114, and the bonding pads 112 and the substrate of each semiconductor chip 110 are stacked. The connection pads 122 of 120 are electrically connected through the bonding wires 116.

그리고, 반도체 칩(110)들을 포함한 기판(120) 상면은 봉지부(190)에 의해 밀봉되고, 기판(120) 하면에 형성된 볼랜드(124)에는 솔더볼(170)이 장착된다.The upper surface of the substrate 120 including the semiconductor chips 110 is sealed by the encapsulation portion 190, and the solder ball 170 is mounted on the ball land 124 formed on the lower surface of the substrate 120.

본딩 와이어(116)는 반도체 칩(110)들 측면과의 숏트를 방지하기 위한 공간을 마련하기 위하여, 반도체 칩(110) 상부에 루프(loop)를 갖는다. The bonding wire 116 has a loop on the semiconductor chip 110 to provide a space for preventing a short with the side surfaces of the semiconductor chips 110.

적층되는 반도체 칩(110)의 개수가 늘어나면, 본딩 패드(112)와 접속 패드(122)간 높이 차이가 커지게 되므로 루프(loop)의 높이를 증가시켜야 한다. 하지만, 루프의 높이가 증가되면 루프가 상부에 위치하는 반도체 칩과 접촉되는 불량이 발생되는 바, 루프의 높이를 높이는 대신에 본딩 와이어(116)를 반도체 칩(110)의 측면으로 길게 형성하여 본딩 와이어(116)가 반도체 칩(110)의 측면과 숏트되는 문제를 방지하고 있다.As the number of stacked semiconductor chips 110 increases, the height difference between the bonding pads 112 and the connection pads 122 increases, so the height of the loop must be increased. However, when the height of the loop is increased, defects in contact with the semiconductor chip positioned at the upper part of the loop may occur. Instead of increasing the height of the loop, the bonding wire 116 is formed to be long on the side of the semiconductor chip 110 to bond the same. The problem that the wire 116 is shorted with the side surface of the semiconductor chip 110 is prevented.

그러나, 이와 같이 반도체 칩(110) 측면으로 본딩 와이어(116)를 길게 형성하면, 본딩 와이어(116)가 지나가는 면적을 확보해야 하므로 패키지의 사이즈가 증가되는 문제점이 있다.However, if the bonding wire 116 is formed long on the side of the semiconductor chip 110 as described above, the size of the package is increased because the area where the bonding wire 116 passes must be secured.

본 발명은, 감소된 사이즈를 갖는 경박단소화된 새로운 형태의 적층 반도체 패키지를 제공하는데, 그 목적이 있다.It is an object of the present invention to provide a new type of laminated semiconductor package having a reduced size with a reduced size.

본 발명의 일 실시예에 따른 적층 반도체 패키지는, 상면에 접속 패드들이 형성된 기판; 상기 기판 상면에 상기 접속 패드들이 노출되도록 적층되며, (ⅰ)상기 기판과 대향하는 일면, 상기 기판과 대응하는 타면, 상기 일면 및 상기 타면을 연결하는 측면을 가지며 상기 측면 중 적어도 일부분이 톱니 형태로 절단되어 가장자리를 따라서 복수개의 돌출부들이 형성된 반도체 칩 몸체, (ⅱ)상기 각각의 돌출부들의 상기 일면에 형성되는 본딩 패드를 각각 포함하는 적어도 2개 이상의 반도체 칩들; 상기 기판의 상기 접속 패드들과 상기 반도체 칩들 중 최하부 반도체 칩의 본딩 패드들을 연결하는 제1 본딩 와이어;및 인접하여 적층된 상기 반도체 칩들의 본딩 패드들 사이를 연결하는 제2 본딩 와이어들을 포함하며, 상기 인접하여 적층된 반도체 칩들 중 상부 반도체 칩의 돌출부들과 하부 반도체 칩의 돌출부들은 상호 엇갈리도록 형성되고, 상기 제2 본딩 와이어들은 상기 인접하여 적층된 상부 반도체 칩 및 하부 반도체 칩들의 돌출부들 상에 배치된 것을 특징으로 한다. According to one or more exemplary embodiments, a multilayer semiconductor package includes: a substrate having connection pads formed on an upper surface thereof; The connection pads are stacked on the substrate to expose the connection pads, and (i) one surface facing the substrate, the other surface corresponding to the substrate, the side surface connecting the one surface and the other surface, and at least a portion of the side surface is sawtooth-shaped. At least two semiconductor chips each comprising a semiconductor chip body cut and formed with a plurality of protrusions along an edge thereof, and (ii) bonding pads formed on the one surface of each of the protrusions; A first bonding wire connecting the connection pads of the substrate and the bonding pads of the lowermost semiconductor chip of the semiconductor chips; and second bonding wires connecting the bonding pads of the adjacent stacked semiconductor chips; The protrusions of the upper semiconductor chip and the protrusions of the lower semiconductor chip of the adjacent stacked semiconductor chips are formed to cross each other, and the second bonding wires are formed on the protrusions of the adjacent stacked upper semiconductor chip and the lower semiconductor chips. Characterized in that arranged.

상기 접속 패드들은 상기 기판과 인접한 반도체 칩의 상기 돌출부들 사이에 배치되는 것을 특징으로 한다.The connection pads may be disposed between the protrusions of the semiconductor chip adjacent to the substrate.

상기 접속 패드들은 상기 기판과 인접한 반도체 칩의 상기 본딩 패드들 바깥쪽에 상기 본딩 패드들과 나란하게 배치되는 것을 특징으로 한다.The connection pads may be disposed in parallel with the bonding pads outside the bonding pads of the semiconductor chip adjacent to the substrate.

상기 기판 및 상기 기판과 인접한 반도체 칩 사이 및 상기 반도체 칩들 사이에 형성되는 접착부재를 포함하는 것을 특징으로 한다.And an adhesive member formed between the substrate, the semiconductor chip adjacent to the substrate, and between the semiconductor chips.

상기 접착부재는, 접착 테이프, 접착 페이스트 중 어느 하나로 형성되는 것을 특징으로 한다.The adhesive member is formed of any one of an adhesive tape and an adhesive paste.

상기 접착 테이프는 스페이서 테이프, WBL(Wafer Back Lamination) 테이프 및 PWBL(Penetrate WBL) 테이프 중 어느 하나로 형성되는 것을 특징으로 한다.The adhesive tape is formed of any one of a spacer tape, a wafer back lamination (WBL) tape, and a planetary WBL (PWBL) tape.

상기 접착 페이스트는 에폭시(epoxy)로 형성되는 것을 특징으로 한다.The adhesive paste is characterized in that formed of epoxy (epoxy).

본 발명에 따르면, 본딩 와이어의 길이가 감소되고 본딩 와이어로 인한 패키지의 사이즈 증가가 감소되므로, 경박단소화된 새로운 형태의 패키지를 제공할 수 있다.According to the present invention, since the length of the bonding wire is reduced and the increase in size of the package due to the bonding wire is reduced, it is possible to provide a new type of package with a light weight.

도 1은 종래 기술에 따른 적층 반도체 패키지를 도시한 단면도이다.
도 2는 본 발명의 제 1 실시예에 따른 적층 반도체 패키지의 일부분을 나타낸 사시도이다.
도 3은 본 발명의 제 1 실시예에 따른 적층 반도체 패키지에서 기판과 제 1 반도체 칩을 나타낸 평면도이다.
도 4는 본 발명의 제 1 실시예에 따른 적층 반도체 패키지에서 제 1 반도체 칩과 제 2 반도체 칩을 나타낸 평면도이다.
도 5는 본 발명의 제 2 실시예에 따른 적층 반도체 패키지의 일부분을 나타낸 사시도이다.
도 6은 본 발명의 제 2 실시예에 따른 적층 반도체 패키지를 나타낸 평면도이다.1 is a cross-sectional view showing a laminated semiconductor package according to the prior art.
2 is a perspective view illustrating a portion of a multilayer semiconductor package according to a first embodiment of the present invention.
3 is a plan view illustrating a substrate and a first semiconductor chip in the multilayer semiconductor package according to the first embodiment of the present invention.
4 is a plan view illustrating a first semiconductor chip and a second semiconductor chip in the multilayer semiconductor package according to the first embodiment of the present invention.
5 is a perspective view illustrating a portion of a multilayer semiconductor package according to a second embodiment of the present invention.
6 is a plan view illustrating a multilayer semiconductor package according to a second exemplary embodiment of the present invention.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제 1 1st 실시예Example

도 2 내지 도 4는 본 발명의 제 1 실시예에 따른 적층 반도체 패키지를 설명하기 위한 도면들이다.2 to 4 are diagrams for describing a multilayer semiconductor package according to a first embodiment of the present invention.

도 2는 본 발명의 제 1 실시예에 따른 적층 반도체 패키지의 일부분을 나타낸 사시도이고, 도 3은 본 발명의 제 1 실시예에 따른 적층 반도체 패키지에서 기판과 제 1 반도체 칩을 나타낸 평면도이고, 도 4는 본 발명의 제 1 실시예에 따른 적층 반도체 패키지에서 제 1 반도체 칩과 제 2 반도체 칩을 나타낸 평면도이다.2 is a perspective view illustrating a portion of a multilayer semiconductor package according to a first embodiment of the present invention, and FIG. 3 is a plan view illustrating a substrate and a first semiconductor chip in the multilayer semiconductor package according to the first embodiment of the present invention. 4 is a plan view illustrating a first semiconductor chip and a second semiconductor chip in the multilayer semiconductor package according to the first embodiment of the present invention.

도 2 내지 도 4를 참조하면, 본 발명의 제 1 실시예에 따른 적층 반도체 패키지는, 기판(210), 제 1, 제 2 반도체 칩(220, 230), 제 1, 제 2 본딩 와이어(240, 250)를 포함한다.2 to 4, the multilayer semiconductor package according to the first embodiment of the present invention may include a substrate 210, first and second semiconductor chips 220 and 230, and first and second bonding wires 240. , 250).

그 외에, 제 1, 제 2 접착부재(260, 270), 봉지부(미도시) 및 외부접속단자(미도시)를 포함한다.In addition, the first and second adhesive members 260 and 270 may include an encapsulation part and an external connection terminal.

기판(210)은 플레이트 형상을 가질 수 있다. 플레이트 형상을 갖는 기판(210)은 상면(210A), 상면(210A)과 대향하는 하면(210B), 상면(210A) 및 하면(210B)을 연결하는 측면(210C)을 갖는다.The substrate 210 may have a plate shape. The substrate 210 having a plate shape has an upper surface 210A, a lower surface 210B facing the upper surface 210A, a side surface 210C connecting the upper surface 210A and the lower surface 210B.

기판(210)은, 예를 들어, 인쇄회로기판(Printed Circuit Board, PCB)일 수 있다. The substrate 210 may be, for example, a printed circuit board (PCB).

기판(210)의 상면(210A)에는 다수의 접속 패드(212)들이 형성되고, 기판(210)의 하면(210B)에는 볼랜드(미도시)가 형성된다.A plurality of connection pads 212 are formed on the top surface 210A of the substrate 210, and a ball land (not shown) is formed on the bottom surface 210B of the substrate 210.

접속 패드(212)와 볼랜드는 기판(210) 내부에 형성된 도전성 비아(미도시)를 통하여 전기적으로 연결된다.The connection pad 212 and the borland are electrically connected through conductive vias (not shown) formed in the substrate 210.

제 1 반도체 칩(220)은 접속 패드(212)가 노출되도록 기판(210)의 상면(210A)에 부착된다. The first semiconductor chip 220 is attached to the top surface 210A of the substrate 210 so that the connection pad 212 is exposed.

기판(210)과 제 1 반도체 칩(220) 사이에는 이들을 상호 부착하기 위한 제 1 접착부재(260)가 개재된다.A first adhesive member 260 is attached between the substrate 210 and the first semiconductor chip 220 to attach them to each other.

제 1 접착부재(260)는 접착 테이프(tape), 접착 페이스트(paste) 중 어느 하나로 형성될 수 있다.The first adhesive member 260 may be formed of any one of an adhesive tape and an adhesive paste.

접착 테이프로는 스페이서 테이프, WBL(Wafer Back Lamination) 테이프 및 PWBL(Penetrate WBL) 테이프 중 어느 하나가 사용될 수 있고, 접착 페이스트로는 에폭시가 사용될 수 있다. As the adhesive tape, any one of a spacer tape, a wafer back lamination (WBL) tape, and a planetary WBL (PWBL) tape may be used, and an epoxy may be used as the adhesive paste.

제 1 반도체 칩(220)은 제 1 반도체 칩 몸체(221) 및 제 1 본딩 패드(222)들을 포함한다.The first semiconductor chip 220 includes a first semiconductor chip body 221 and first bonding pads 222.

제 1 반도체 칩 몸체(221)는 일면(221A), 타면(221B), 측면(221C), 제 1 돌출부(223)들 및 제 1 회로부(미도시)를 포함한다.The first semiconductor chip body 221 includes one surface 221A, the other surface 221B, the side surface 221C, the first protrusions 223, and the first circuit unit (not shown).

일면(221A)은 기판(210)과 대향하고, 타면(221B)은 기판(210)과 대응한다. 측면(221C)은 일면(221A) 및 타면(221C)을 연결한다.One surface 221A faces the substrate 210, and the other surface 221B corresponds to the substrate 210. Side surface 221C connects one surface 221A and the other surface 221C.

제 1 반도체 칩 몸체(221)의 측면(221C) 중 적어도 일부분은 톱니 형태로 절단되어 있다. 제 1 돌출부(223)는 측면(221C)이 톱니 형태로 절단된 제 1 반도체 칩 몸체(221)의 가장자리를 따라서 복수개 형성된다. 제 1 돌출부(223)는 직육면체 형상을 가질 수 있다.At least a portion of the side surface 221C of the first semiconductor chip body 221 is cut in a sawtooth shape. The first protrusion 223 is formed in plural along the edge of the first semiconductor chip body 221 having the side surface 221C cut in a sawtooth shape. The first protrusion 223 may have a rectangular parallelepiped shape.

제 1 돌출부(223)의 일면(221A)에는 제 1 본딩 패드(222)가 형성된다. 제 1 본딩 패드(222)는 제 1 돌출부(223)마다 각각 1개씩 형성된다.A first bonding pad 222 is formed on one surface 221A of the first protrusion 223. One first bonding pad 222 is formed for each of the first protrusions 223.

제 1 회로부는 데이터를 저장하기 위한 데이터 저장부 및 데이터를 저장하기 위한 데이터 처리부를 포함한다. 제 1 본딩 패드(222)들은 외부와의 연결을 위한 회로부의 전기적 접점에 해당된다.The first circuit portion includes a data storage portion for storing data and a data processing portion for storing data. The first bonding pads 222 correspond to electrical contacts of a circuit unit for connection with the outside.

본 실시예에서, 제 1 돌출부(223)들은 기판(210)의 접속 패드(212)들 사이 사이에 배치되고, 기판(210)의 접속 패드(212)들은 제 1 돌출부(223)들 사이 사이에 배치된다.In the present embodiment, the first protrusions 223 are disposed between the connection pads 212 of the substrate 210, and the connection pads 212 of the substrate 210 are between the first protrusions 223. Is placed.

제 2 반도체 칩(230)은 제 1 반도체 칩(220)의 일면(220A)에 제 2 접착부재(270)을 매개로 부착된다.The second semiconductor chip 230 is attached to one surface 220A of the first semiconductor chip 220 through the second adhesive member 270.

제 2 접착부재(270)는 제 1 접착부재(260)와 동일한 물질로 형성될 수 있다. 본 실시에에서, 제 2 접착부재(270)는 접착 테이프, 접착 페이스트 중 어느 하나로 형성될 수 있다.The second adhesive member 270 may be formed of the same material as the first adhesive member 260. In the present embodiment, the second adhesive member 270 may be formed of any one of an adhesive tape and an adhesive paste.

접착 테이프로는 스페이서 테이프, WBL 테이프 및 PWBL 테이프 중 어느 하나가 사용될 수 있고, 접착 페이스트로는 에폭시가 사용될 수 있다. Any one of a spacer tape, a WBL tape, and a PWBL tape may be used as the adhesive tape, and epoxy may be used as the adhesive paste.

제 2 반도체 칩(230)은 제 2 반도체 칩 몸체(231) 및 제 2 본딩 패드(232)들을 포함한다.The second semiconductor chip 230 includes a second semiconductor chip body 231 and second bonding pads 232.

제 2 반도체 칩 몸체(231)는 제1면(231A), 제2면(231B), 측면(221C), 제 2 돌출부(233)들 및 제 2 회로부(미도시)를 포함한다.The second semiconductor chip body 231 includes a first surface 231A, a second surface 231B, a side surface 221C, second protrusions 233, and a second circuit unit (not shown).

제1면(231A)은 기판(210)과 대향하고, 제2면(231B)은 기판(210)과 대응한다. 측면(231C)들은 제1면(231A) 및 제2면(231C)을 연결한다.The first surface 231A faces the substrate 210, and the second surface 231B corresponds to the substrate 210. Side surfaces 231C connect the first surface 231A and the second surface 231C.

제 2 반도체 칩 몸체(231)의 측면(231C) 중 적어도 일부분은 톱니 형태로 절단되어 있다. 제 2 돌출부(233)는 측면(231C)이 톱니 형태로 절단된 제 2 반도체 칩 몸체(231)의 가장자리를 따라서 복수개 형성된다. 제 2 돌출부(233)는 직육면체 형상을 가질 수 있다.At least a portion of the side surface 231C of the second semiconductor chip body 231 is cut in a sawtooth shape. The second protrusion 233 is formed in plural along the edge of the second semiconductor chip body 231 having the side surface 231C cut in a sawtooth shape. The second protrusion 233 may have a rectangular parallelepiped shape.

제 2 돌출부(233)들은 제 1 반도체 칩(220)의 제 1 돌출부(223)들과 어갈리도록 형성된다. The second protrusions 233 are formed to alternate with the first protrusions 223 of the first semiconductor chip 220.

제 2 돌출부(233)의 제1면(231A)에는 제 2 본딩 패드(232)가 형성된다. A second bonding pad 232 is formed on the first surface 231A of the second protrusion 233.

제 2 회로부는 데이터를 저장하기 위한 데이터 저장부 및 데이터를 저장하기 위한 데이터 처리부를 포함한다. 제 2 본딩 패드(232)들은 외부와의 연결을 위한 회로부의 전기적 접점에 해당된다.The second circuit portion includes a data storage portion for storing data and a data processing portion for storing data. The second bonding pads 232 correspond to electrical contacts of a circuit unit for connection with the outside.

제 2 본딩 패드(232)는 제 2 돌출부(233)마다 각각 1개씩 형성된다.One second bonding pad 232 is formed for each of the second protrusions 233.

제 1 본딩 와이어(240)는 기판(210)의 접속 패드(212)들과 제 1 반도체 칩(220)의 제 1 본딩 패드(222)들을 전기적으로 연결한다.The first bonding wire 240 electrically connects the connection pads 212 of the substrate 210 and the first bonding pads 222 of the first semiconductor chip 220.

그리고, 제 2 본딩 와이어(250)는 제 1 반도체 칩(220)의 제 1 본딩 패드(222)들과 제 2 반도체 칩(230)의 제 2 본딩 패드(232)들을 전기적으로 연결한다.The second bonding wire 250 electrically connects the first bonding pads 222 of the first semiconductor chip 220 and the second bonding pads 232 of the second semiconductor chip 230.

도시하지 않았지만, 봉지부는 제 1, 제 2 반도체 칩(220, 230)을 포함한 기판(210)의 상면(210A)을 밀봉되고, 외부접속단자는 기판(210)의 하면(210B)에 형성된 볼랜드에 어탯치된다. 외부접속단자는 솔더볼을 포함할 수 있다.Although not shown, the encapsulation portion seals the upper surface 210A of the substrate 210 including the first and second semiconductor chips 220 and 230, and the external connection terminal is connected to the ball land formed on the lower surface 210B of the substrate 210. It is attached. The external connection terminal may include a solder ball.

제2 Second 실시예Example

도 5 내지 도 6은 본 발명의 제 2 실시예에 따른 적층 반도체 패키지를 설명하기 위한 도면들이다.5 to 6 are diagrams for describing a multilayer semiconductor package according to a second embodiment of the present invention.

도 5는 본 발명의 제 2 실시예에 따른 적층 반도체 패키지의 일부분을 나타낸 사시도이고, 도 6은 본 발명의 제 2 실시예에 따른 적층 반도체 패키지를 나타낸 평면도이다.5 is a perspective view illustrating a part of a multilayer semiconductor package according to a second embodiment of the present invention, and FIG. 6 is a plan view illustrating a multilayer semiconductor package according to a second embodiment of the present invention.

도 5 및 도 6을 참조하면, 본 발명의 제 2 실시예에 따른 적층 반도체 패키지는, 기판(210), 제 1, 제 2 반도체 칩(220, 230), 제 1, 제 2 본딩 와이어(240, 250)를 포함한다.5 and 6, a multilayer semiconductor package according to a second exemplary embodiment of the present invention may include a substrate 210, first and second semiconductor chips 220 and 230, and first and second bonding wires 240. , 250).

그 외에, 제 1, 제 2 접착부재(260, 270), 봉지부(미도시) 및 외부접속단자(미도시)를 포함한다.In addition, the first and second adhesive members 260 and 270 may include an encapsulation part and an external connection terminal.

기판(210)은 플레이트 형상을 가질 수 있다. 플레이트 형상을 갖는 기판(210)은 상면(210A), 상면(210A)과 대향하는 하면(210B), 상면(210A) 및 하면(210B)을 연결하는 측면(210C)을 갖는다.The substrate 210 may have a plate shape. The substrate 210 having a plate shape has an upper surface 210A, a lower surface 210B facing the upper surface 210A, a side surface 210C connecting the upper surface 210A and the lower surface 210B.

기판(210)은, 예를 들어 인쇄회로기판일 수 있다.The substrate 210 may be, for example, a printed circuit board.

기판(210)의 상면(210A)에는 다수의 접속 패드(212)들이 형성되고, 기판(210)의 하면(210B)에는 볼랜드(미도시)가 형성된다.A plurality of connection pads 212 are formed on the top surface 210A of the substrate 210, and a ball land (not shown) is formed on the bottom surface 210B of the substrate 210.

접속 패드(212)와 볼랜드는 기판(210) 내부에 형성된 도전성 비아(미도시)를 통하여 전기적으로 연결된다.The connection pad 212 and the borland are electrically connected through conductive vias (not shown) formed in the substrate 210.

제 1 반도체 칩(220)은 접속 패드(212)가 노출되도록 기판(210)의 상면(210A)에 부착된다. The first semiconductor chip 220 is attached to the top surface 210A of the substrate 210 so that the connection pad 212 is exposed.

기판(210)과 제 1 반도체 칩(220) 사이에는 이들을 상호 부착하기 위하여 제 1 접착부재(260)가 개재된다.A first adhesive member 260 is interposed between the substrate 210 and the first semiconductor chip 220 to attach them to each other.

제 1 접착부재(260)는 접착 테이프, 접착 페이스트 중 어느 하나로 형성될 수 있다.The first adhesive member 260 may be formed of any one of an adhesive tape and an adhesive paste.

접착 테이프로는 스페이서 테이프, WBL 테이프 및 PWBL 테이프 중 어느 하나가 사용될 수 있고, 접착 페이스트로는 에폭시가 사용될 수 있다. Any one of a spacer tape, a WBL tape, and a PWBL tape may be used as the adhesive tape, and epoxy may be used as the adhesive paste.

제 1 반도체 칩(220)은 제 1 반도체 칩 몸체(221) 및 제 1 본딩 패드(222)들을 포함한다.The first semiconductor chip 220 includes a first semiconductor chip body 221 and first bonding pads 222.

제 1 반도체 칩 몸체(221)는 일면(221A), 타면(221B), 측면(221C), 제 1 돌출부(223)들 및 제 1 회로부(미도시)를 포함한다.The first semiconductor chip body 221 includes one surface 221A, the other surface 221B, the side surface 221C, the first protrusions 223, and the first circuit unit (not shown).

일면(221A)은 기판(210)과 대향하고, 타면(221B)은 기판(210)과 대응한다. 측면(221C)은 일면(221A) 및 타면(221C)을 연결한다.One surface 221A faces the substrate 210, and the other surface 221B corresponds to the substrate 210. Side surface 221C connects one surface 221A and the other surface 221C.

제 1 반도체 칩 몸체(221)의 측면(221C) 중 적어도 일부분은 톱니 형태로 절단되어 있다. 제 1 돌출부(223)는 측면(221C)이 톱니 형태로 절단된 제 1 반도체 칩 몸체(221)의 가장자리를 따라서 복수개 형성된다. 제 1 돌출부(223)는 직육면체 형상을 가질 수 있다.At least a portion of the side surface 221C of the first semiconductor chip body 221 is cut in a sawtooth shape. The first protrusion 223 is formed in plural along the edge of the first semiconductor chip body 221 having the side surface 221C cut in a sawtooth shape. The first protrusion 223 may have a rectangular parallelepiped shape.

제 1 돌출부(223)의 일면(221A)에는 제 1 본딩 패드(222)가 형성된다. A first bonding pad 222 is formed on one surface 221A of the first protrusion 223.

제 1 회로부는 데이터를 저장하기 위한 데이터 저장부 및 데이터를 저장하기 위한 데이터 처리부를 포함한다. 제 1 본딩 패드(222)는 외부와의 연결을 위한 회로부의 전기적 접점에 해당된다.The first circuit portion includes a data storage portion for storing data and a data processing portion for storing data. The first bonding pad 222 corresponds to an electrical contact of a circuit unit for connection with the outside.

제 1 본딩 패드(222)는 제 1 돌출부(223)마다 각각 1개씩 형성된다.One first bonding pad 222 is formed for each of the first protrusions 223.

본 실시예에서, 기판(210)의 접속 패드(212)들은 제 1 반도체 칩(220)의 제 1 본딩 패드(222)들 바깥쪽 기판(210) 상면(210A)에 제 1 본딩 패드(222)들과 나란하게 배치된다.In the present exemplary embodiment, the connection pads 212 of the substrate 210 may include the first bonding pads 222 on the upper surface 210A of the substrate 210 outside the first bonding pads 222 of the first semiconductor chip 220. Placed alongside the fields.

제 2 반도체 칩(230)은 제 1 반도체 칩(220)의 일면(220A)에 제 2 접착부재(270)을 매개로 부착된다.The second semiconductor chip 230 is attached to one surface 220A of the first semiconductor chip 220 through the second adhesive member 270.

제 2 접착부재(270)는 제 1 접착부재(260)와 동일한 물질로 형성될 수 있다. 본 실시에에서, 제 2 접착부재(270)는 접착 테이프, 접착 페이스트 중 어느 하나로 형성될 수 있다.The second adhesive member 270 may be formed of the same material as the first adhesive member 260. In the present embodiment, the second adhesive member 270 may be formed of any one of an adhesive tape and an adhesive paste.

접착 테이프로는 스페이서 테이프, WBL 테이프 및 PWBL 테이프 중 어느 하나가 사용될 수 있고, 접착 페이스트로는 에폭시가 사용될 수 있다. Any one of a spacer tape, a WBL tape, and a PWBL tape may be used as the adhesive tape, and epoxy may be used as the adhesive paste.

제 2 반도체 칩(230)은 제 2 반도체 칩 몸체(231) 및 제 2 본딩 패드(232)들을 포함한다.The second semiconductor chip 230 includes a second semiconductor chip body 231 and second bonding pads 232.

제 2 반도체 칩 몸체(231)는 제1면(231A), 제2면(231B), 측면(221C), 제 2 돌출부(233)들 및 제 2 회로부(미도시)를 포함한다.The second semiconductor chip body 231 includes a first surface 231A, a second surface 231B, a side surface 221C, second protrusions 233, and a second circuit unit (not shown).

제1면(231A)은 기판(210)과 대향하고, 제2면(231B)은 기판(210)과 대응한다. 측면(231C)은 제1면(231A) 및 제2면(231C)을 연결한다.The first surface 231A faces the substrate 210, and the second surface 231B corresponds to the substrate 210. Side surface 231C connects the first surface 231A and the second surface 231C.

제 2 반도체 칩 몸체(231)는 측면(231C) 중 적어도 일부분은 톱니 형태로 절단되어 있다. 제 2 돌출부(233)는 측면(231C)이 톱니 형태로 절단된 제 2 반도체 칩 몸체(231)의 가장자리를 따라서 복수개 형성된다. 제 2 돌출부(233)는 직육면체 형상을 가질 수 있다.At least a portion of the side surface 231C of the second semiconductor chip body 231 is cut into a sawtooth shape. The second protrusion 233 is formed in plural along the edge of the second semiconductor chip body 231 having the side surface 231C cut in a sawtooth shape. The second protrusion 233 may have a rectangular parallelepiped shape.

제 2 돌출부(233)의 제1면(231A)에는 제 2 본딩 패드(232)가 형성된다. A second bonding pad 232 is formed on the first surface 231A of the second protrusion 233.

제 2 회로부는 데이터를 저장하기 위한 데이터 저장부 및 데이터를 저장하기 위한 데이터 처리부를 포함한다. 제 2 본딩 패드(232)는 외부와의 연결을 위한 회로부의 전기적 접점에 해당된다.The second circuit portion includes a data storage portion for storing data and a data processing portion for storing data. The second bonding pads 232 correspond to electrical contacts of a circuit unit for connection with the outside.

제 2 본딩 패드(232)은 제 2 돌출부(233)마다 각각 1개씩 형성된다.One second bonding pad 232 is formed for each second protrusion 233.

제 2 돌출부(233)들은 제 1 반도체 칩(220)의 제 1 돌출부(223)들과 엇갈리도록 형성된다. The second protrusions 233 are formed to cross the first protrusions 223 of the first semiconductor chip 220.

제 1 본딩 와이어(240)는 기판(210)의 접속 패드(212)들과 제 1 반도체 칩(220)의 제 1 본딩 패드(222)들을 전기적으로 연결한다.The first bonding wire 240 electrically connects the connection pads 212 of the substrate 210 and the first bonding pads 222 of the first semiconductor chip 220.

그리고, 제 2 본딩 와이어(250)는 제 1 반도체 칩(220)의 제 1 본딩 패드(222)들과 제 2 반도체 칩(230)의 제 2 본딩 패드(232)들을 전기적으로 연결한다.The second bonding wire 250 electrically connects the first bonding pads 222 of the first semiconductor chip 220 and the second bonding pads 232 of the second semiconductor chip 230.

도시하지 않았지만, 봉지부는 제 1, 제 2 반도체 칩(220, 230)을 포함한 기판(210)의 상면(210A)을 밀봉되고, 외부접속단자는 기판(210)의 하면(210B)에 형성된 볼랜드에 어탯치된다. 외부접속단자는 솔더볼을 포함할 수 있다.Although not shown, the encapsulation portion seals the upper surface 210A of the substrate 210 including the first and second semiconductor chips 220 and 230, and the external connection terminal is connected to the ball land formed on the lower surface 210B of the substrate 210. It is attached. The external connection terminal may include a solder ball.

이상에서 상세하게 설명한 바에 의하면, 본딩 와이어의 길이가 감소되고 본딩 와이어로 인한 패키지의 사이즈 증가가 감소되므로, 경박단소화된 새로운 형태의 패키지를 제공할 수 있다.As described in detail above, since the length of the bonding wire is reduced and the size increase of the package due to the bonding wire is reduced, a new type of package can be provided.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

예컨데, 전술한 실시예들에서는 적층되는 반도체 칩의 개수가 2개인 경우에 한하여 설명하였으나, 본 발명은 이에 한정되지 않으며, 적층되는 반도체 칩의 개수가 2개 이상인 모든 경우를 포함한다.For example, the above-described embodiments have been described in the case where the number of stacked semiconductor chips is two, but the present invention is not limited thereto and includes all cases in which the number of stacked semiconductor chips is two or more.

210 : 기판
212 : 접속 패드
220, 230 : 제 1, 제 2 반도체 칩
222, 232 : 제 1, 제 2 본딩 패드
223, 233 : 제 1, 제 2 돌출부
240, 250 : 제 1, 제 2 본딩 와이어210: substrate
212: connection pad
220, 230: first and second semiconductor chips
222 and 232: first and second bonding pads
223 and 233: first and second protrusions
240, 250: first and second bonding wires

Claims (7)

상면에 접속 패드들이 형성된 기판;
상기 기판 상면에 상기 접속 패드들이 노출되도록 적층되며, (ⅰ)상기 기판과 대향하는 일면, 상기 기판과 대응하는 타면, 상기 일면 및 상기 타면을 연결하는 측면을 가지며 상기 측면 중 적어도 일부분이 톱니 형태로 절단되어 가장자리를 따라서 복수개의 돌출부들이 형성된 반도체 칩 몸체, (ⅱ)상기 각각의 돌출부들의 상기 일면에 형성되는 본딩 패드를 각각 포함하는 적어도 2개 이상의 반도체 칩들;
상기 기판의 상기 접속 패드들과 상기 반도체 칩들 중 최하부 반도체 칩의 본딩 패드들을 연결하는 제1 본딩 와이어;및
인접하여 적층된 상기 반도체 칩들의 본딩 패드들 사이를 연결하는 제2 본딩 와이어들을 포함하며,
상기 인접하여 적층된 반도체 칩들 중 상부 반도체 칩의 돌출부들과 하부 반도체 칩의 돌출부들은 상호 엇갈리도록 형성되고, 상기 제2 본딩 와이어들은 상기 인접하여 적층된 상부 반도체 칩 및 하부 반도체 칩들의 돌출부들 상에 배치된 것을 특징으로 하는 적층반도체 패키지.A substrate having connection pads formed on an upper surface thereof;
The connection pads are stacked on the substrate to expose the connection pads, and (i) one surface facing the substrate, the other surface corresponding to the substrate, the side surface connecting the one surface and the other surface, and at least a portion of the side surface is sawtooth-shaped. At least two semiconductor chips each comprising a semiconductor chip body cut and formed with a plurality of protrusions along an edge thereof, and (ii) bonding pads formed on the one surface of each of the protrusions;
A first bonding wire connecting the connection pads of the substrate and bonding pads of a lowermost semiconductor chip of the semiconductor chips; and
Second bonding wires connecting between bonding pads of the semiconductor chips stacked adjacent to each other;
The protrusions of the upper semiconductor chip and the protrusions of the lower semiconductor chip of the adjacent stacked semiconductor chips are formed to cross each other, and the second bonding wires are formed on the protrusions of the adjacent stacked upper semiconductor chip and the lower semiconductor chips. Laminated semiconductor package, characterized in that disposed. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1항에 있어서,
상기 접속 패드들은 상기 기판과 인접한 반도체 칩의 상기 돌출부들 사이에 배치되는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1,
And the connection pads are disposed between the protrusions of the semiconductor chip adjacent to the substrate. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 has been abandoned due to the setting registration fee. 제 1항에 있어서,
상기 접속 패드들은 상기 기판과 인접한 반도체 칩의 상기 본딩 패드들 바깥쪽에 상기 본딩 패드들과 나란하게 배치되는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1,
And the connection pads are disposed in parallel to the bonding pads outside the bonding pads of the semiconductor chip adjacent to the substrate. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 has been abandoned due to the setting registration fee. 제 1항에 있어서,
상기 기판 및 상기 기판과 인접한 반도체 칩 사이 및 상기 반도체 칩들 사이에 형성되는 접착부재를 포함하는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1,
And an adhesive member formed between the substrate, the semiconductor chip adjacent to the substrate, and between the semiconductor chips. 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제 4항에 있어서,
상기 접착부재는 접착 테이프, 접착 페이스트 중 어느 하나로 형성되는 것을 특징으로 하는 적층 반도체 패키지.The method of claim 4, wherein
The adhesive member is a laminated semiconductor package, characterized in that formed by any one of an adhesive tape, an adhesive paste. 청구항 6은(는) 설정등록료 납부시 포기되었습니다.Claim 6 has been abandoned due to the setting registration fee. 제 5항에 있어서,
상기 접착 테이프는 스페이서 테이프, WBL(Wafer Back Lamination) 테이프 및 PWBL(Penetrate WBL) 테이프 중 어느 하나로 형성되는 것을 특징으로 하는 적층 반도체 패키지.6. The method of claim 5,
The adhesive tape is a laminated semiconductor package, characterized in that formed of any one of a spacer tape, a wafer back lamination (WBL) tape and a planetary WBL (PWBL) tape. 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제 5항에 있어서,
상기 접착 페이스트는 에폭시(epoxy)로 형성되는 것을 특징으로 하는 적층 반도체 패키지.6. The method of claim 5,
The adhesive paste is a laminated semiconductor package, characterized in that formed of epoxy (epoxy).
KR1020100000778A 2010-01-06 2010-01-06 Stacked semiconductor package KR101195460B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150120A1 (en) 2005-08-24 2008-06-26 Fujitsu Limited Semiconductor device and method of producing the same
US7518237B2 (en) 2005-02-08 2009-04-14 Micron Technology, Inc. Microfeature systems including adhered microfeature workpieces and support members

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7518237B2 (en) 2005-02-08 2009-04-14 Micron Technology, Inc. Microfeature systems including adhered microfeature workpieces and support members
US20080150120A1 (en) 2005-08-24 2008-06-26 Fujitsu Limited Semiconductor device and method of producing the same

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