KR20060074091A - Chip stack package - Google Patents

Chip stack package Download PDF

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Publication number
KR20060074091A
KR20060074091A KR1020040112715A KR20040112715A KR20060074091A KR 20060074091 A KR20060074091 A KR 20060074091A KR 1020040112715 A KR1020040112715 A KR 1020040112715A KR 20040112715 A KR20040112715 A KR 20040112715A KR 20060074091 A KR20060074091 A KR 20060074091A
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substrate
pads
stepped
pad
package
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KR1020040112715A
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Korean (ko)
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최형석
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주식회사 하이닉스반도체
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Priority to KR1020040112715A priority Critical patent/KR20060074091A/en
Publication of KR20060074091A publication Critical patent/KR20060074091A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

본 발명은 계단형 홈이 구비된 기판을 이용하고, 기판과 반도체 칩 간의 전기적 접속이 범프에 의해 이루어지도록 함으로써, 패키지의 박형화 및 소자의 고속 동작을 구현할 수 있는 칩 스택 패키지에 관한 것이다. 이 패키지는, 중심부에 계단형 홈이 구비되고, 상기 홈의 저면 및 상기 계단면에는 제 1 및 제 2 패드가 배열되며, 상기 제 1 및 제 2 패드들 각각은 비아 홀을 통해 하부면에 배열된 제 3 패드들과 각각 전기적으로 연결되는 기판; 상부면에 에지 어레이 타입으로 본딩 패드들이 구비되고, 범프를 매개로 상기 기판의 계단형 홈 저면 및 계단면에 부착되면서, 상기 본딩 패드들이 상기 기판의 제 1 패드 및 제 2 패드와 전기적으로 접속되는 제 1 및 제 2 반도체 칩; 상기 기판의 제 3 패드들 각각에 부착되어 전기적 접속 수단으로서의 기능을 하는 솔더 볼; 및 상기 계단형 홈의 계단면 측부 및 제 2 반도체 칩 상부를 포함하는 영역을 밀봉하는 봉지제;를 포함한다. The present invention relates to a chip stack package using a substrate having a stepped groove and allowing electrical connection between the substrate and the semiconductor chip to be made by bumps, thereby enabling a thinner package and a faster operation of the device. The package includes a stepped groove in a center portion, and first and second pads are arranged on a bottom surface and the step surface of the groove, and each of the first and second pads is arranged on a lower surface through a via hole. A substrate electrically connected to each of the third pads; Bonding pads are provided on the top surface in an edge array type, and the bonding pads are electrically connected to the first pad and the second pad of the substrate while being attached to the stepped groove bottom and the step surface of the substrate via bumps. First and second semiconductor chips; Solder balls attached to each of the third pads of the substrate to function as electrical connection means; And an encapsulant for sealing an area including a stepped side of the stepped groove and an upper portion of the second semiconductor chip.

Description

칩 스택 패키지{Chip stack package}Chip stack package

도 1은 두 개의 패키지를 스택하여 제조된 종래의 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional stack package manufactured by stacking two packages.

도 2는 하나의 패키지에 두 개의 반도체 칩을 적층하는 스택 패키지를 도시한 단면도.2 is a cross-sectional view illustrating a stack package in which two semiconductor chips are stacked in one package.

도 3은 본 발명의 실시예에 따른 기판을 도시한 단면도.3 is a cross-sectional view showing a substrate according to an embodiment of the present invention.

도 4는 본 발명의 실시예에 따른 제 1 및 제 2 반도체 칩을 도시한 단면도.4 is a cross-sectional view illustrating first and second semiconductor chips according to an embodiment of the present invention.

도 5는 본 발명의 실시예에 따른 기판 내에 제 1 및 제 2 반도체 칩이 탑재된 상태를 보여주는 단면도.5 is a cross-sectional view illustrating a state in which first and second semiconductor chips are mounted in a substrate according to an embodiment of the present invention.

도 6 내지 도 10은 본 발명의 실시예에 따른 칩 스택 패키지의 제조 과정을 설명하기 위한 단면도.
6 to 10 are cross-sectional views illustrating a manufacturing process of a chip stack package according to an exemplary embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 명치 *Nomenclature for the main parts of the drawing

20: 기판 21: 계단형 홈20: substrate 21: stepped groove

23: 제 1 패드 24: 제 2 패드23: first pad 24: second pad

25: 비아 홀 26: 제 3 패드25: via hole 26: third pad

30: 제 1 반도체 칩 31,41: 본딩패드 30: first semiconductor chip 31, 41: bonding pad                 

32,42: 범프 40: 제 2 반도체 칩
32, 42 bump 40: second semiconductor chip

본 발명은 칩 스택 패키지에 관한 것으로서, 보다 상세하게는, 계단형의 기판 내에 두 개의 반도체 칩들을 탑재시킨 칩 스택 패키지에 관한 것이다.The present invention relates to a chip stack package, and more particularly, to a chip stack package having two semiconductor chips mounted in a stepped substrate.

최근, 전기.전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. 고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 용량 증대, 다시 말해, 메모리 칩의 고집적화를 들 수 있으며, 이러한 고접적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. 그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선 폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 하다.Recently, as high performance is required along with miniaturization of electric and electronic products, various technologies for providing a high capacity semiconductor module have been researched and developed. As a method for providing a high-capacity semiconductor module, there is an increase in the capacity of a memory chip, that is, high integration of the memory chip, which is achieved by integrating a larger number of cells in a limited space of a semiconductor chip. Can be realized. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width.

이에 따라, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서, 스택(stack) 기술이 제안되었으며, 이러한 스택 패키지는 하나의 패키지에 두 개 이상의 반도체 칩을 적층하는 방식, 또는 두 개 이상의 패키지들을 적층하는 방식을 통해 제조되고 있다.Accordingly, as another method for providing a high capacity semiconductor module, a stack technology has been proposed, and such a stack package is a method of stacking two or more semiconductor chips in one package, or stacking two or more packages. It is manufactured by the method.

도 1은 두 개의 패키지를 스택하여 제조된 종래의 스택 패키지를 도시한 단면도이다. 1 is a cross-sectional view showing a conventional stack package manufactured by stacking two packages.                         

두 개의 패키지를 스택하여 제조된 종래의 스택 패키지는, 개별 공정을 통해 제작된 두 개의 패키지(10,11)가 상하에 배치되고, 각 패키지(10,11)의 외부로 인출된 리드 프레임(lead frame)의 아우터 리드(12,13)는 동축 선상에 배치되어 동일 기능을 하는 것들끼리 상호 연결된다.In a conventional stack package manufactured by stacking two packages, two packages 10 and 11 manufactured by individual processes are disposed above and below, and lead frames drawn out of each package 10 and 11 are drawn out. The outer leads 12, 13 of the frame are arranged on a coaxial line and interconnected with ones having the same function.

이와 같은 종래의 스택 패키지는, 두개의 패키지(10,11)가 서로 불안정하게 적층되어 있으며, 또한 적층된 두 패키지(10,11)의 아우터 리드(12,13)가 상호 불안정하게 연결되어 있다. 그 결과, 두 패키지(10,11)의 작은 흔들임에도 아우터 리드(12,13)가 단락되어 패키지의 불량이 발생될 수 있다. 또한, 두 개의 패키지를 적층함에 따라 패키지의 두께가 두꺼워진다.In the conventional stack package, the two packages 10 and 11 are unstablely stacked on each other, and the outer leads 12 and 13 of the two stacked packages 10 and 11 are unstablely connected to each other. As a result, the outer leads 12 and 13 may be short-circuited even with small shaking of the two packages 10 and 11, resulting in a defect of the package. In addition, as the two packages are stacked, the thickness of the package becomes thicker.

도 2는 하나의 패키지에 두 개의 반도체 칩을 적층하는 스택 패키지를 도시한 단면도이다.2 is a cross-sectional view illustrating a stack package in which two semiconductor chips are stacked in one package.

하나의 패키지에 두 개의 반도체 칩을 적층하는 스택 패키지는, 크기가 다른 두개의 반도체 칩을(14,15)을 기판(16)상에 적층하고, 동일 기능의 본딩패드를 금속 와이어(17,18)를 통해 전기적을 연결시키는 와이어 본딩을 실시한다. 이와 같은 종래의 칩 스택 패키지는, 와이어 본딩을 실시하기 위한, 일정 공간이 필요하게 되며, 그에 따라, 도 1에 도시한 스택 패키지와 동일하게 패키지의 박형화 구현에 한계가 있다.In a stack package in which two semiconductor chips are stacked in one package, two semiconductor chips 14 and 15 of different sizes are stacked on the substrate 16, and a bonding pad having the same function is attached to the metal wires 17 and 18. Wire bonding is used to connect electricity. Such a conventional chip stack package requires a certain space for wire bonding, and thus, there is a limit to a thinner package implementation similar to the stack package shown in FIG. 1.

따라서, 본 발명은 상기한 바와 같은 선행 기술에 내재되었던 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은, 계단형 홈이 구비된 기판을 이용하 고, 기판과 반도체 칩 간의 전기적 접속이 범프에 의해 이루어지도록 함으로써, 패키지의 박형화 및 소자의 고속 동작을 구현할 수 있는 칩 스택 패키지를 제공함에 있다.Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to use a substrate provided with stepped grooves, and the electrical connection between the substrate and the semiconductor chip is applied to the bumps. The present invention provides a chip stack package capable of thinning a package and high-speed operation of the device.

상기 목적을 달성하기 위해, 본 발명의 일면에 따라, 칩 스택 패키지가 제공되며: 이 패키지는, 중심부에 계단형 홈이 구비되고, 상기 홈의 저면 및 상기 계단면에는 제 1 및 제 2 패드가 배열되며, 상기 제 1 및 제 2 패드들 각각은 비아 홀을 통해 하부면에 배열된 제 3 패드들과 각각 전기적으로 연결되는 기판; 상부면에 에지 어레이 타입으로 본딩 패드들이 구비되고, 범프를 매개로 상기 기판의 계단형 홈 저면 및 계단면에 부착되면서, 상기 본딩 패드들이 상기 기판의 제 1 패드 및 제 2 패드와 전기적으로 접속되는 제 1 및 제 2 반도체 칩; 상기 기판의 제 3 패드들 각각에 부착되어 전기적 접속 수단으로서의 기능을 하는 솔더 볼; 및 상기 계단형 홈의 계단면 측부 및 제 2 반도체 칩 상부를 포함하는 영역을 밀봉하는 봉지제;를 포함하는 것을 특징으로 한다.In order to achieve the above object, in accordance with one aspect of the present invention, a chip stack package is provided: the package includes a stepped groove in a central portion thereof, and a first and a second pad on the bottom surface and the step surface of the groove. A substrate, each of the first and second pads electrically connected to third pads arranged on the bottom surface through a via hole; Bonding pads are provided on the top surface in an edge array type and attached to the stepped groove bottom and the step surface of the substrate via bumps, and the bonding pads are electrically connected to the first pad and the second pad of the substrate. First and second semiconductor chips; Solder balls attached to each of the third pads of the substrate to function as electrical connection means; And an encapsulant for sealing an area including a stepped side of the stepped groove and an upper portion of the second semiconductor chip.

(실시예)(Example)

이하, 첨부한 도면을 참고하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3 내지 도 5은 본 발명의 실시예에 따른 칩 스택 패키지를 설명하기 위한 단면도로서, 도 3은 본 발명의 실시예에 따른 기판을 도시한 단면도이고, 도 4는 본 발명의 실시예에 따른 제 1 및 제 2 반도체 칩을 도시한 단면도이며, 도 5는 상 기 기판 내에 제 1 및 제 2 반도체 칩이 탑재된 상태를 보여주는 단면도이다.3 to 5 are cross-sectional views illustrating a chip stack package according to an exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view illustrating a substrate according to an exemplary embodiment of the present invention, and FIG. 1 and 2 are cross-sectional views showing the first and second semiconductor chips, and FIG. 5 is a cross-sectional view showing a state in which the first and second semiconductor chips are mounted in the substrate.

도 3을 참조하면, 본 발명의 실시예에 따른 기판(20)은, 상부면 중심부에 1단의 계단형 홈(21)을 갖으며, 상기 홈(21)의 저면(22a) 및 상기 계단면(22b)에는 각각 제 1 및 제 2 패드들(23,24)이 배열되어 있다. 제 1 및 제 2 패드들(23,24)은, 내부에 구비된 비아 홀(25)을 통해 하부면(22c)에 배치된 제 3 패드(26), 즉, 볼랜드와가각 전기적으로 연결되어 있다.Referring to FIG. 3, the substrate 20 according to the embodiment of the present invention has a single stepped groove 21 at the center of the upper surface, and has a bottom surface 22a and the step surface of the groove 21. First and second pads 23 and 24 are arranged at 22b, respectively. The first and second pads 23 and 24 are electrically connected to the third pad 26 disposed on the lower surface 22c, that is, the borland, through the via hole 25 provided therein. .

도 4를 참조하면, 제 1 및 제 2 반도체 칩(30,40)은 에지 어레이 타입(edge array type)으로 본딩 패드(31,41)가 배열된 구조를 갖고, 본딩 패드(31,41) 상에는 범프(32,42)가 형성되어 있다.Referring to FIG. 4, the first and second semiconductor chips 30 and 40 have a structure in which bonding pads 31 and 41 are arranged in an edge array type, and on the bonding pads 31 and 41. Bumps 32 and 42 are formed.

도 5를 참조하면, 상기 제 1 반도체 칩(30)은, 기판(20)의 계단형 홈(21)의 저면(22a)에 배치되고, 그의 본딩 패드들(31)은 범프(32)에 의해서 기판(20)의 제 1 패드들(23)과 각각 전기적으로 접속되어 있다. 상기 제 2 반도체 칩(40)은, 비전도성 접착제(50)를 매개로 상기 제 1 반도체 칩(30)의 상부에 배치되면서, 기판920)의 계단면(22b) 상에 배치되고, 그의 본딩 패드들(31)은 범프(42)에 의해서 기판(20)의 제 2 패드들(24)과 각각 전기적으로 접속되어 있다. 또한, 제 2 반도체 칩(40) 상부면은 봉지제(60)로 밀봉된 구조를 갖고, 기판(20) 하부면(22c)의 제 3 패드(26) 상에는 솔더 볼(70)이 부착되어 있다.Referring to FIG. 5, the first semiconductor chip 30 is disposed on the bottom surface 22a of the stepped groove 21 of the substrate 20, and the bonding pads 31 thereof are formed by the bumps 32. The first pads 23 of the substrate 20 are electrically connected to each other. The second semiconductor chip 40 is disposed on the stepped surface 22b of the substrate 920 while being disposed above the first semiconductor chip 30 via the nonconductive adhesive 50, and the bonding pad thereof. The fields 31 are electrically connected to the second pads 24 of the substrate 20 by the bumps 42, respectively. In addition, the upper surface of the second semiconductor chip 40 has a structure sealed with an encapsulant 60, and solder balls 70 are attached to the third pads 26 of the lower surface 22c of the substrate 20. .

이하, 도 6 내지 도 10을 참조하여, 본 발명의 실시예에 따른 칩 스택 패키지의 제조 과정을 설명하기로 한다.Hereinafter, a manufacturing process of a chip stack package according to an exemplary embodiment of the present invention will be described with reference to FIGS. 6 to 10.

도 6를 참조하면, 상기 제 1 반도체 칩(30)은 기판(20)의 계단형 홈(21)의 저면(22a)에 배치되고, 제 1 반도체 칩(30)의 본딩 패드들(31)은 범프(32)에 의해서 기판(20)의 제 1 패드들(23)과 전기적으로 접속된다.Referring to FIG. 6, the first semiconductor chip 30 is disposed on the bottom surface 22a of the stepped groove 21 of the substrate 20, and the bonding pads 31 of the first semiconductor chip 30 are formed. The bumps 32 are electrically connected to the first pads 23 of the substrate 20.

도 7을 참조하면, 기판(20)에 부착된 제 1 반도체 칩(30) 상부에는 비전도성 접착제(50)가 상기 계단형 홈(21)의 계단면(22b)과 평행하게 도포된다.Referring to FIG. 7, a non-conductive adhesive 50 is applied on the first semiconductor chip 30 attached to the substrate 20 in parallel with the step surface 22b of the stepped groove 21.

도 8을 참조하면, 상기 제 2 반도체 칩(40)은 상기 계단형 홈(21)의 계단면(22b)에 배치되고, 제 2 반도체 칩(40)의 본딩 패드들(41)은 범프(42)에 의해서 기판(20)의 제 2 패드들(24)과 전기적으로 접속된다.Referring to FIG. 8, the second semiconductor chip 40 is disposed on the stepped surface 22b of the stepped groove 21, and the bonding pads 41 of the second semiconductor chip 40 are bumps 42. Is electrically connected to the second pads 24 of the substrate 20.

도 9을 참조하면, 상기 계단형 홈(21)의 계단면(22b) 측면부 및 제 2 반도체 칩(40) 상부를 포함하는 영역은 봉지제(60)에 의하여 밀봉된다. Referring to FIG. 9, an area including a side surface of the stepped surface 22b of the stepped groove 21 and an upper portion of the second semiconductor chip 40 is sealed by the encapsulant 60.

도 10를 참조하면, 기판(20)의 하부면(12c), 즉, 볼 랜드 상에는 외부와의 전기적 접속 경로로서의 기능을 하는 솔더 볼(70)이 부착된다.Referring to FIG. 10, a solder ball 70 is attached to the lower surface 12c of the substrate 20, that is, the ball land, which functions as an electrical connection path to the outside.

상기와 같은 구조를 갖는 본 발명에 따른 칩 스택 패키지는, 반도체 칩들이 기판의 계단형 홈에 탑재된 구조를 갖고, 기판과 반도체 칩간의 전기적 접속이 종래의 금속 와이어가 아닌 범프에 의해 이루어짐에 따라, 패키지의 크기 및 두께 증가를 방지할 수 있다. 또한, 반도체 칩과 기판 간의 전기적 접속 경로가 범프에 의해 짧아짐으로써, 소자의 고속 동작이 가능하다.The chip stack package according to the present invention having the above structure has a structure in which semiconductor chips are mounted in stepped grooves of a substrate, and electrical connection between the substrate and the semiconductor chips is made by bumps rather than conventional metal wires. As a result, the size and thickness of the package can be prevented from increasing. In addition, the electrical connection path between the semiconductor chip and the substrate is shortened by bumps, thereby enabling high-speed operation of the device.

본 발명의 상기한 바와 같은 구성에 따라, 반도체 칩들이 계단형 홈이 구비된 기판 내에 탑재된 구조이기 때문에 패키지의 크기 및 두께의 감소가 가능하다.또한, 반도체 칩과 기판의 접속을 범프를 사용함으로써, 연결 패스가 짧아지며, 이 에 따라, 소자의 고속 동작 구현이 가능하다.According to the above-described configuration of the present invention, the size and thickness of the package can be reduced because the semiconductor chips are mounted in a substrate having a stepped groove. Further, bumps are used for the connection between the semiconductor chip and the substrate. As a result, the connection path is shortened, thereby enabling high-speed operation of the device.

본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 바령이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been illustrated and described with reference to certain preferred embodiments, the invention is not so limited, and it is intended that the invention be construed without departing from the spirit or scope of the invention as defined by the following claims. It will be readily apparent to those skilled in the art that these various modifications and variations can be made.

Claims (1)

칩 스택 패키지에 있어서,In a chip stack package, 중심부에 계단형 홈이 구비되고, 상기 홈의 저면 및 상기 계단면에는 제 1 및 제 2 패드가 배열되며, 상기 제 1 및 제 2 패드들 각각은 비아 홀을 통해 하부면에 배열된 제 3 패드들과 각각 전기적으로 연결되는 기판;A stepped groove is provided at a central portion, and first and second pads are arranged on a bottom surface and the step surface of the groove, and each of the first and second pads is a third pad arranged at a lower surface through a via hole. Substrates electrically connected to the respective ones; 상부면에 에지 어레이 타입(edge array type)으로 본딩 패드들이 구비되고, 범프를 매개로 상기 기판의 계단형 홈 저면 및 계단면에 부착되면서, 상기 본딩 패드들이 상기 기판의 제 1 패드 및 제 2 패드와 전기적으로 접속되는 제 1 및 제 2 반도체 칩; Bonding pads are provided on an upper surface of an edge array type and attached to the bottom and step surfaces of the stepped grooves of the substrate via bumps, and the bonding pads are attached to the first pad and the second pad of the substrate. First and second semiconductor chips electrically connected with the first and second semiconductor chips; 상기 기판의 제 3 패드들 각각에 부착되어 전기적 접속 수단으로서의 기능을 하는 솔더 볼; 및Solder balls attached to each of the third pads of the substrate to function as electrical connection means; And 상기 계단형 홈의 계단면 측부 및 제 2 반도체 칩 상부를 포함하는 영역을 밀봉하는 봉지제;를 포함하는 것을 특징으로 하는 칩 스택 패키지.And an encapsulant for sealing an area including the stepped side of the stepped groove and the upper portion of the second semiconductor chip.
KR1020040112715A 2004-12-27 2004-12-27 Chip stack package KR20060074091A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165505A (en) * 2011-12-09 2013-06-19 三星电子株式会社 Methods of fabricating fan-out wafer level packages and packages formed by the methods
WO2015130264A1 (en) * 2014-02-26 2015-09-03 Intel Corporation Embedded multi-device bridge with through-bridge conductive via signal connection
US9455235B2 (en) 2013-11-25 2016-09-27 SK Hynix Inc. Thin embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165505A (en) * 2011-12-09 2013-06-19 三星电子株式会社 Methods of fabricating fan-out wafer level packages and packages formed by the methods
US9455235B2 (en) 2013-11-25 2016-09-27 SK Hynix Inc. Thin embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same
WO2015130264A1 (en) * 2014-02-26 2015-09-03 Intel Corporation Embedded multi-device bridge with through-bridge conductive via signal connection
TWI549252B (en) * 2014-02-26 2016-09-11 英特爾公司 Embedded multi-device bridge with through-bridge conductive via signal connection
US9754890B2 (en) 2014-02-26 2017-09-05 Intel Corporation Embedded multi-device bridge with through-bridge conductive via signal connection
US10229882B2 (en) 2014-02-26 2019-03-12 Intel Corporation Embedded multi-device bridge with through-bridge conductive via signal connection
US10797000B2 (en) 2014-02-26 2020-10-06 Intel Corporation Embedded multi-device bridge with through-bridge conductive via signal connection

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