JP2013135061A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- JP2013135061A JP2013135061A JP2011283790A JP2011283790A JP2013135061A JP 2013135061 A JP2013135061 A JP 2013135061A JP 2011283790 A JP2011283790 A JP 2011283790A JP 2011283790 A JP2011283790 A JP 2011283790A JP 2013135061 A JP2013135061 A JP 2013135061A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
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- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract
Description
本発明は、基板と半導体素子が封止樹脂体で封止されてなる半導体装置の製造方法に関するものである。 The present invention relates to a method for manufacturing a semiconductor device in which a substrate and a semiconductor element are sealed with a sealing resin body.
IGBT（Insulated Gate Bipolar Transistor）等の半導体素子を搭載した半導体装置（パワーモジュール）は、回路基板の表面に半導体素子がはんだ層を介して接続されたユニットがケース内に収容され、さらにこのケース内に封止樹脂体が形成された構成のものや、ケースレス構造であって、比較的硬質の封止樹脂体で回路基板や半導体素子が保護された構成のものなど、その形態は多様に存在している。なお、ケースレス構造のもの、ケースを具備する構造のもののいずれであっても、それらの下方にはヒートシンクや冷媒を還流させる冷却器などが配され、半導体素子からの熱をこれらに放熱させる構造が一般に適用されている。 A semiconductor device (power module) equipped with a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) contains a unit in which a semiconductor element is connected to the surface of a circuit board via a solder layer. Various forms exist, such as a structure in which a sealing resin body is formed on the surface, or a caseless structure in which a circuit board and a semiconductor element are protected by a relatively hard sealing resin body doing. In addition, whether it is a caseless structure or a structure having a case, a heat sink or a cooler that circulates the refrigerant is arranged below them, and the heat from the semiconductor element is dissipated to these Is generally applied.
ところで、ケースレス構造の半導体装置においては、回路基板や半導体素子の表面を保護する硬質の封止樹脂体と回路基板の間の接着力を高めるために、封止樹脂体と接着する回路基板の接着面（すなわち、回路基板の表面のうち、半導体素子を搭載するはんだ層が形成されていない領域）には多数の凹溝を設けて封止樹脂体との接着面積を増加させ、接着界面における接着力を高めようとする半導体装置も開発されており、たとえば特許文献１にこのような構成の半導体装置が開示されている。 By the way, in a caseless semiconductor device, in order to increase the adhesive force between a hard sealing resin body that protects the surface of a circuit board or a semiconductor element and the circuit board, the circuit board that adheres to the sealing resin body The bonding surface (that is, the region of the circuit board surface where the solder layer for mounting the semiconductor element is not formed) is provided with a large number of concave grooves to increase the bonding area with the sealing resin body, and at the bonding interface A semiconductor device for increasing the adhesive force has also been developed. For example, Patent Document 1 discloses a semiconductor device having such a configuration.
このようにケースレス構造であって、回路基板の表面に多数の凹溝を設けて封止樹脂体との接着面積を増加させる構成の半導体装置を図６に模擬している。同図で示す半導体装置Ｐ１は、Cu素材の基板Ｋの素子搭載面の上にはんだ層Ｈを介して半導体素子Ｓが接合され、基板Ｋと半導体素子Ｓが比較的硬質のエポキシ樹脂からなる封止樹脂体Ｆで封止されてなる半導体装置であり、基板Ｋのうち、封止樹脂体Ｆと接着される表面に多数の凹溝Ｋａ，…が設けられ、ここに封止樹脂体Ｆの一部が入り込んで双方の接着強度が高められた構成となっている。封止樹脂体Ｆの成形においては、大気雰囲気下、180℃程度の成形温度でエポキシ樹脂をトランスファー成形し、たとえば4時間以上の硬化時間を経て封止樹脂体Ｆが成形される。 A semiconductor device having such a caseless structure and having a structure in which a large number of grooves are provided on the surface of the circuit board to increase the adhesion area with the sealing resin body is simulated in FIG. In the semiconductor device P1 shown in the figure, a semiconductor element S is bonded onto an element mounting surface of a Cu substrate K via a solder layer H, and the substrate K and the semiconductor element S are made of a relatively hard epoxy resin. This is a semiconductor device sealed with a stop resin body F, and a plurality of concave grooves Ka,... Are provided on the surface of the substrate K that is bonded to the sealing resin body F. It has a configuration in which a part of it enters and the adhesive strength of both is increased. In the molding of the sealing resin body F, the epoxy resin is transfer molded at a molding temperature of about 180 ° C. in an air atmosphere, and the sealing resin body F is molded after a curing time of, for example, 4 hours or more.
特許文献１や図６で示されるケースレス構造の半導体装置においては、封止樹脂体と接着される基板表面に多数の凹溝が設けられて双方の接着界面が増加されたことにより、接着界面における接着力が高まると考えられており、理論上は確かに接着力が高められることになる。しかしながら、限られた範囲に多数の凹溝を設けることから個々の凹溝が細かくなってしまい、封止樹脂材が凹溝内に十分に充填されずにボイドが生じ、結果として接着力を十分に高めることができないことが本発明者等によって特定されている。 In the caseless structure semiconductor device shown in Patent Document 1 and FIG. 6, the adhesion interface is increased by providing a large number of concave grooves on the substrate surface to be bonded to the sealing resin body and increasing the adhesion interface between the two. It is thought that the adhesive strength in the case will increase, and theoretically, the adhesive strength will certainly be increased. However, since a large number of concave grooves are provided in a limited range, the individual concave grooves become finer, and the sealing resin material is not sufficiently filled in the concave grooves, resulting in voids, resulting in sufficient adhesive strength. It has been specified by the present inventors that it cannot be increased to a high level.
また、多数の凹溝を基板表面に形成することからそのための加工手間を要し、これが製造効率低下に繋がる恐れもある。たとえば流動性の良好な樹脂を適用して細かな凹溝内への樹脂の充填性を保証しようとすると、結局は、使用できる樹脂素材が限定されたり、あるいは、放熱性を高めるために樹脂内にフィラーを含有させたい場合に、フィラーの含有に起因して樹脂の流動性が低下することからフィラーの含有を断念せざるを得ないといった問題などもある。 Further, since a large number of concave grooves are formed on the substrate surface, it takes time for processing, which may lead to a decrease in manufacturing efficiency. For example, if a resin with good fluidity is applied to try to guarantee the filling of the resin in the fine groove, the resin material that can be used will eventually be limited, or in order to improve heat dissipation When it is desired to contain a filler, there is a problem that the fluidity of the resin is lowered due to the inclusion of the filler, so that the inclusion of the filler must be abandoned.
さらに、封止樹脂材によってCu基板表面が酸化し易く、脆弱な酸化被膜が介在することで封止樹脂体と基板の接着強度が著しく低下する恐れがある。 Further, the surface of the Cu substrate is easily oxidized by the sealing resin material, and the adhesive strength between the sealing resin body and the substrate may be significantly reduced due to the presence of a brittle oxide film.
一方、特許文献２には、Cuからなる基板にPAI（ポリアミドイミド）を含有したプライマーをプライマー処理し、封止樹脂材を175℃でモールド成形する技術が開示されている。
On the other hand,
このことを図７を参照して説明すると、同図で示す半導体装置Ｐ２は、Cu素材の基板Ｋの素子搭載面の上にはんだ層Ｈを介して半導体素子Ｓが接合され、基板Ｋと半導体素子Ｓが比較的硬質のエポキシ樹脂からなる封止樹脂体Ｆで封止されてなる半導体装置であり、基板Ｋのうち、封止樹脂体Ｆと接着される表面にプライマー処理層Ｑを形成しておき、これと封止樹脂体Ｆを接着させることによって接着強度が高められた構成となっている。 This will be described with reference to FIG. 7. In the semiconductor device P <b> 2 shown in FIG. 7, the semiconductor element S is bonded onto the element mounting surface of the Cu substrate K via the solder layer H, and the substrate K and the semiconductor are connected. A semiconductor device in which the element S is sealed with a sealing resin body F made of a relatively hard epoxy resin, and a primer treatment layer Q is formed on the surface of the substrate K bonded to the sealing resin body F. The adhesive strength is increased by adhering this to the sealing resin body F.
基板の露出面に凹凸が形成されていないことから封止樹脂体の成形に際してボイドの発生が抑制でき、封止樹脂材の流動性の制限も緩和される。また、PAI含有プライマー層が形成されていることから、Cu素材の基板表面の酸化が抑制でき、もって封止樹脂体と基板の接着強度の向上が期待できるはずである。 Since the unevenness is not formed on the exposed surface of the substrate, generation of voids can be suppressed during molding of the sealing resin body, and the restriction on the fluidity of the sealing resin material is eased. In addition, since the PAI-containing primer layer is formed, the oxidation of the Cu material substrate surface can be suppressed, and therefore the improvement in the adhesive strength between the sealing resin body and the substrate should be expected.
そこで、本発明者等は、図６，７にかかる従来の半導体装置Ｐ１，Ｐ２を構成する基板と封止樹脂体を接着させた不図示の試験体を作成し、不図示のシェアテスターで封止樹脂体の途中位置をせん断した際の封止樹脂体と基板の間の接着強度を測定する実験をおこなった。なお、この実験条件の詳細は後述する。実験結果を図８に示している。 Therefore, the present inventors have created a test body (not shown) in which a substrate constituting the conventional semiconductor devices P1 and P2 shown in FIGS. 6 and 7 and a sealing resin body are bonded, and sealed with a shear tester (not shown). An experiment was conducted to measure the adhesive strength between the sealing resin body and the substrate when the middle position of the stopping resin body was sheared. Details of the experimental conditions will be described later. The experimental results are shown in FIG.
同図より、半導体装置Ｐ１の試験体、Ｐ２の試験体ともに、接着強度に大きな差異はなく、Ｐ２の試験体の方が接着強度が低下するという結果が得られている。 From the figure, there is no significant difference in the bonding strength between the test body of the semiconductor device P1 and the test body of P2, and the result is that the bonding strength of the P2 test body is lower.
この比較例に関する実験結果を踏まえ、本発明者等は、Cu素材の基板表面にPAI含有プライマー処理をおこなうことを前提としながら、エポキシ樹脂からなる封止樹脂材の成形温度を最適な温度範囲に制御することにより、封止樹脂体と基板の接着強度が従来構造の半導体装置に比して格段に高くなる製造方法を見出し、本願発明に至っている。 Based on the experimental results relating to this comparative example, the present inventors assumed that the PAI-containing primer treatment is performed on the substrate surface of the Cu material, and set the molding temperature of the sealing resin material made of epoxy resin to the optimum temperature range. By controlling, a manufacturing method in which the adhesive strength between the sealing resin body and the substrate is remarkably higher than that of a semiconductor device having a conventional structure has been found, and the present invention has been achieved.
本発明は上記する問題に鑑みてなされたものであり、Cu素材の基板表面にPAI含有プライマー処理をおこなった後にエポキシ樹脂からなる封止樹脂材を成形して半導体装置を製造する製造方法に関し、成形温度を最適な温度範囲に制御することにより、封止樹脂体と基板の接着強度を従来構造の半導体装置に比して格段に高くすることのできる半導体装置の製造方法を提供することを目的とする。 The present invention has been made in view of the above problems, and relates to a manufacturing method for manufacturing a semiconductor device by molding a sealing resin material made of an epoxy resin after performing a PAI-containing primer treatment on a substrate surface of a Cu material, An object of the present invention is to provide a method for manufacturing a semiconductor device, in which the molding temperature is controlled within an optimum temperature range, whereby the adhesive strength between the sealing resin body and the substrate can be remarkably increased as compared with a conventional semiconductor device. And
前記目的を達成すべく、本発明による半導体装置の製造方法は、CuもしくはCu合金からなる基板の素子搭載面の上にはんだ層を介して半導体素子が接続され、基板と半導体素子がエポキシ樹脂からなる封止樹脂体で封止されてなる半導体装置の製造方法であって、封止樹脂体を成形する前段で、基板の表面のうち、少なくとも外部に露出する箇所にPAI含有プライマーをプライマー処理し、145℃〜165℃の成形温度範囲で封止樹脂体を成形するものである。 In order to achieve the above object, a semiconductor device manufacturing method according to the present invention includes a semiconductor element connected to an element mounting surface of a substrate made of Cu or Cu alloy via a solder layer, and the substrate and the semiconductor element are made of epoxy resin. A method of manufacturing a semiconductor device that is sealed with a sealing resin body, wherein, before forming the sealing resin body, a PAI-containing primer is primer-treated on at least a portion of the surface of the substrate exposed to the outside. The sealing resin body is molded in a molding temperature range of 145 ° C to 165 ° C.
本発明の製造方法は、基板のうち、はんだ層を介して半導体素子と接続される領域以外の領域、すなわち、本来的には封止樹脂体と密着する領域（露出表面）に封止樹脂体の成形の前段でPAI（ポリアミドイミド）含有プライマーをプライマー処理しておくことと、エポキシ樹脂からなる封止樹脂材の射出（射出成形、トランスファー成形など）の際の成形温度を145℃〜165℃の温度範囲でおこなうこと、を特徴とするものである。 In the manufacturing method of the present invention, a sealing resin body is formed in a region other than a region connected to a semiconductor element through a solder layer, that is, a region (exposed surface) that is essentially in close contact with the sealing resin body. The primer temperature of the PAI (polyamideimide) -containing primer is primed in the previous stage of molding, and the molding temperature during injection (injection molding, transfer molding, etc.) of the sealing resin material made of epoxy resin is 145 ° C to 165 ° C It is performed in the temperature range.
前者の特徴構成により、基板の露出表面の凹凸処理が不要となり、凹凸内に生じ得るボイドによって接着強度が低下するといった課題を解消でき、基板の該露出表面の酸化を抑制することができる。 With the former characteristic configuration, it is not necessary to perform uneven processing on the exposed surface of the substrate, and the problem that the adhesive strength is reduced due to voids that can be generated in the uneven surface can be eliminated, and oxidation of the exposed surface of the substrate can be suppressed.
一方、後者の特徴構成により、基板のCuがPAI含有プライマー内に広範囲に拡散することを防止でき、PAIの有する高接着力性能、高耐熱性能を期待することができ、このプライマーを介して封止樹脂体と基板の高い接続強度を奏するものとなる。なお、既述する特許文献２で開示する170℃以上の温度条件では、基板のCuがプライマー内に拡散しながら酸化され易くなってしまい、PAIの有する上記特性を期待し難くなってしまうことが本発明者等の知見によって分かっている。
On the other hand, the latter characteristic configuration prevents the Cu of the substrate from diffusing extensively into the PAI-containing primer, and can be expected to have high adhesion performance and high heat resistance performance possessed by PAI. High connection strength between the resin stopper and the substrate is achieved. In addition, under the temperature condition of 170 ° C. or higher disclosed in
ここで、「封止樹脂体を成形する前段」とは、封止樹脂体の成形前の多様な段階を包含する意味であり、基板に半導体素子がはんだ付けされた後に基板の露出表面にプライマー処理をおこなってもよいし、基板表面のうち、はんだ層形成箇所にマスキングを施してその他の表面部位にプライマー処理を施し、マスキングを剥がして半導体素子をはんだ付けしてもよい。 Here, “the pre-stage of molding the sealing resin body” means various stages before the molding of the sealing resin body, and the primer is applied to the exposed surface of the board after the semiconductor element is soldered to the board. The surface of the substrate may be subjected to masking at the solder layer forming portion and the other surface portion may be subjected to primer treatment, and the masking may be removed to solder the semiconductor element.
また、「基板」とは、回路基板、もしくは回路基板と絶縁基板の組み合わせ、もしくは回路基板と絶縁基板と応力緩和基板の組み合わせなど、のすべてを総称するものである。また、この絶縁基板は、たとえば純Alからなる基板とAlN(窒化アルミニウム)からなる基板を積層してなる積層体（DBA）であってもよいことは勿論のことである。また、この半導体装置は、上記基板の下方に、ヒートシンク板や、ヒートシンク板と冷媒還流路を具備する冷却器とのアルミダイキャスト一体成形体を具備するものであってもよい。 The “substrate” is a general term for a circuit board, a combination of a circuit board and an insulating substrate, or a combination of a circuit board, an insulating substrate, and a stress relaxation substrate. Of course, this insulating substrate may be a laminate (DBA) formed by laminating a substrate made of pure Al and a substrate made of AlN (aluminum nitride), for example. In addition, the semiconductor device may include an aluminum die-cast integrally formed body of a heat sink plate or a cooler including a heat sink plate and a refrigerant reflux path below the substrate.
また、封止樹脂体がエポキシ樹脂からなることで比較的硬質な封止樹脂体で半導体素子等を防護することができるため、ケースレス構造の半導体装置に好適である。なお、封止樹脂体の放熱性を高めるべく、エポキシ樹脂にシリカやアルミナ、窒化ホウ素、窒化ケイ素、炭化ケイ素、酸化マグネシウム等の熱伝導性フィラーが含有された素材を適用してもよい。 In addition, since the sealing resin body is made of an epoxy resin, the semiconductor element and the like can be protected by a relatively hard sealing resin body, which is suitable for a semiconductor device having a caseless structure. In addition, in order to improve the heat dissipation of the sealing resin body, a material in which a thermally conductive filler such as silica, alumina, boron nitride, silicon nitride, silicon carbide, or magnesium oxide is contained in an epoxy resin may be applied.
また、「PAI含有プライマー」とは、PAIを主成分として含み、その他の成分は任意であって、エポキシ樹脂やポリオール樹脂などの他の樹脂成分、硬化剤（フェノール樹脂やアミノ樹脂などからなる）などが所望の含有割合で混合されたプライマー組成物のことである。なお、PAIにエポキシ樹脂を加えることで低温硬化性、高接着性が得られる。 The “PAI-containing primer” includes PAI as a main component, and other components are optional. Other resin components such as an epoxy resin and a polyol resin, a curing agent (made of a phenol resin, an amino resin, etc.) These are primer compositions mixed in a desired content ratio. In addition, low temperature curability and high adhesiveness can be obtained by adding an epoxy resin to PAI.
また、本発明による半導体装置の製造方法の好ましい実施の形態として、前記プライマー処理の前段で基板の表面からCu酸化被膜を除去する製造方法を挙げることができる。 Further, as a preferred embodiment of the method for producing a semiconductor device according to the present invention, a production method for removing a Cu oxide film from the surface of the substrate before the primer treatment can be mentioned.
Cu酸化被膜を除去する方法としては、酸化被膜除去剤を用いて洗浄する方法を挙げることができ、Cu素材の基板の露出表面に形成され易い酸化被膜を予め除去しておくことで基板とプライマーとの接着性が良好となる。 As a method of removing the Cu oxide film, there can be mentioned a method of cleaning using an oxide film removing agent. By removing in advance an oxide film that is easily formed on the exposed surface of the Cu substrate, the substrate and the primer are removed. Adhesiveness is improved.
さらに、本発明による半導体装置の製造方法の好ましい実施の形態として、少なくともプライマー処理が真空雰囲気下、もしくは不活性ガス雰囲気下でおこなわれる製造方法を挙げることができる。 Furthermore, as a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, a manufacturing method in which at least primer treatment is performed in a vacuum atmosphere or an inert gas atmosphere can be mentioned.
ここで、「少なくともプライマー処理が」とは、プライマー処理工程を真空雰囲気（減圧雰囲気を含む）下等でおこなうこと、プライマー処理工程に加えて射出成形工程（トランスファー成形）を真空雰囲気下等でおこなうこと、プライマー処理工程と射出成形工程に加えて樹脂が硬化するまでのキュア工程までの全工程を真空雰囲気下等でおこなうこと、などを包含する意味である。 Here, “at least primer treatment” means that the primer treatment step is performed in a vacuum atmosphere (including a reduced pressure atmosphere) or the like, and the injection molding step (transfer molding) is performed in a vacuum atmosphere or the like in addition to the primer treatment step. In addition to the primer treatment step and the injection molding step, all the steps up to the curing step until the resin is cured are performed in a vacuum atmosphere or the like.
本発明者等の検証によれば、PAI含有プライマーで基板の露出表面をプライマー処理すること、145℃〜165℃の成形温度範囲で封止樹脂体を成形すること、に加えて、真空雰囲気下等でプライマー処理等をおこなうことで封止樹脂体と基板の接着強度が一層高めることが知見として得られている。 According to the verification by the present inventors, in addition to priming the exposed surface of the substrate with a PAI-containing primer and molding a sealing resin body at a molding temperature range of 145 ° C. to 165 ° C., in a vacuum atmosphere It has been found as a finding that the adhesion strength between the sealing resin body and the substrate can be further improved by performing primer treatment or the like.
上記する本発明の製造方法で得られた半導体装置は、上記のごとく基板と封止樹脂体の接着強度が極めて高いものであることから、耐衝撃性、耐久性に優れており、さらには、基板の露出表面にプライマー処理を施すだけの簡易な製法改良ゆえに基板表面に凹凸を付したりすることに比べて製法も簡易となり、このことは製造コスト低減に繋がる。これらのことから、上記する本発明の製造方法で得られた半導体装置は、搭載部品等に対して高耐久性と製造コスト低減を要求する近時のハイブリッド車や電気自動車に車載されるインバータ等への適用に最適である。 The semiconductor device obtained by the manufacturing method of the present invention described above has excellent impact resistance and durability because the bonding strength between the substrate and the sealing resin body is extremely high as described above. Since the manufacturing method is simply improved by simply applying the primer treatment to the exposed surface of the substrate, the manufacturing method becomes simpler as compared with the case where the surface of the substrate is uneven, which leads to a reduction in manufacturing cost. For these reasons, the semiconductor device obtained by the manufacturing method of the present invention described above is an inverter mounted on a recent hybrid vehicle or electric vehicle that requires high durability and reduced manufacturing cost for mounted components and the like. Ideal for application to.
以上の説明から理解できるように、本発明の半導体装置の製造方法によれば、基板のうち、本来的には封止樹脂体と密着する領域（露出表面）に封止樹脂体の成形の前段でPAI含有プライマーをプライマー処理しておくこと、および、エポキシ樹脂からなる封止樹脂材の射出の際の成形温度を145℃〜165℃の温度範囲でおこなうこと、によって、封止樹脂体と基板の接着強度を高めることができる。 As can be understood from the above description, according to the method for manufacturing a semiconductor device of the present invention, the former stage of molding of the sealing resin body in the region (exposed surface) that is essentially in close contact with the sealing resin body of the substrate. By sealing the PAI-containing primer with a primer, and performing the molding temperature at the time of injection of the sealing resin material made of epoxy resin in the temperature range of 145 ° C to 165 ° C, the sealing resin body and the substrate The adhesive strength can be increased.
以下、図面を参照して本発明の半導体装置の製造方法とこの方法によって製造された半導体装置の一実施の形態を説明する。なお、製造される半導体装置は図示例のものに何等限定されるものではなく、他の構成要素として、他の構成要素、たとえば、絶縁基板や応力緩和板、ヒートシンクや冷却器などがさらに付加された半導体装置であってもよく、これらの積層体がケース内に収容された形態、ケース内に封止樹脂体がポッティングされた形態などであってもよい。 A semiconductor device manufacturing method and a semiconductor device manufactured by the method according to an embodiment of the present invention will be described below with reference to the drawings. The semiconductor device to be manufactured is not limited to the example shown in the figure, and other components such as an insulating substrate, a stress relaxation plate, a heat sink, and a cooler are further added as other components. The semiconductor device may be a configuration in which these stacked bodies are accommodated in a case, a configuration in which a sealing resin body is potted in the case, or the like.
（半導体装置とその製造方法の実施の形態）
図１は本発明の製造方法で製造された半導体装置の一実施の形態の縦断面図である。図示する半導体装置１０は、CuもしくはCu合金からなる基板２（回路基板）の上にはんだ層３を介して半導体素子１（ICチップやトランジスタ、ダイオードなど）が接続され、回路基板２の露出表面にPAI含有プライマー層５が形成され、PAI含有プライマー層５の表面、はんだ層３の露出部および半導体素子１が比較的硬質のエポキシ樹脂からなる封止樹脂体４で包囲されてその全体が大略構成されており、ケースレス構造を呈するものである。
(Embodiment of semiconductor device and manufacturing method thereof)
FIG. 1 is a longitudinal sectional view of an embodiment of a semiconductor device manufactured by the manufacturing method of the present invention. In the illustrated
ここで、封止樹脂体４を形成するエポキシ樹脂内には、シリカやアルミナ、窒化ホウ素、窒化ケイ素、炭化ケイ素、酸化マグネシウム等の熱伝導性フィラーが含有されていてもよい。
Here, the epoxy resin forming the sealing
はんだ層３は、Pb系はんだ、Pbフリーはんだのいずれであってもよいが、環境影響負荷低減を図るべく、Sn−Ag系はんだ、Sn−Cu系はんだ、Sn−Ag−Cu系はんだ、Sn−Zn系はんだ、Sn−Sb系はんだなどのPbフリーはんだからなるものが好ましい。
The
PAI含有プライマーは、PAIを主成分として含み、その他の成分としては、エポキシ樹脂やポリオール樹脂などの他の樹脂成分、硬化剤（フェノール樹脂やアミノ樹脂などからなる）などが所望の含有割合で混合されたプライマー組成物からなる。 PAI-containing primer contains PAI as the main component, and as other components, other resin components such as epoxy resin and polyol resin, curing agent (consisting of phenol resin, amino resin, etc.), etc. are mixed in the desired content ratio Of the prepared primer composition.
次に、図示する半導体装置１０の製造方法を概説する。
Next, a method for manufacturing the
まず、基板２の表面のうち、はんだ層３が形成される箇所に不図示のマスキングを施してその他の表面部位にPAI含有プライマーを塗工（プライマー処理）し、これが硬化してPAI含有プライマー層５が形成された段階でマスキングを剥がす。
First, masking (not shown) is applied to the surface of the
次に、半導体素子１を基板２の中央領域にはんだ層３を介してはんだ付けし、基板２と半導体素子１の組み付けユニットを不図示の成形型内に収容し、エポキシ樹脂をトランスファー成形し、熱硬化させて封止樹脂体４が成形されることで図１で示す半導体装置１０が製造される。
Next, the semiconductor element 1 is soldered to the central region of the
この製造過程において、トランスファー成形の際の成形温度を145℃〜165℃の温度範囲でおこなうことにより、基板２のCuがPAI含有プライマー層５の内部に拡散することのを防止することができ、PAIの有する高接着力性能、高耐熱性能を期待することのできるプライマー層５を介して封止樹脂体４と基板２を高い接続強度で接続することができる。
In this manufacturing process, by performing the molding temperature at the time of transfer molding in the temperature range of 145 ° C. to 165 ° C., Cu of the
また、プライマー処理工程を真空雰囲気もしくは窒素ガスやアルゴンガス等の不活性ガス雰囲気下でおこなうこと、もしくは、プライマー処理工程に加えて射出成形工程を真空雰囲気下等でおこなうこと、もしくはプライマー処理工程と射出成形工程に加えて樹脂が硬化するまでのキュア工程までの全工程を真空雰囲気下等でおこなうことにより、封止樹脂体４と基板２の接着強度を一層高めることができる。
In addition, the primer treatment process is performed in a vacuum atmosphere or an inert gas atmosphere such as nitrogen gas or argon gas, or the injection molding process is performed in a vacuum atmosphere in addition to the primer treatment process, or the primer treatment process. By performing all the steps up to the curing step until the resin is cured in addition to the injection molding step in a vacuum atmosphere or the like, the adhesive strength between the sealing
[基板（の表面のフライマー層）と封止樹脂体の接着強度を評価する実験とその結果]
本発明者等は、本発明の製造方法で得られた基板（の表面のフライマー層）と封止樹脂体の接着強度を評価する実験をおこなった。ここで、図２は、実験で使用した試験体と試験概要を模擬した図である。
[Experiment to evaluate the bond strength between the substrate (the surface of the flyer layer) and the sealing resin body and its results]
The present inventors conducted an experiment to evaluate the adhesive strength between the substrate (the surface of the flyer layer) obtained by the production method of the present invention and the sealing resin body. Here, FIG. 2 is a diagram simulating the test body and the test outline used in the experiment.
同図において、Cu素材の基板試験片Ｍ３の表面にPAI含有プライマーを塗布し、乾燥させてPAI含有プライマー層Ｍ１を形成し、PAI含有プライマー層Ｍ１の上にエポキシ樹脂をトランスファー成形し、アフターキュア（硬化）させて封止樹脂体試験片Ｍ２を成形してPAI含有プライマー層Ｍ１と接着させ、試験片Ｍを製作した。 In the figure, a PAI-containing primer is applied to the surface of a Cu substrate test piece M3 and dried to form a PAI-containing primer layer M1, and an epoxy resin is transfer molded onto the PAI-containing primer layer M1, and aftercure. The cured resin test piece M2 was molded and adhered to the PAI-containing primer layer M1, and the test piece M was manufactured.
本実験では、成形時の温度条件を種々変化させ、大気雰囲気下、4時間の硬化時間で試験片を作成し、それぞれの試験片に対してシェアテスターＴを使用して（移動方向はＸ方向）接着強度を測定している。 In this experiment, test conditions were prepared by changing the temperature conditions at the time of molding in various atmospheres, with a curing time of 4 hours in an air atmosphere, and a shear tester T was used for each test specimen (moving direction was X direction). ) The adhesive strength is measured.
ここで、シェアテスターＴのシェア速度は50μm/s、シェア高さは30μm、測定温度は25±3℃である。封止樹脂材の硬化温度と基板−封止樹脂体の接着強度の関係に関する実験結果を図３に示している。 Here, the shear rate of the shear tester T is 50 μm / s, the shear height is 30 μm, and the measurement temperature is 25 ± 3 ° C. The experimental result regarding the relationship between the curing temperature of the sealing resin material and the bond strength between the substrate and the sealing resin body is shown in FIG.
同図では、各試験片の接着強度を近似曲線で繋いだグラフをともに示している。同グラフより、エポキシ樹脂からなる封止樹脂材の硬化温度が145℃、165℃でともに変曲点を迎え、145℃〜165℃の間で16MPa程度と最も高い接着強度を示すことが実証されている。 In the same figure, the graph which connected the adhesive strength of each test piece with the approximate curve is shown together. From this graph, it is demonstrated that the curing temperature of the epoxy resin sealing resin material reaches the inflection point at both 145 ° C and 165 ° C, and shows the highest adhesive strength of about 16 MPa between 145 ° C and 165 ° C. ing.
なお、図８で示す従来構造の半導体装置Ｐ１，Ｐ２の試験体も図２と同じような方法で作成しており、シェアテスターＴを使用して上記条件で接着強度を測定したものである。 In addition, the test body of the semiconductor devices P1 and P2 having the conventional structure shown in FIG. 8 is also prepared by the same method as in FIG. 2, and the adhesive strength is measured using the shear tester T under the above conditions.
図８の結果と図３の結果を比較すると明らかであるが、従来構造の半導体装置Ｐ１の試験体の接着強度に対して2倍以上、従来構造の半導体装置Ｐ２の試験体の接着強度に対して3倍以上の接着強度を有することが分かる。 8 and FIG. 3 are clearly compared, but it is more than twice the bond strength of the test piece of the semiconductor device P1 having the conventional structure, and the bond strength of the test piece of the semiconductor device P2 having the conventional structure. It can be seen that the adhesive strength is three times or more.
この実験結果より、エポキシ樹脂からなる封止樹脂材の硬化温度、すなわち、成形温度を145℃〜165℃の間に調整するのがよいと規定することができる。 From this experimental result, it can be defined that the curing temperature of the sealing resin material made of epoxy resin, that is, the molding temperature, should be adjusted between 145 ° C. and 165 ° C.
次に、本発明者等は、トランスファー成形とアフターキュアの際の温度条件、時間条件、雰囲気条件を種々変化させて試験片を作成し、それぞれの試験片に対して上記と同様にシェアテスターＴを使用して（移動方向はＸ方向）接着強度を測定している。 Next, the present inventors made test pieces by changing various temperature conditions, time conditions, and atmospheric conditions during transfer molding and after-curing, and for each test piece, the share tester T (The moving direction is the X direction) is used to measure the adhesive strength.
実施例1の試験片は、プライマー処理前に酸化銅被膜を除去し、プライマー処理、トランスファー成形、キュアの全工程を真空雰囲気下でおこなったものである。また、実施例2の試験片は、成形温度が150℃で硬化時間が2時間のもの、実施例3の試験片は、成形温度が150℃で、プライマー処理、トランスファー成形、キュアの全工程を真空雰囲気下でおこなったものである。さらに、実施例4の試験片は、プライマー処理前に酸化銅被膜を除去し、成形温度が150℃で硬化時間が2時間であって、プライマー処理、トランスファー成形、キュアの全工程を真空雰囲気下でおこなったものである。測定結果を図４に示している。 In the test piece of Example 1, the copper oxide film was removed before the primer treatment, and all the steps of primer treatment, transfer molding, and curing were performed in a vacuum atmosphere. In addition, the test piece of Example 2 has a molding temperature of 150 ° C. and a curing time of 2 hours, and the test piece of Example 3 has a molding temperature of 150 ° C., and all steps of primer treatment, transfer molding, and curing are performed. This was performed in a vacuum atmosphere. Further, the test piece of Example 4 was obtained by removing the copper oxide film before the primer treatment, the molding temperature was 150 ° C., the curing time was 2 hours, and the primer treatment, transfer molding, and curing steps were all performed in a vacuum atmosphere. It was done in. The measurement results are shown in FIG.
同図において、温度制御のみの場合の接着強度（約15MPa）を点線で示している。実施例1〜4の中でも、プライマー処理前に酸化銅被膜の除去をおこない、全工程を真空雰囲気下でおこなう実施例4の結果が温度制御のみの場合よりも格段に高い接着強度を有することが実証されている。 In the figure, the adhesive strength (about 15 MPa) in the case of only temperature control is indicated by a dotted line. Among Examples 1 to 4, the copper oxide film is removed before the primer treatment, and the results of Example 4 in which all steps are performed in a vacuum atmosphere may have much higher adhesive strength than the case of only temperature control. Proven.
また、図５には、Cu素材の基板とPAI含有プライマー層の界面の状態を示したTEM画像図を示しており、封止樹脂材の硬化温度が175℃の場合のものである。 FIG. 5 shows a TEM image showing the state of the interface between the Cu substrate and the PAI-containing primer layer, and shows the case where the curing temperature of the sealing resin material is 175 ° C.
この硬化温度で封止樹脂材を成形すると、基板のCuが酸化銅としてプライマー層に拡散することが確認できる。 When the sealing resin material is molded at this curing temperature, it can be confirmed that Cu of the substrate diffuses into the primer layer as copper oxide.
以上、本発明の実施の形態を図面を用いて詳述してきたが、具体的な構成はこの実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲における設計変更等があっても、それらは本発明に含まれるものである。 The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. They are also included in the present invention.
１…半導体素子、２…基板（回路基板）、３…はんだ層、４…封止樹脂体、５…PAI含有プライマー層、１０…半導体装置 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Board | substrate (circuit board), 3 ... Solder layer, 4 ... Sealing resin body, 5 ... PAI containing primer layer, 10 ... Semiconductor device
Claims (3)
封止樹脂体を成形する前段で、基板の表面のうち、少なくとも外部に露出する箇所にPAI含有プライマーをプライマー処理し、145℃〜165℃の成形温度範囲で封止樹脂体を成形する半導体装置の製造方法。 A semiconductor device manufacturing method in which a semiconductor element is connected via a solder layer on an element mounting surface of a substrate made of Cu or Cu alloy, and the substrate and the semiconductor element are sealed with a sealing resin body made of epoxy resin. There,
A semiconductor device that forms a sealing resin body in a molding temperature range of 145 ° C. to 165 ° C. by primer-treating a PAI-containing primer at least on a portion of the surface of the substrate that is exposed to the outside before molding the sealing resin body Manufacturing method.
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| JP2018046192A (en) * | 2016-09-15 | 2018-03-22 | 三菱マテリアル株式会社 | Manufacturing method of resin sealed power module |
| JP2019087575A (en) * | 2017-11-02 | 2019-06-06 | トヨタ自動車株式会社 | Method for manufacturing semiconductor device |
| WO2019124414A1 (en) | 2017-12-20 | 2019-06-27 | 日立化成株式会社 | Polyamide imide resin, polyamide imide resin composition, and semiconductor device using polyamide imide resin and polyamide imide resin composition |
| JP2020096153A (en) * | 2018-12-13 | 2020-06-18 | 力成科技股▲分▼有限公司 | Semiconductor package structure and manufacturing method of the same |
| WO2021045004A1 (en) | 2019-09-06 | 2021-03-11 | 昭和電工マテリアルズ株式会社 | Polyamide imide resin, resin composition and semiconductor device |
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| JP2020096153A (en) * | 2018-12-13 | 2020-06-18 | 力成科技股▲分▼有限公司 | Semiconductor package structure and manufacturing method of the same |
| WO2021045004A1 (en) | 2019-09-06 | 2021-03-11 | 昭和電工マテリアルズ株式会社 | Polyamide imide resin, resin composition and semiconductor device |
| KR20220010519A (en) | 2019-09-06 | 2022-01-25 | 쇼와덴코머티리얼즈가부시끼가이샤 | Polyamideimide resin, resin composition, and semiconductor device |
| WO2022185718A1 (en) | 2021-03-04 | 2022-09-09 | 昭和電工マテリアルズ株式会社 | Poly(amide-imide) resin, resin composition, and semiconductor device |
| KR20230135678A (en) | 2021-03-04 | 2023-09-25 | 가부시끼가이샤 레조낙 | Polyamideimide resin, resin composition, and semiconductor device |
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