CN210040172U

CN210040172U - Chip packaging structure and electronic equipment

Info

Publication number: CN210040172U
Application number: CN201920929428.2U
Authority: CN
Inventors: 吴宝全; 蒋万里
Original assignee: Shenzhen Huiding Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2018-09-29
Filing date: 2018-09-29
Publication date: 2020-02-07
Anticipated expiration: 2028-09-29
Also published as: CN209104140U

Abstract

The disclosure relates to the technical field of chip packaging, and discloses a chip packaging structure and an electronic device. The chip packaging structure comprises a substrate, a connector, an image sensing module and an auxiliary module, wherein the image sensing module and the auxiliary module are integrally packaged by utilizing the substrate; the image sensing module comprises an image sensing chip, and the image sensing chip is packaged on the first surface of the substrate; the auxiliary module comprises at least one optical auxiliary chip, and the at least one optical auxiliary chip is packaged on the second surface of the substrate and is electrically connected with the image sensing chip through the substrate; the connector is connected to the substrate and used for electrically connecting the chip packaging structure with an external unit. The embodiment of the disclosure can improve the integration level of the chip packaging module and reduce the total volume of the module.

Description

Chip packaging structure and electronic equipment

The application is a divisional application of a utility model with application date of 2018, 29.9 and 201821611765.9, and a name of "chip package structure and electronic device".

Technical Field

The present disclosure relates to the field of chip packaging technologies, and more particularly, to a chip packaging structure and an electronic device.

Background

Along with the progress of scientific technology and the gradual increase of user demands, the integration level of electronic equipment is higher and higher. In order to meet the trend, various components and devices used in electronic devices are also moving toward higher integration, smaller size and higher standardization.

However, the optical fingerprint chip, as an important component of an electronic device with an optical fingerprint identification function, is affected by its packaging manner, and the integration level is greatly limited. The current optical fingerprint chip generally uses the optical fingerprint module packaging scheme of disconnect-type, and the image sensing chip, auxiliary chip and the connector of this type of optical fingerprint module paste respectively on the base plate of difference usually, then realize the electricity through Flexible Circuit board (FPC) with auxiliary module, image sensing chip module, connector etc. and connect. The mode has low integration level and large volume, and is difficult to realize standardization and meet the market demand.

SUMMERY OF THE UTILITY MODEL

To solve the problems in the background art, the present disclosure provides a chip packaging structure and an electronic device, which effectively improve the chip packaging integration level, reduce the size, and simultaneously improve the standardization level.

In a first aspect, a chip package structure is provided, including: the image sensing module and the auxiliary module are integrally packaged by utilizing the substrate; the image sensing module comprises an image sensing chip, and the image sensing chip is packaged on the first surface of the substrate; the auxiliary module comprises at least one optical auxiliary chip, and the at least one optical auxiliary chip is packaged on the second surface of the substrate and is electrically connected with the image sensing chip through the substrate; the connector is connected to the substrate and used for electrically connecting the chip packaging structure with an external unit.

As an optional implementation of the chip package structure provided by the present disclosure, the connector is connected to the first surface or the second surface of the substrate; specifically, the image sensing chip and the at least one optical auxiliary chip are respectively disposed on the main body portion of the first surface and the second surface of the substrate, and the connector is connected to the edge portion of the first surface or the second surface of the substrate.

As an optional implementation of the chip package structure provided by the present disclosure, the substrate further includes a plurality of side surfaces, and the connector is disposed on one of the side surfaces of the substrate.

As an optional implementation of the chip package structure provided by the present disclosure, the first surface is a main surface of the substrate, and the second surface is a back surface of the substrate facing away from the main surface.

As an optional implementation of the chip package structure provided by the present disclosure, the image sensing module further includes a lens module, and the lens module is disposed above the image sensing chip and is used for converging or guiding a target light signal to the image sensing chip.

As an optional implementation of the chip package structure provided by the present disclosure, the lens module includes a lens barrel and an optical lens accommodated in the lens barrel, the image sensing chip includes an optical sensing array, and the optical lens and the optical sensing array are arranged in an optical path alignment manner.

As an optional implementation of the chip package structure provided by the present disclosure, the lens module further includes an optical filter, the optical filter is accommodated in the lens barrel and located between the optical lens and the image sensing chip, and the optical filter is used for isolating external interference light to prevent the external interference light from entering the optical sensing array.

As an optional implementation of the chip package structure provided in the present disclosure, the image sensing module is an optical fingerprint detection module, and the target light signal is fingerprint detection light reflected from a surface of a finger, where the fingerprint detection light is converged or guided to the image sensing chip by the optical lens, and the image sensing chip is configured to detect the fingerprint detection light for optical fingerprint imaging.

As an optional implementation of the chip package structure provided by the present disclosure, the image sensing chip is attached to the first surface of the substrate by a first adhesive, and the pad on the surface of the image sensing chip is connected to the electrical connection point on the first surface of the substrate by a first metal wire.

As an optional implementation of the chip package structure provided by the present disclosure, the optical auxiliary chip is attached to the second surface of the substrate by a second adhesive, and the pad on the surface of the optical auxiliary chip is connected to the electrical connection point on the second surface of the substrate by a second metal wire, and the optical auxiliary chip is electrically connected to the image sensing chip by the connection circuit of the substrate.

As an optional implementation of the chip package structure provided in the present disclosure, the substrate is a silicon substrate having through-silicon vias, the image sensing chip is connected to the first surface of the silicon substrate through a pad on a bottom surface of the image sensing chip, and at least a portion of the pad of the image sensing chip is electrically connected to the through-silicon vias of the silicon substrate.

As an optional implementation of the chip package structure provided by the present disclosure, the optical sub-chip is connected to the second surface of the silicon substrate by a bonding pad on a bottom surface thereof in a flip-chip bonding manner, and at least a portion of the bonding pad of the optical sub-chip is electrically connected to the image sensing chip by the through-silicon via.

As an optional implementation of the chip package structure provided by the present disclosure, the auxiliary module further includes at least one capacitor connected to an edge region of the second surface of the substrate by solder.

As an optional implementation of the chip package structure provided by the present disclosure, the auxiliary module further includes a molding compound, where the molding compound seals the optical auxiliary chip and the at least one capacitor on the second surface of the substrate, and makes the surface of the chip package structure flat.

In a second aspect, an electronic device is provided, which includes a display screen and an optical fingerprint detection device located below the display screen, where the optical fingerprint detection device includes the chip package structure described above.

This disclosed embodiment is through encapsulating image sensing chip and optics auxiliary chip respectively on two surfaces of base plate, realizes image sensing chip with optics auxiliary chip's integral type encapsulation not only can reduce the step of chip encapsulation, improves the integrated level of chip encapsulation to reduce the total volume of chip package module, improved the standardization level of chip encapsulation simultaneously.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a schematic diagram of a chip package structure according to one embodiment of the present disclosure;

FIG. 2 is a flow chart of a method of chip packaging according to one embodiment of the present disclosure;

fig. 3 to 9 are schematic views illustrating a manufacturing process of the chip package structure shown in fig. 1;

fig. 10 is a schematic diagram of a chip package structure according to another embodiment of the present disclosure;

fig. 11 is a flow chart of a chip packaging method according to another embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter may be practiced without these specific details or with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic diagram of a chip package structure according to one embodiment of the present disclosure. As shown in fig. 1, the chip package structure includes: a substrate 100, an auxiliary module 200, an image sensing module 300, and a connector 400. The image sensing module 300, the auxiliary module 200 and the connector 400 are integrated by the substrate 100 to form a highly integrated package.

The substrate 100 includes a main surface, a back surface facing away from the main surface, and a plurality of side surfaces connecting the main surface and the back surface, and more specifically, the main surface and the back surface may be an upper surface and a lower surface of the substrate 100, respectively. The auxiliary module 200 is disposed on the lower surface of the substrate 100; the image sensing module 300 is disposed on the upper surface of the substrate 100 and is located in the main body portion of the substrate 100.

The connector 400 is used for electrically connecting the chip package structure with an external unit, and may be specifically disposed on the upper surface or the lower surface of the substrate 100, for example, in an embodiment, the connector 400 may be disposed on the upper surface of the substrate 100 and located at an edge portion of the substrate 100, as shown in fig. 1; alternatively, in other embodiments, the connector 400 may be disposed at an edge portion of the lower surface of the substrate 100. Alternatively, the connector 400 may be attached to one surface of the substrate 100. That is, in the embodiment of the present disclosure, the installation manner and the installation position of the connector 400 are not limited to the structure of fig. 1; in addition, the specification and the wire-outgoing manner of the connector 400 may be determined according to actual needs, and the embodiment of the present disclosure is not limited thereto.

In the embodiment of the present disclosure, the substrate 100 may be a PCB substrate, a silicon substrate with Through Silicon Vias (TSVs), a ceramic substrate, or an organic material substrate, and the upper surface and the lower surface of the substrate may be used for chip packaging at the same time. For example, in the embodiment shown in fig. 1, the image sensing module 300 and the connector 400 are packaged on the upper surface of the substrate 100, and the auxiliary module 200 is packaged on the lower surface of the substrate 100. Meanwhile, the substrate 100 may further include a functional circuit (or an auxiliary circuit) and an associated connection line required for the operation of the chip package structure; in addition, a plurality of electrical connection points for electrically connecting the auxiliary module 200, the image sensing module 300, the connector 400, and the like in a normal soldering manner, a flip chip bonding manner, a tape automated bonding manner, a metal wire bonding manner, or the like are previously formed on the surface of the substrate 100. The electrical connection points may also be connected with connection lines inside the substrate 100 to realize the overall electrical interconnection of the chip package structure.

The image sensing module 300 may be embodied as an optical fingerprint detection module, and may include an image sensing chip 301 and a lens module 302. The image sensor chip 301 may be a CMOS Image Sensor (CIS) chip, which is disposed on the upper surface of the substrate 100 and located on the main body portion of the substrate 100, for example, the image sensor chip 301 may be attached and fixed on the upper surface of the substrate 100 by an adhesive 502.

Moreover, the image sensor chip 301 includes an optical sensor array located in a middle region thereof and a pad 602 disposed at an edge. The optical sensing array is mainly used for detecting a target light signal passing through the lens module 302 to implement optical imaging, and in a specific embodiment, the target light signal may be fingerprint detection light formed by reflection of an excitation light source on a finger, the fingerprint detection light is transmitted to the optical sensing array of the image sensing chip 301 through the lens module 302, and the optical sensing array may detect the fingerprint detection light to implement optical fingerprint imaging. The bonding pads 602 may be connected to electrical connection points on the upper surface of the substrate 100 through metal wires 702, so as to electrically interconnect the optical sensing chip 301 and the substrate 100.

The lens module 302 is disposed above the image sensing chip 301, and is configured to converge or guide a target light signal to the image sensing chip 301; for example, the lens module 302 may be fixed on the surface of the image sensor chip 301 by an adhesive 503. In one embodiment, as shown in fig. 1, the lens module 302 may specifically include a lens barrel 303, an optical lens 304, and an optical filter 305; the optical lens 304 and the optical filter 305 are housed inside the lens barrel 303, and the optical filter 305 is located between the optical lens 304 and the image sensor chip 301. The optical lens 304 is mainly used for converging or guiding the optical path of the target optical signal, and the optical filter 305 may be an infrared filter, and is mainly used for isolating infrared interference light or other interference light of an external environment, so as to avoid interference of the interference light on the optical imaging of the image sensing chip 301.

In the embodiment shown in fig. 1, the bottom of the lens barrel 303 may be attached to the periphery of the optical sensing array of the image sensor chip 301 by an adhesive 503, and the bonding pad 602 is located at the outer side of the lens barrel 303 and facilitates the wire bonding of the metal wire 702.

The auxiliary module 200 includes an optical auxiliary chip 201, a capacitor 202, and a molding compound 203. The optical sub-chips 201 may be one or more, and may be sub-chips for assisting the image sensing module 300 in performing optical fingerprint detection or other types of optical detection. The optical sub-chip 201 may be disposed on the lower surface of the substrate 100, for example, the optical sub-chip 201 may be attached and fixed on the lower surface of the substrate 100 by the adhesive 501, and the main surface of the optical sub-chip 201 faces away from the lower surface of the substrate 100 after the optical sub-chip 201 is attached. The edge region of the main surface of the optical auxiliary chip 201 is further provided with a pad 601, the pad 601 is connected to an electrical connection point on the lower surface of the substrate 100 through a metal wire 701, and the electrical interconnection between the optical auxiliary chip 201 and the connection line of the substrate 100 is realized through the metal wire 701.

One or more capacitors 202 may be provided, and the specific number may be determined according to actual circuit design requirements, and the capacitors are disposed on the lower surface of the substrate 100 and located at the edge portion of the substrate 100, for example, the capacitors 202 may be soldered and fixed on the lower surface of the substrate 100 by a solder 801 in a Surface Mount Technology (SMT) manner. The solder 801 may be used as an electrical connection medium to connect the capacitor 202 to the electrical connection point on the lower surface of the substrate 100.

The molding compound 203 covers the optical auxiliary chip 201 and the capacitor 202, so as to seal the optical auxiliary chip 201 and the capacitor 202 on the lower surface of the substrate 100, and protect the optical auxiliary chip 201 and the capacitor 202. The molding compound 203 not only can seal the components (including the optical auxiliary chip 201, the capacitor 202, the metal wire 701, and the like) on the lower surface of the substrate 100, but also provides a high degree of flatness for the subsequent processes, wherein the molding compound 203 may be an epoxy resin material or an organic insulating material, and the like.

The connector 400 is mainly used for electrically connecting the chip package structure with an external unit (such as a control unit, a processing unit, or other electrical components of an electronic device) to realize a communication function between the image sensing module 300 and the external unit, so as to realize fingerprint authentication or other functions. In the embodiment shown in fig. 1, the connector 400 is disposed on the upper surface of the substrate 100 and located at the edge of the substrate 100, for example, the connector 400 may be soldered and fixed on the substrate 100 by a solder 802 in a surface mount manner, wherein the solder 802 is connected to electrical connection points on the upper surface of the substrate 100 and can be used as an electrical connection medium to electrically interconnect the connector 400 and the substrate 100.

In the embodiment of the present disclosure, the

adhesives

501, 502, 503 may be adhesive substances such as glue or adhesive film, which are respectively used to attach the optical fingerprint auxiliary chip 201 and the image sensing chip 301 to corresponding surfaces of the substrate 100, and attach the lens barrel 303 to the image sensing chip 301 or an upper surface of the substrate 100.

In the embodiment shown in fig. 1, the bonding pad 601 of the optical accessory chip 201 is connected to the electrical connection point on the lower surface of the substrate 100 through the metal wire 701 by a wire bonding process, so as to electrically connect the optical accessory chip 201 and the substrate 100. Similarly, the bonding pad 602 of the image sensor chip 301 is connected to the electrical connection point on the upper surface of the substrate 100 through the metal wire 702 by a wire bonding process, so as to electrically connect the image sensor chip 301 and the substrate 100. The

metal lines

701 and 702 are electrical connection media of the chip package structure, and specifically may be metals with good conductivity, such as aluminum, copper, nickel, silver, and gold.

Here, the

bonding pads

601 and 602 may be understood as pins for connecting the optical sub-chip 201 and the image sensing chip 301 to the substrate 100. It should be noted that, one surface of the optical sub-chip 201 and the image sensing chip 301 may be prepared with the

bonding pads

601 and 602 in advance, as shown in fig. 1, and the other surface of the optical sub-chip 201 and the image sensing chip 301 is used to be attached to the lower surface or the upper surface of the substrate 100. In the disclosed embodiment, as described above, the capacitor 202 may be attached to the edge portion of the lower surface of the substrate 100 by soldering 801 through an SMT process, and connected to the electrical connection point of the substrate 100 through the soldering 801, wherein the capacitor 202 is electrically connected to the substrate 100 at this time.

On the other hand, the image sensing module 300 may be provided with one or more image sensing chips 301 according to actual requirements, and correspondingly, the image sensing module 300 may include one or more lens modules 302 to cooperate with the one or more image sensing chips 301 to perform optical imaging. Alternatively, when the image sensing module 300 employs a plurality of image sensing chips 301, at least some of the image sensing chips 301 may share one lens module 302. In the embodiment shown in fig. 1, the image sensing chip 301 is directly attached to the upper surface of the substrate 100, alternatively, the image sensing chip 301 may also be embedded in the upper surface of the substrate 100 by using an embedded process, specifically, a groove may be formed in a region of the upper surface of the substrate 100 where the image sensing chip 301 is disposed, and at least a portion of the image sensing chip 301 may be accommodated in the groove and attached to and fixed with the bottom surface of the groove, so as to further improve the integration level of the chip package structure.

In the embodiment shown in fig. 1, the lens module 302 may be attached to the upper surface of the image sensor chip 301 by an adhesive 503; in other alternative embodiments, the lens module 302 may also be attached to the upper surface of the substrate 100, that is, the lens barrel 303 spans over the periphery of the image sensing chip 301 and is attached and fixed to the substrate surface outside the image sensing chip 301. The application is not particularly limited to the attaching manner of the lens module 302, as long as the optical lens 304 and the optical filter 305 can be aligned with the optical sensing array of the image sensing chip 301. The optical lens 304 and the optical filter 305 may be separately disposed, as shown in fig. 1, the optical filter 305 is located below the optical lens 304, the optical lens 304 and the optical filter 305 may be integrated together, or the optical filter 305 may be attached to the surface of the optical sensing array of the image sensor chip 301.

In an embodiment, the lens module 302 of the image sensing module 300 may be provided with one or more optical lenses 304 according to actual requirements, and the optical lenses 304 may be lenses, such as aspheric lenses. In other alternative embodiments, the optical lens 304 may also be replaced by an optical path collimator or other optical path modulator, and the optical lens 304 and the optical filter 305 may also be directly attached to or integrated into the surface or the interior of the image sensing module 301, so that the lens barrel 303 does not need to be additionally disposed.

Based on the chip packaging structure shown in fig. 1, the embodiment of the present disclosure further provides a chip packaging method, which may be used for manufacturing the chip packaging structure shown in fig. 1. Referring to fig. 2, which is a flowchart of a chip packaging method according to an embodiment of the disclosure, in order to better understand the chip packaging method provided by the disclosure, the chip packaging method shown in fig. 2 is described below with reference to schematic diagrams of a manufacturing process of the chip packaging structure described in fig. 3 to 9. Fig. 3 is a schematic view of a substrate used in the chip packaging method; FIG. 4 is a schematic view of an optical sub-chip disposed on a lower surface of a substrate; FIG. 5 is a schematic view of the capacitor attached to the lower surface of the substrate; FIG. 6 is a schematic view of the optical auxiliary chip and the capacitor being molded on the lower surface of the substrate by using a molding compound; FIG. 7 is a schematic view of an image sensor chip disposed on an upper surface of a substrate; FIG. 8 is a schematic view of a lens module disposed above an image sensor chip; fig. 9 is a schematic view of attaching a connector to a substrate.

Specifically, the chip packaging method mainly comprises the following steps:

step S101, providing a substrate for chip packaging, processing a required circuit on the substrate, and designing the required circuit to be in a required size;

referring to fig. 3, the substrate 100 provided in step S101 may be a PCB substrate, a silicon substrate with TSVs, a ceramic substrate, or an organic material substrate, and in step S101, the substrate 100 may be first ground to a required size including a length, a width, a thickness, and the like, and then a required functional circuit (or an auxiliary circuit) and a connection circuit are manufactured through an etching process, and meanwhile, various electrical connection points are manufactured in a predetermined region of the surface of the substrate 100 to prepare for a subsequent typical connection between the substrate 100 and a chip or a module to be packaged.

Step S102, attaching an optical auxiliary chip to the lower surface of the substrate;

referring to fig. 4, in step S102, one or more optical sub-chips 201 may be attached to the lower surface of the substrate 100 by an adhesive 501 in a flip-chip package manner, and a wire bonding process is used to electrically connect the pads 601 of the optical sub-chips 201 and the electrical connection points on the lower surface of the substrate 100 through metal wires 701.

The adhesive 501 may be a material having adhesive properties such as glue or an adhesive film, as long as the optical sub chip 201 can be attached to the lower surface of the substrate 100. The bonding pads 601 of the optical sub-chip 201 can be understood as pins for connecting the optical sub-chip 201 to the substrate 100. It should be noted that, before the optical sub-chip 201 is bonded to the substrate 100, the main surface (non-bonding surface) of the optical sub-chip 201 is prepared with the pad 601 in advance, so in step S102, after the optical sub-chip 201 is bonded to the lower surface of the substrate 100, the pad 601 of the optical sub-chip 201 can be directly connected to the electrical connection point of the lower surface of the substrate 100 through the metal wire 701 by using a metal wire bonding process.

Step S103, welding a capacitor to the edge area of the lower surface of the substrate;

referring to fig. 5, in step S103, specifically, one or more capacitors 202 may be soldered to the edge area of the lower surface of the substrate 100 by solder 801 through an SMT process, where the solder 801 is used as an electrical connection medium in addition to the soldering and fixing of the capacitors 202 and the substrate 100, so as to electrically connect the capacitors 202 to the electrical connection points on the lower surface of the substrate 100.

It should be understood that, in the actual process, the steps S102 and S103 are not strictly sequential, that is, the capacitor 202 may be soldered to the edge region of the lower surface of the substrate 100, and then the optical sub-chip 201 is bonded and wire-bonded.

Step S104, sealing the optical auxiliary chip and the capacitor on the lower surface of the substrate through a plastic package material;

specifically, referring to fig. 6, after the optical auxiliary chip 201 and the capacitor 202 are fixed on the substrate 100, in step S104, a molding compound 203 may be used to seal the optical auxiliary chip 201 and the capacitor 202, together with the pad 601, the metal wire 701, the solder 801, and the like, on the lower surface of the substrate 100 by using a molding process. The molding compound 203 may be an epoxy resin material or an organic insulating material, and after the step S104, not only the lower surface of the substrate 100 is sealed, but also a higher flatness is provided for the subsequent processes.

Step S105, attaching an image sensing chip to the upper surface of the substrate;

referring to fig. 7, in step S105, the image sensor chip 301 may be attached to the main body portion of the upper surface of the substrate 100 by using an adhesive 502, and the adhesive 502 may also be a material having adhesiveness, such as glue or an adhesive film; then, a wire bonding process is used to electrically connect the bonding pad 602 of the image sensor chip 301 to the electrical connection point on the upper surface of the substrate 100 through the metal wire 702.

The image sensor chip 301 may be specifically a CIS chip having an optical sensor array, wherein the bonding pad 602 may be fabricated in advance on an edge region of the surface of the image sensor chip 301, and therefore, in step S105, after the image sensor chip 301 is attached to the upper surface of the substrate 100, the bonding pad 602 of the optical image sensor chip 301 may be directly connected to the electrical connection point on the upper surface of the substrate 100 through the metal wire 702 by using a metal wire bonding process.

Step S106, arranging a lens module above the image sensing chip;

referring to fig. 8, in step S106, an optical lens 304 and a filter 305 are disposed inside a lens barrel 303 to form a lens module, wherein the filter 305 is disposed below the optical lens 304, and the optical lens 304 may include at least one aspheric lens. Next, the lens module is attached to the surface of the image sensing chip 301 by an adhesive 503; specifically, the bottom of the lens barrel 303 of the lens module may be attached to the outer peripheral surface of the optical sensor array of the image sensor chip 301, and the attachment position of the lens module needs to ensure that the optical lens 304 and the optical filter 305 are arranged in optical path alignment with the optical sensor array of the image sensor chip 301.

Step S107, welding a connector to the substrate for electrically connecting the chip packaging structure with an external unit;

specifically, referring to fig. 9, the connector 400 is mainly used for providing a connection port or a connection medium for electrical connection between the chip package structure and an external unit, for example, the connector 400 may be used for realizing communication between the image sensing chip 301 and the external unit, and may be soldered to an edge portion of the upper surface of the substrate 100 by using an SMT process and a solder 802, where the solder 802 is used as an electrical connection medium in addition to performing soldering and fixing of the connector 400 and the substrate 100, so as to realize electrical connection between the connector 400 and an electrical connection point on the upper surface of the substrate 100.

In the chip packaging method provided by the above embodiment of the present disclosure, the chip packaging structure shown in fig. 1 can be manufactured through the above steps.

It should be understood that although the above-mentioned embodiment uses the image sensing chip 301 and the lens module of the image sensing module to be bonded to the substrate 100 before the connector 400 is soldered, in alternative embodiments, the connector 400 may be bonded to the substrate 100 before the image sensing chip 301 and the lens module are bonded, i.e. step S107 may be performed before step S105.

In addition, as can be understood by those skilled in the art, in practice, most steps of the chip packaging method provided in the embodiment are not in strict sequence, for example, the connector 400 and/or the image sensing module on the upper surface of the substrate 100 may be attached and mounted first, and then the capacitor 202 and the optical auxiliary chip 201 on the lower surface of the substrate 100 are attached.

On the other hand, although the step S107 of the chip packaging method provided in the above embodiment is to mount the connector 400 on the upper surface of the substrate 100 on which the image sensing chip 301 is located through a surface mounting process, in another embodiment, the connector 400 and the capacitor 202 may also be mounted on the lower surface of the substrate 100 on which the optical auxiliary chip 201 is located through a surface mounting process or other processes. Alternatively, the connector 400 may be attached to one side of the substrate 100 by a single mounting step, in which case, the side of the substrate 100 needs to be pre-fabricated with a corresponding connection end for attaching the connector 400.

Please refer to fig. 10, which is a schematic diagram of a chip package structure according to another embodiment of the disclosure. The chip package structure shown in fig. 10 is similar to the chip package structure shown in fig. 1, and the main difference is that a silicon substrate having Through Silicon Vias (TSVs) is used as the substrate 100 of the chip package structure shown in fig. 10, instead of the

metal lines

701 and 702 of the chip package structure shown in fig. 1.

In the chip package structure shown in fig. 10, the pads of the image sensor chip 301 may be disposed at the bottom, i.e. the surface of the image sensor chip that is attached to the upper surface of the substrate 100, and are soldered to the upper surface of the substrate 100 by a solder 502, and at least a portion of the pads of the image sensor chip 301 may be connected to the through-silicon-vias of the substrate 100, and further electrically connected to the connection lines of the substrate 100 or other electrical components (such as the optical auxiliary chip 201 or the connector 400) of the chip package structure through the through-silicon-vias. Since the image sensor chip 301 and the connector 400 are fixed to the upper surface of the substrate 100 by soldering, the image sensor chip 301 and the connector 400 can be soldered to the upper surface of the substrate 100 and electrically connected by the same connecting process (such as a surface mount process), thereby reducing the number of process steps.

Similarly, the bonding pad of the optical sub-chip 201 may also be disposed on the bonding surface of the substrate 100, and may be bonded to the lower surface of the substrate 100 by the solder 501 through a flip-chip bonding process. Also, at least a portion of the pads of the optical sub-chip 201 may be connected to the through-silicon vias of the substrate 100, and further electrically connected to the connection lines of the substrate 100 or other electrical components of the chip package structure (such as the image sensor chip 301, the connector 400, the capacitor 201, etc.) through the through-silicon vias. Since the optical auxiliary chip 201 and the capacitor 202 are soldered and electrically interconnected by solder, the optical auxiliary chip 201 and the capacitor 202 can be soldered to the lower surface of the substrate 100 and electrically connected by the same flip-chip soldering process, thereby reducing the number of process steps.

Based on the chip packaging structure shown in fig. 10, the present disclosure further provides another chip packaging method, and fig. 11 is a flowchart of the chip packaging method according to an embodiment of the present disclosure. The chip packaging method can be used for preparing the chip packaging structure shown in fig. 10. The chip packaging method specifically comprises the following steps:

s201, processing a required circuit on a substrate and designing the circuit to be in a required size;

s202, attaching an optical auxiliary chip and a capacitor to the lower surface of the substrate by adopting an SMT (surface mount technology) process, and connecting the optical auxiliary chip and the capacitor to the electric connection points on the lower surface of the substrate through soldering tin, wherein at least part of bonding pads of the optical auxiliary chip are connected to the through silicon vias of the substrate through the soldering tin;

s203, sealing the optical auxiliary chip and the capacitor on the lower surface of the substrate through a plastic package material by adopting a plastic package process;

s204, attaching an image sensing chip and a connector to the upper surface of the substrate by adopting an SMT (surface mount technology) process, and connecting the image sensing chip and the connector to the electric connection points on the upper surface of the substrate through soldering tin, wherein at least part of bonding pads of the image sensing chip are connected to the through silicon vias of the substrate through the soldering tin;

in step S204, the image sensor chip and the image sensor chip can be electrically connected through the through-silicon via of the substrate, that is, at least one pad of the image sensor chip on the upper surface of the substrate is electrically connected through the through-silicon via and the optical auxiliary chip on the lower surface of the substrate.

S205, attaching a lens module to the upper side of the image sensing chip through an adhesive, wherein an optical lens of the lens module is aligned with the image sensing chip.

In the chip packaging method shown in fig. 11, the image sensor chip and the connector can be connected to the upper surface of the substrate by the same surface mount process; in other alternative embodiments, the connector and the optical sub-chip may be connected to the lower surface of the substrate by the same surface mount process, thereby reducing the number of process steps. Alternatively, the connector may be attached to one of the sides of the substrate using a single attachment step.

The chip packaging structure provided by each of the above embodiments of the present disclosure may be applicable to chip packaging of an optical fingerprint detection device, and is particularly applicable to an electronic device having an optical fingerprint detection device under a screen. Specifically, based on the chip package structure provided in the above embodiment, an embodiment of the present disclosure further provides an electronic device, where the electronic device includes a display screen and an optical fingerprint detection device disposed below the display screen, where the optical fingerprint detection device may include the chip package structure described in the above embodiment. More specifically, the display screen may be an OLED display screen or an LCD display screen, and when the OLED display screen is adopted, the optical fingerprint detection device may utilize a part of display pixels of the OLED display screen as an excitation light source for optical fingerprint detection; when an LCD display screen is adopted, the optical fingerprint detection device can be provided with an additional light source as an excitation light source for optical fingerprint detection.

While this disclosure contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document can also be implemented in combination in a single embodiment, in the context of separate embodiments. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the various individual system components in the embodiments described in this patent document are not to be construed as requiring such separation in all embodiments.

It will be understood by those of ordinary skill in the art that the embodiments described above are specific embodiments for carrying out the present application and that various changes in form and details may be made therein without departing from the scope of the present application in practice.

Claims

1. A chip packaging structure is characterized by comprising a substrate, an image sensing module and an auxiliary module, wherein the image sensing module and the auxiliary module are integrally packaged by utilizing the substrate;

the image sensing module is an optical fingerprint detection module and comprises an image sensing chip, and the image sensing chip is packaged on the first surface of the substrate;

the auxiliary module comprises at least one optical auxiliary chip, and the at least one optical auxiliary chip is packaged on the second surface of the substrate and is electrically connected with the image sensing chip through the substrate.

2. The chip package structure according to claim 1, further comprising a connector connected to the substrate for electrically connecting the chip package structure with an external unit.

3. The chip package structure according to claim 2, wherein the connector is attached to the first surface or the second surface of the substrate.

4. The chip package structure according to claim 3, wherein the image sensor chip and the at least one optical sub-chip are disposed on the main portion of the first surface of the substrate and the main portion of the second surface of the substrate, respectively, and the connector is connected to an edge portion of the first surface of the substrate or the second surface of the substrate.

5. The chip package structure according to claim 2, wherein the substrate further comprises a plurality of sides, and the connector is disposed on one of the sides of the substrate.

6. The chip package structure according to claim 1, wherein the image sensor chip is attached to the first surface of the substrate by a first adhesive, and the pads on the surface of the image sensor chip are connected to the electrical connection points on the first surface of the substrate by first metal wires.

7. The chip package structure according to claim 6, wherein the optical sub-chip is attached to the second surface of the substrate by a second adhesive, and the pads on the surface of the optical sub-chip are connected to the electrical connection points on the second surface of the substrate by second metal wires, and the optical sub-chip is electrically connected to the image sensor chip by the connection wires of the substrate.

8. The chip package structure according to claim 1, wherein the substrate is a silicon substrate having through-silicon-vias, the image sensor chip is connected to the first surface of the silicon substrate through pads on a bottom surface thereof, and at least some of the pads of the image sensor chip are electrically connected to the through-silicon-vias of the silicon substrate.

9. The chip package structure according to claim 8, wherein the optical sub-chip is flip-chip bonded to the second surface of the silicon substrate via a bonding pad on a bottom surface thereof, and at least a portion of the bonding pad of the optical sub-chip is electrically connected to the image sensor chip via the through-silicon via.

10. The chip package structure according to claim 1, wherein the image sensor module further comprises a lens module disposed above the image sensor chip for converging or guiding the target light signal to the image sensor chip.

11. The chip package structure according to claim 10, wherein the lens module includes a lens barrel and an optical lens accommodated in the lens barrel, the image sensor chip includes an optical sensor array, and the optical lens and the optical sensor array are arranged in optical path alignment.

12. The chip package structure according to claim 11, wherein the target light signal is fingerprint detection light reflected from a surface of a finger, wherein the fingerprint detection light is converged or guided to the image sensor chip by the optical lens, and the image sensor chip is configured to detect the fingerprint detection light for optical fingerprint imaging.

13. The chip package structure according to claim 11, wherein the lens module further includes an optical filter, the optical filter is received in the lens barrel and located between the optical lens and the image sensor chip, and the optical filter is used for isolating external interference light to prevent the external interference light from entering the optical sensor array.

14. The chip package structure according to any one of claims 1 to 13, wherein the auxiliary module further comprises at least one capacitor connected to an edge region of the second surface of the substrate by solder.

15. The chip package structure according to claim 14, wherein the auxiliary module further comprises a molding compound, the molding compound sealing the optical auxiliary chip and the at least one capacitor to the second surface of the substrate and making the surface of the chip package structure flat.

16. An electronic device comprising a display screen and an optical fingerprint detection device located below the display screen, the optical fingerprint detection device comprising the chip packaging structure according to any one of claims 1 to 15.