CN200976345Y - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN200976345Y CN200976345Y CN200620147480.5U CN200620147480U CN200976345Y CN 200976345 Y CN200976345 Y CN 200976345Y CN 200620147480 U CN200620147480 U CN 200620147480U CN 200976345 Y CN200976345 Y CN 200976345Y
- Authority
- CN
- China
- Prior art keywords
- chip
- carrier
- heat
- heat radiation
- packaging structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model relates to a chip package structure, comprising a carrier, a chip at least, a heat sink and a heat-conducting medium. The chip is arranged on the carrier and the two are electrically connected. The radiator is arranged on the carrier, wherein the carrier and the heat sink jointly form a confined space which is provided with the chip and filled with the heat-conducting medium. In addition, a manufacturing method of the chip package structure is also proposed.
Description
Technical field
The utility model relates to a kind of chip-packaging structure, and relates in particular to the chip-packaging structure that a kind of radiating efficiency promotes to some extent.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the making (IC process) of the design of integrated circuit (IC design), integrated circuit and the encapsulation (IC package) of integrated circuit.
In the making of integrated circuit, chip (chip) is to finish via wafer (wafer) making, formation integrated circuit and cut crystal steps such as (wafer sawing).Wafer has an active face (activesurface), the surface with active element (active element) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active face of wafer more disposed a plurality of weld pads (bonding pad), can outwards be electrically connected on a carrier (carrier) via these weld pads so that finally cut formed chip by wafer.Carrier for example is a lead frame (leadframe) or a base plate for packaging (packagesubstrate).Chip can wire-bonded (wire bonding) or the mode of flip-chip bond (flip chipbonding) be connected on the carrier, make these weld pads of chip can be electrically connected on the contact of carrier, to constitute a chip-packaging structure.
With regard to flip-chip bond technology (flip chip bonding technology), usually on the active face of wafer, form after these weld pads, can on each weld pad, make a projection (bump), to be electrically connected the usefulness of outer enclosure substrate as chip.Since these projections usually with the face arranged in array mode on the active face of chip, make the flip-chip bond technology be suitable for being used in the chip-packaging structure of high number of contacts and high contactor density, for example be applied to the flip-chip/spherical grid array type encapsulation (flip chip/ball grid array package) in the semiconductor packages industry at large.In addition, compared to the wire-bonded technology,, make the flip-chip bond technology can promote the electrical property efficiency of chip-packaging structure (electrical performance) because these projections can provide transmission path short between chip and the carrier.
In existing flip-chip bond technology; with chip via a plurality of projections after being electrically connected and being fixed on the substrate; in order to strengthen the radiating effect of chip; usually a radiator (heat spreader) with groove (cavity) can be attached at the back side of chip by thermal paste (thermal adhesive), make chip be positioned to be disposed at the groove of the radiator on the substrate.When existing chip-packaging structure operates, the heat that chip produced is mainly transmitted (transfer) to external environment by the thermal paste and the radiator of chip back, so radiator its temperature of part direct and that chip back heat couples is higher, the temperature of radiator other parts is then lower.In other words, the radiating efficiency of the radiator of existing chip-packaging structure is relatively poor.Yet under highly energy-consuming when operating along with chip and the high-frequency designer trends, the existing radiating efficiency that is attached at the radiator on the chip has not applied demand, and the radiating efficiency that therefore improves existing chip-packaging structure is that its necessity is arranged.
The utility model content
The purpose of this utility model provides a kind of chip-packaging structure, and its radiating efficiency promotes to some extent.
For reaching above-mentioned or other purpose, the utility model proposes a kind of chip-packaging structure, it comprise a carrier, at least one chip, a radiator and a heat-conducting medium (thermal interface material, TIM).Chip configuration is on carrier and be electrically connected to carrier.Heat sink arrangements is on carrier, and wherein radiator and carrier are common forms a confined space (closed space), and chip is positioned at confined space.In addition, heat-conducting medium fills up confined space.
For reaching above-mentioned or other purpose, the utility model proposes a kind of chip-packaging structure, it comprises a carrier, at least one chip, a radiator and a heat-conducting medium.Chip configuration is on carrier and be electrically connected to carrier.Heat sink arrangements is on carrier, and wherein radiator and carrier are common forms a confined space, and chip is positioned at confined space.In addition, heat-conducting medium is positioned at confined space, and wherein heat-conducting medium contacts with the inner surface of radiator.
For above-mentioned and other purpose, feature and advantage of the present utility model can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A illustrates the generalized section of a kind of chip-packaging structure of the utility model first embodiment;
Figure 1B illustrates the generalized section of the another kind of chip-packaging structure of the utility model first embodiment;
Fig. 2 A to Fig. 2 G illustrates the schematic flow sheet of manufacture method of the chip-packaging structure of Figure 1A;
Fig. 3 illustrates the generalized section of a kind of chip-packaging structure of the utility model second embodiment.
Description of reference numerals
10: confined space 20: accommodation space
100,100 ', 200: chip-packaging structure 110,210: carrier
112: loading end 120,220: chip
130,130 ': radiator 132: the heat radiation plate body
132a: the inner surface 134 of heat radiation plate body: heat radiation ring body
134a: the inner surface 136 of heat radiation ring body: groove
138: the inner surface 139 of radiator: fin
140: heat-conducting medium 150: conductive projection
160: primer layer H: highly
Embodiment
Please refer to Figure 1A, it illustrates the generalized section of a kind of chip-packaging structure of the utility model first embodiment.The chip-packaging structure 100 of first embodiment comprises a carrier 110, at least one chip 120, a radiator 130 and a heat-conducting medium 140.Chip 120 is disposed on the carrier 110 and is electrically connected to carrier 110.Radiator 130 is disposed on the carrier 110, and wherein radiator 130 forms confined spaces 10 jointly with carrier 110, and chip 120 is positioned at confined space 10.In addition, heat-conducting medium 140 fills up confined space 10.
It should be noted that when chip-packaging structure 100 runnings, because heat-conducting medium 140 fills up confined space 10, so the heat that chip 120 is produced can be passed to radiator 130 in the mode of conducting by heat-conducting medium 140.Deceive arrow as can be known by the thick of Fig. 1, the heat that the chip 120 of present embodiment is produced not only can also can be passed to radiator 130 in the mode of conducting by the side of chip 120 by the back side of chip 120.Therefore, compare with existing, the temperature of the radiator 130 of present embodiment is (uniform) comparatively evenly, and in other words, the radiating efficiency of the chip-packaging structure 100 of present embodiment is preferred.
Heat-conducting medium 140 can be heat conduction compound (thermally conductive compound) or heat-conducting elastomer (thermally conductive elastomer).Particularly, heat-conducting medium 140 can be tin cream (solder paste), thermal grease (thermal grease) or is interpolation silicon dioxide or silver-colored epoxy resin (epoxy resin).Wherein heat-conducting medium 140 also can comprise metal materials such as tin or lead.This mandatory declaration be, heat-conducting medium 140 can be according to designer's demand changes to some extent, first embodiment is just in order to for example and non-limiting the utility model.
In detail, the radiator 130 of first embodiment comprises a heat radiation plate body (thermal plate) 132 and one heat radiation ring body (thermal ring) 134.Heat radiation ring body 134 is disposed on the heat radiation plate body 132, and heat radiation ring body 134 and the heat radiation plate body 132 common grooves 136 that form, and heat radiation ring body 134 is between heat radiation plate body 132 and carrier 110.As shown in Figure 1, in first embodiment, confined space 10 can be formed with 110 of carriers jointly by heat radiation plate body 132, heat radiation ring body 134, and the heat-conducting medium 140 that fills up confined space 10 contacts with the inner surface 138 of radiator 130.In other words, the heat-conducting medium 140 of first embodiment contacts with the inwall of the groove 136 of radiator 130.
In this mandatory declaration be, the heat radiation plate body 132 of first embodiment can be distinguished moulding in advance with heat radiation ring body 134, reprocessing is afterwards engaged and is formed (seeing aftermentioned for details), yet heat radiation plate body 132 also can one-body molded according to design requirement (integrally formed) with the ring body 134 that dispels the heat.In addition, please refer to Figure 1B, it illustrates the generalized section of the another kind of chip-packaging structure of the utility model first embodiment.The radiator 130 ' of chip-packaging structure 100 ' more comprises a plurality of fins (fin) 139, and it is disposed on the side with respect to heat radiation ring body 134 of heat radiation plate body 132.In other words, these fins 139 by heat radiation plate body 132 with towards extending away from the direction of chip 120.The function of these fins 139 is to increase the area that radiator 130 ' and external environment are carried out heat exchange, and then promotes the radiating efficiency of radiator 130 '.
Refer again to Figure 1A, the chip-packaging structure 100 of first embodiment more comprises a plurality of conductive projections (conductive bump) 150 and one primer layers (underfill layer) 160, and carrier 110 can be circuit board.These conductive projections 150 are disposed between chip 120 and the carrier 110, and primer layer 160 coats these conductive projections 150.Primer layer 160 is in order to protect these conductive projections 150; and produce when hot the phenomenon of do not match (mismatch) of the thermal strain (thermal strain) that is produced between carrier 110 that primer layer 160 available buffers are heated and the chip 120 that is heated when chip-packaging structure 100 running.
Below elaborate for the manufacture method of the chip-packaging structure 100 of first embodiment.Fig. 2 A to Fig. 2 G illustrates the schematic flow sheet of manufacture method of the chip-packaging structure of Figure 1A, and the manufacture method of the chip-packaging structure 100 of first embodiment comprises the following steps.At first, please refer to Fig. 2 A, a carrier 110 is provided.Then, please refer to Fig. 2 B, at least one chip 120 is disposed on the carrier 110.Then, be electrically connected chip 120 and carrier 110.
In first embodiment, above-mentioned these steps that are disposed at chip 120 on the carrier 110 and are electrically connected to carrier 110 are finished by the flip-chip bond technology, and it comprises following substep.At first, for example on chip 110, form a plurality of conductive projections 150 in the mode of electroplating.Afterwards, chip 120 is disposed on the carrier 110, and these conductive projections 150 of reflow (reflow), make these conductive projections 150 be electrically connected between chip 120 and the carrier 110.At last, form a primer layer 160, to coat these conductive projections 150.Primer layer 160 is normally by filling a primer (underfill) and being toasted and finish between chip 120 and carrier 110.
Afterwards, please refer to Fig. 2 C, for example a heat radiation ring body 134 is disposed on the carrier 110, make heat radiation ring body 134 around chip 120 in the mode of sticking together.Afterwards, please refer to Fig. 2 D, a heat-conducting medium 140 is filled up the accommodation space (containingspace) 20 that centered on of heat radiation ring body 134 on carrier 110, make heat-conducting medium 140 coating chips 120.
Then, please refer to Fig. 2 E, in first embodiment, can after above-mentioned step of heat-conducting medium 140 being filled up accommodation space 20, heat-conducting medium 140 gas inside be detached.If heat-conducting medium 140 is solid-state, mode that then can vacuum drawn (vacuum extraction) detaches heat-conducting medium 140 gas inside; If heat-conducting medium 140 be a liquid state, then can vacuum drawn or heating or mode that both walk abreast heat-conducting medium 140 gas inside are detached.In this mandatory declaration is that after heat-conducting medium 140 gas inside were detached, the height H of heat-conducting medium 140 can descend usually.
Then, please refer to Fig. 2 F, insert heat-conducting medium 140 again, to fill up accommodation space 20 and coating chip 120.Then, please refer to Fig. 2 G, for example a heat radiation plate body 132 is disposed on the heat radiation ring body 134 by the mode of sticking together or welding, make heat radiation plate body 132 cover chip 120, and heat-conducting medium 140 fill up by heat radiation plate body 132,110 confined spaces 10 that form jointly of heat radiation ring body 134 and carrier.Wherein, heat radiation plate body 132 and heat radiation ring body 134 constitute the radiator 130 of (compose) present embodiments.
Please refer to Figure 1A, in first embodiment, aforesaid confined space 10 is to be the boundary with the inner surface 132a of heat radiation plate body 132, the heat radiation inner surface 134a of ring body 134 and the loading end 112 of carrier 110.The inner surface 138 of radiator 130 be by the heat radiation plate body 132 inner surface 132a with the heat radiation ring body 134 inner surface 134a constituted.After heat-conducting medium 140 was inserted confined space 10, heat-conducting medium 140 meetings and inner surface 138 contacted with loading end 112.That is heat-conducting medium 140 covers the inner surface 132a of heat radiation plate body 132, the inner surface 134a of heat radiation ring body 134 and the loading end 112 of carrier 110.
Please refer to Fig. 3, it illustrates the generalized section of a kind of chip-packaging structure of the utility model second embodiment.The main difference part of the chip-packaging structure 200 of second embodiment and the chip-packaging structure 100 of first embodiment is that the chip-packaging structure 200 of second embodiment comprises a plurality of chips 220.These chips 220 are electrically connected mutually, and are disposed on the carrier 210 in the mode of piling up.In this mandatory declaration is that the quantity of these chips 220 can change according to designer's demand to some extent with the mode that is disposed on the carrier 210.Present embodiment is non-limiting the utility model in order to give an example just.
In sum, chip-packaging structure of the present utility model and manufacture method thereof have following advantage at least:
One, when chip-packaging structure of the present utility model operates, because heat-conducting medium fills up confined space, so the heat that chip produced can be passed to radiator in the mode of conducting by heat-conducting medium.Therefore, the heat that chip of the present utility model produced not only can also can be passed to radiator in the mode of conducting by the side of chip by the back side of chip.From the above, compare with existing, radiator internal temperature of the present utility model is comparatively even, that is the radiating efficiency of chip-packaging structure of the present utility model is preferred.
Two, since these steps of the manufacture method of chip-packaging structure of the present utility model can with existing process integration, therefore the manufacturing cost of the chip-packaging structure that promotes to some extent of radiating efficiency of the present utility model is comparatively cheap.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection range of the present utility model is as the criterion when looking the appending claims person of defining.
Claims (10)
1. chip-packaging structure is characterized in that comprising:
One carrier;
At least one chip is disposed on this carrier and is electrically connected to this carrier;
One radiator is disposed on this carrier, and wherein this radiator and this carrier are common forms a confined space, and this chip is positioned at this confined space; And
One heat-conducting medium fills up this confined space.
2. chip-packaging structure as claimed in claim 1 is characterized in that this radiator comprises:
One heat radiation plate body; And
One heat radiation ring body is disposed on this heat radiation plate body, and wherein should dispel the heat ring body and this heat radiation plate body form a groove jointly, and this heat dissipating ring body is positioned between this heat radiation plate body and this carrier.
3. chip-packaging structure as claimed in claim 2 is characterized in that this heat radiation plate body and this heat radiation ring body are formed in one.
4. chip-packaging structure as claimed in claim 2 is characterized in that this radiator more comprises a plurality of fins, and it is disposed on the side with respect to this heat radiation ring body of this heat radiation plate body.
5. chip-packaging structure as claimed in claim 1 is characterized in that more comprising:
A plurality of conductive projections are disposed between this chip and this carrier; And
One primer layer coats those conductive projections.
6. chip-packaging structure is characterized in that comprising:
One carrier;
At least one chip is disposed on this carrier and is electrically connected to this carrier;
One radiator is disposed on this carrier, and wherein this radiator and this carrier are common forms a confined space, and this chip is positioned at this confined space; And
One heat-conducting medium is positioned at this confined space, and wherein this heat-conducting medium contacts with the inner surface of this radiator.
7. chip-packaging structure as claimed in claim 6 is characterized in that this radiator comprises:
One heat radiation plate body; And
One heat radiation ring body is disposed on this heat radiation plate body, and wherein should dispel the heat ring body and this heat radiation plate body form a groove jointly, and this heat dissipating ring body is positioned between this heat radiation plate body and this carrier.
8. chip-packaging structure as claimed in claim 7 is characterized in that this heat radiation plate body and this heat radiation ring body are formed in one.
9. chip-packaging structure as claimed in claim 7 is characterized in that this radiator more comprises a plurality of fins, and it is disposed on the side with respect to this heat radiation ring body of this heat radiation plate body.
10. chip-packaging structure as claimed in claim 6 is characterized in that more comprising:
A plurality of conductive projections are disposed between this chip and this carrier; And
One primer layer coats those conductive projections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200620147480.5U CN200976345Y (en) | 2006-11-24 | 2006-11-24 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200620147480.5U CN200976345Y (en) | 2006-11-24 | 2006-11-24 | Chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200976345Y true CN200976345Y (en) | 2007-11-14 |
Family
ID=38902626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200620147480.5U Expired - Lifetime CN200976345Y (en) | 2006-11-24 | 2006-11-24 | Chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN200976345Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187371A (en) * | 2011-12-27 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor structure and manufacturing method thereof |
| CN108962876A (en) * | 2012-10-11 | 2018-12-07 | 台湾积体电路制造股份有限公司 | POP structure and forming method thereof |
| CN112885794A (en) * | 2021-01-15 | 2021-06-01 | 浪潮电子信息产业股份有限公司 | PCB (printed Circuit Board), POP (Point of Place) packaging heat dissipation structure and manufacturing method thereof |
-
2006
- 2006-11-24 CN CN200620147480.5U patent/CN200976345Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187371A (en) * | 2011-12-27 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor structure and manufacturing method thereof |
| CN108962876A (en) * | 2012-10-11 | 2018-12-07 | 台湾积体电路制造股份有限公司 | POP structure and forming method thereof |
| CN108962876B (en) * | 2012-10-11 | 2022-05-17 | 台湾积体电路制造股份有限公司 | POP structure and forming method thereof |
| CN112885794A (en) * | 2021-01-15 | 2021-06-01 | 浪潮电子信息产业股份有限公司 | PCB (printed Circuit Board), POP (Point of Place) packaging heat dissipation structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11594462B2 (en) | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods | |
| US11688664B2 (en) | Semiconductor device assembly with through-mold cooling channel formed in encapsulant | |
| US11862611B2 (en) | Thermal transfer structures for semiconductor die assemblies | |
| US11239095B2 (en) | Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill | |
| US20080093733A1 (en) | Chip package and manufacturing method thereof | |
| CN102414815B (en) | There is the multi-die semiconductor package of radiator | |
| JP6626083B2 (en) | Stacked semiconductor die assembly with high efficiency heat path and related systems | |
| US6429513B1 (en) | Active heat sink for cooling a semiconductor chip | |
| CN101425486A (en) | Flip chip packages with spacers separating heat sinks and substrates | |
| CN109585396A (en) | The laminate packaging semiconductor packages of thermal coupling | |
| CN200976345Y (en) | Chip packaging structure | |
| CN101882606B (en) | Heat-dissipation semiconductor encapsulation structure and manufacturing method thereof | |
| US20080185712A1 (en) | Semiconductor device and method for manufacturing the same | |
| CN101211872A (en) | Radiation-type semiconductor package member and its used radiation structure | |
| CN103050454A (en) | Package on package structure | |
| CN112908984A (en) | SSD (solid State disk) stacked packaging structure with radiating fins and manufacturing method thereof | |
| US11973000B2 (en) | Heat dissipation plate and semiconductor device | |
| CN101937884B (en) | Semiconductor packaging member | |
| CN116759397A (en) | Chip packaging structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20071114 |
|
| EXPY | Termination of patent right or utility model |