TW476148B - Semiconductor packaging piece and its manufacture method to improve lead bonding reliability - Google Patents

Semiconductor packaging piece and its manufacture method to improve lead bonding reliability Download PDF

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Publication number
TW476148B
TW476148B TW090108740A TW90108740A TW476148B TW 476148 B TW476148 B TW 476148B TW 090108740 A TW090108740 A TW 090108740A TW 90108740 A TW90108740 A TW 90108740A TW 476148 B TW476148 B TW 476148B
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semiconductor package
item
scope
patent application
recesses
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TW090108740A
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Chinese (zh)
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Ru-Sheng Liou
Jen-Huei Wu
Fu-Di Tang
Cheng-Shiu Shiau
Jin-Deng Shiu
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

This invention provides QFN semiconductor packaging piece manufacture method to improve reliability and prevent flash, which includes: preparing a lead plate having a top plane and a corresponding bottom plane, which is constructed by many lead frames in matrix arrangement and whose adjacent lead frames are linked using a plural number of bus bar; individual frames bottom bus bars and lead portions having a plural number of recesses made and using a heat resistant adhesive tape to completely adhere to the lead plate surface having the recesses; subsequently, performing die bonding, wire bonding and encapsulating in the way that the lead and the bottom surface of the die support are exposed; and finally cutting to complete manufacture of the QFN semiconductor packaging piece. The inventive method utilizes temperature variation in the process environment to control the adhesion strength between adhesive tape and lead frame. The employment of the adhesive tape can protect the bottom surface of leads from flashing and provide stable adhesion with the leads to improve bonding reliability.

Description

476148 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（1 ) 【發明領域】 本發明係有關一種半導體封裝件及其製法，尤指一 種藉由不同作業溫度控制貼片與導線架間之接合強度之 QFN半導體封裝件及其製法。 【發明背景】為因應電子產品輕薄短小的開發趨勢，現今半導體 裝置多朝向低成本、高性能以及高度集積化之方向發展， 准在半導體裝置之製造成本、性能性及記憶容量上力求改 良之餘，半導體裝置的體積以及整體厚度亦要求儘量精 巧，遂有晶片尺寸封裝結構（Chip Size Package，csp) 問世。晶片尺寸封裝結構（CSP) 一般係建構於一大型晶 片承載件（Chip Carrier)上，其上包含有多個矩陣列置 之封裝單元以供半導體晶片安置；每一封裝切單完成之晶 片尺寸封裝結構（CSP)其整體尺寸僅略大於其内所封裝 之半導體晶片，蔚為今後封裝製品之開發主流。 晶片尺寸封裝結構（CSP) 一般採用導線架形式封裝， 如QFN ( Quad-Flat N〇n-leaded)封裝件等。如第1圖以 QFN封裝件為例，此種封裝件係包括一晶片座ι〇〇，接合 於該晶片座100上之半導體晶片u，設置於該晶片座1〇〇 周圍俾供該晶片1〗與印刷電路板1 9電性連結之導腳 1 〇 1，連設於該晶片11與各導腳！ 〇丨間之導電銲線^ 2， 以及藉使該等導腳1〇1與晶片座1〇〇之外側表面及/或底 側表面外露之方式將該等導腳1〇1、晶片u、導電銲線12 以及該晶片座1〇〇加以包覆之封裝膠體13qQfn封裝 (請先閱讀背面之注意事項本頁) .裝 · 丨線 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 16222 經濟部智慧財產局員工消費合作社印製 4f76148 A7 -’ ----- B7 五、發明說明（2 ) 摒棄傳統QFP ( Quad Flat Package )封裝件利用外導腳 (External Lead)與印刷電路板導電連結之方式，而改以 其導腳ιοί之底側外露表面直接導電連接至印刷電路板19 上，相較於傳統QFP封裝形式得縮減整體封裝尺寸達 60%。另者，QFN封裝件免除外導腳之導腳設計，因而提 供更短之電訊傳輸路徑，以獲得更佳之電子運作效率。 然而，當QFN封裝件施以模壓製程藉以形成封裝膠 #體時，一般係使用兩件式半模模具組14，如第2圖所示， 該半模模具組14係包含一具有開槽形成塊u〇之上模ΐ4ι 以及一平檯式下模142,藉由該上模141與下模142喃合 夾固QFN半導體裝置而形成一模穴143俾供一熔融封裝 樹脂1 5注入。然而流動性封裝樹脂丨5往往滲入該等導腳 1〇1與晶片座100底側表面造成溢膠進而阻礙導腳1〇1與 外部裝置（如印刷電路板）對接點（請參第1圖1 9〇所示） 之導電觸接。另一方面，導腳101本身極其纖細難以固定， 鲁故而實施鮮線作業（Wire Bonding)時時常發生導腳滑動 而景々響其録接信賴性。此外，由於導腳1〇1與晶片座j 以及相鄰導腳10 1間之間距非常細微，製造過程中任何晃 動往往引發相鄰導腳101或導腳101與晶片n間產生不 當電性觸碰導致短路。因此業界一般於上片作業（ Bonding)實施前預先在導線板（即尚未切單前之導線架 組合體）底面黏一貼片（Adhesive Tape )方便導腳固著 定位，待模壓作業完成後復行撕除。 貼片之使用得以保護導腳底側表面防止溢膠侵入， 本纸張尺度適用中國國豕標準（CNS)A4規格（2】0 297公爱） 16222 -----^-----------------線 (請先閱讀背面之注意項再填寫本頁) 476148 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（3 ) 同時提供導線架上各導腳與晶片座一穩定附著力避免滑動 或晃動發生。惟該貼片使用之材質多為一熱固性或熱塑性 聚亞醯胺（Polyimide )膠片，如採傳統方式以塗敷有膠 黏劑之貼片直接平貼至導線板表面，將極難控制該貼片與 導線板間之接合強度：該貼片與導線板間之接合強度過 大，貼片撕除不易，除造成膠劑殘存導腳底側表面阻礙該 導腳與外部裝置電性連結之外，撕除貼片時的過度拉扯亦 易造成半導體封裝件本身變形受損；然若減弱該貼片與導 線板間之接合力，又恐無法有效杜絕溢膠現象之發生。因 此迫切高要ie出一項身以控制該貼片與導線板間接合強度 之作業方法。 【發明概述】 本發明之主要目的係提供一種利用導線架底面蝕刻 凹洞方式，藉由作業環境之溫度變化控制貼片與導線架間 之接合強度俾以阻絕溢膠侵入導腳底側表面，維持導腳與 外部裝置優良導電品質之QFN半導體封裝件。 、 本發明之另一目的係提供一種利用導線架底面姓刻 凹洞方式，藉由作業環境之溫度變化控制貼片與導線架間 之接合強度提供該導線架一穩定附著力避免導腳滑動或晃 動產生’ it以提昇導腳銲接信賴性a卿半導體封裝件。 本發明之再-目的係提供—種利用導線架底面姓刻 凹洞方式’藉由作業環境之溫度變化控制貼片與導線架間 之接合強度，取代傳統膠黏劑貼片藉以避免膠片撕除時引 發諸多問題之QFN半導體封裝件。 --------------裝--- (請先閱讀背面之注意事項本頁) · •蜂' 本纸張尺度適用中國國豕標準（CNS)A4規格 297公釐） 476148 A7 -------—_____ 五、發明說明（4 ) (請先閱讀背面之注意事項再填寫本頁) 鑒於上述及其他目的，本發明維持導腳銲接信賴性 以及防止溢膠之QFN半導體封裝件製法係包含：先備一 導線板’其具有一頂面及一相對之底面，該導線板係藉多 數矩陣列置之導線架所構成者，相鄰導線架間藉由多條匯 流條（Bus Bar)予以連接，該導線架中央部設有一晶片 座，並於該晶片座外圍形成有多數之導腳；於該導線板底 面之匯流條及導腳部開設有複數個凹洞，並藉以一耐熱性 _貼片完整貼合於設有凹洞之導線板表面；而後令一半導體 晶片接置至該晶片座上，再藉由多條導電銲線提供該晶片 與該等導聊間產生電1連結，最後藉使該等$ 底側表面外露之方式實施膠體封裝以及切單製程，即製得 此一 QFN半導體封裝件。 經请部智慧財產局員工消費合作社印製 本發明之QFN半導體封裝件製法不同於傳統製法之 特點，在於該導線架底面之導腳及匯流條上蝕刻形成複數 個凹洞。高溫作業環境下（280至3〇(rc )，該等凹洞藉由 參貼片蓋合致使熱空氣存封於凹洞内，而後改置於室溫，熱 空氣遇冷收縮導致該等凹洞顯現一低於大氣壓力之負廢狀 態，此時耐熱性貼片受到該負壓牵引而得穩固地吸附於導 線架底面，導腳底側表面與耐熱性貼片間完全密合，此舉 不僅使得該等導腳得穩固定置於貼片避免滑動或晃動產 生，提昇導腳之銲接信賴性；同時，進行膠體封裝製程時，j 導腳底側表面亦能有效防止溢膠之入侵。 另一方面，本發明半導體封裝件採用之貼片係為一 耐熱性貼片，使用時僅需平貼於導線板底面不必藉由任何 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐） 4 16222 476148 A7476148 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (1) [Field of Invention] The present invention relates to a semiconductor package and a method for manufacturing the same, especially a chip and lead frame controlled by different operating temperatures. QFN semiconductor package with bonding strength between them and its manufacturing method. [Background of the Invention] In response to the development trend of thin, light and short electronic products, today's semiconductor devices are mostly developed towards low cost, high performance, and high integration. We must strive to improve the manufacturing cost, performance, and memory capacity of semiconductor devices. The volume and overall thickness of semiconductor devices are also required to be as compact as possible, and a chip size package (CSP) was introduced. The chip size package structure (CSP) is generally constructed on a large chip carrier, which contains a plurality of packaging units arranged in a matrix for semiconductor wafer placement; each package is singulated to complete the chip size package The overall size of the structure (CSP) is only slightly larger than the semiconductor wafer packaged therein, and Wei is the mainstream for the development of packaged products in the future. The chip size package structure (CSP) is generally packaged in a lead frame, such as a QFN (Quad-Flat Non-leaded) package. As shown in FIG. 1, a QFN package is taken as an example. This package includes a wafer holder 100, and a semiconductor wafer u bonded to the wafer holder 100 is provided around the wafer holder 100 for the wafer 1 〖Guide pin 1 〇1 which is electrically connected to the printed circuit board 19 is connected to the chip 11 and each guide pin! 〇 丨 the conductive bonding wire ^ 2, and by way of exposing the outer surface and / or the bottom surface of the guide pins 101 and the wafer holder 100, the guide pins 101, the chip u, The conductive bonding wire 12 and the encapsulating gel 13qQfn packaged with the wafer holder 100 (please read the precautions on the back page first). Assembly · 丨 The paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 public love) 16222 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4f76148 A7-'----- B7 V. Invention Description (2) Abandon the traditional QFP (Quad Flat Package) package and use the external lead (External Lead) ) It is conductively connected to the printed circuit board, and the exposed surface of the bottom side of the guide pin is directly conductively connected to the printed circuit board 19. Compared with the traditional QFP package, the overall package size can be reduced by 60%. In addition, the QFN package eliminates the need for a guide pin design, thus providing a shorter telecommunication transmission path for better electronic operation efficiency. However, when the QFN package is subjected to a molding process to form an encapsulant, a two-piece mold mold set 14 is generally used. As shown in FIG. 2, the mold mold set 14 includes a grooved formation. The upper mold ΐ4ι of the block u0 and a platform-type lower mold 142 are formed by using the upper mold 141 and the lower mold 142 to sandwich and clamp the QFN semiconductor device to form a cavity 143 for injection of a molten encapsulation resin 15. However, the fluid encapsulation resin 丨 5 often penetrates the guide pins 101 and the bottom surface of the wafer holder 100 and causes overflow, which hinders the contact between the guide pins 101 and external devices (such as printed circuit boards) (see Figure 1). (Shown in Figure 19). On the other hand, the guide pin 101 itself is extremely thin and difficult to fix. Therefore, when the wire bonding operation is performed, the guide pin often slides, and Jing Jing sounds its recording reliability. In addition, since the distance between the guide pin 101 and the wafer holder j and the adjacent guide pin 101 is very fine, any shaking during the manufacturing process often causes improper electrical contact between the adjacent guide pin 101 or between the guide pin 101 and the wafer n. Touching can cause a short circuit. Therefore, the industry generally sticks an adhesive tape on the bottom surface of the lead board (ie, the lead frame assembly before cutting the order) before the bonding operation is carried out to facilitate the positioning of the guide feet. It will be restored after the molding operation is completed. Line tearing. The use of the patch can protect the bottom surface of the guide foot from the overflow of glue. This paper size applies to China National Standard (CNS) A4 (2) 0 297 public love. 16222 ----- ^ ------ ----------- Line (Please read the note on the back before filling out this page) 476148 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (3) Also provided on the lead frame Each guide pin and the wafer seat have a stable adhesion to avoid sliding or shaking. However, the material used for this patch is mostly a thermosetting or thermoplastic Polyimide film. If the traditional method is to apply the adhesive-coated patch directly to the surface of the wire board, it will be extremely difficult to control the patch. The bonding strength between the chip and the lead plate: The bonding strength between the patch and the lead plate is too large, and the patch is not easy to tear off. In addition to causing the adhesive to remain on the bottom surface of the guide foot and preventing the guide foot from being electrically connected to the external device, the tear Except for the excessive pulling during the patch, the semiconductor package itself is likely to be deformed and damaged; however, if the bonding force between the patch and the wiring board is weakened, it may not be able to effectively prevent the occurrence of glue overflow. Therefore, it is urgent to develop an operation method to control the bonding strength between the patch and the lead plate. [Summary of the Invention] The main purpose of the present invention is to provide a method of etching recesses on the bottom surface of the lead frame, and controlling the bonding strength between the patch and the lead frame through the temperature change of the working environment, so as to prevent the overflowing glue from invading the bottom surface of the guide foot and maintain QFN semiconductor package with excellent conductive quality for the guide pins and external devices. 2. Another object of the present invention is to provide a method of using the bottom face of the lead frame to dent the bottom surface of the lead frame to control the bonding strength between the patch and the lead frame by the temperature change of the working environment to provide the lead frame with a stable adhesion to prevent the guide legs from sliding or Sloshing produces' it to improve the soldering reliability of the lead pins. Another object of the present invention is to provide a method of using the bottom surface of the lead frame to dent the bottom surface of the lead frame to control the bonding strength between the patch and the lead frame by changing the operating environment temperature, instead of the traditional adhesive patch to avoid film tearing. QFN semiconductor packages that cause many problems. -------------- Loading --- (Please read the precautions on the back page first) · • Bee 'This paper size applies to China National Standard (CNS) A4 specification 297 mm ) 476148 A7 -------—_____ V. Description of the invention (4) (Please read the precautions on the back before filling this page) In view of the above and other purposes, the present invention maintains the reliability of guide pin welding and prevents glue overflow The manufacturing method of the QFN semiconductor package includes: preparing a lead plate having a top surface and an opposite bottom surface. The lead plate is formed by a plurality of lead frames arranged in a matrix, and adjacent lead frames are formed by a plurality of lead frames. A bus bar is connected to the central portion of the lead frame, and a plurality of guide pins are formed on the periphery of the wafer base. A plurality of recesses are provided on the bus bar and the guide leg portions on the bottom surface of the lead plate. Hole, and a heat-resistant chip is completely attached to the surface of the wire board provided with a recess; then a semiconductor wafer is connected to the chip holder, and the chip and the like are provided by a plurality of conductive bonding wires. An electrical 1 link was created between the guides, and finally the glue was implemented by exposing the bottom surface of these $ The body packaging and singulation processes can produce such a QFN semiconductor package. Printed by the Consumers' Cooperative of the Ministry of Intellectual Property Bureau of the People's Republic of China The manufacturing method of the QFN semiconductor package of the present invention is different from the traditional manufacturing method in that a plurality of recesses are formed by etching on the bottom pins and bus bars of the lead frame. Under high-temperature operating conditions (280 to 30 (rc)), the recesses are sealed by the reference patch to cause the hot air to be sealed in the recesses, and then changed to room temperature. The recession of the hot air causes the recesses. The hole shows a negative waste state lower than the atmospheric pressure. At this time, the heat-resistant patch is pulled by the negative pressure to be firmly absorbed on the bottom surface of the lead frame, and the bottom surface of the guide pin and the heat-resistant patch are completely tight. The guide pins can be stably fixed on the patch to avoid sliding or shaking, which improves the welding reliability of the guide pins. At the same time, when the colloidal packaging process is performed, the bottom surface of the guide pins can also effectively prevent the invasion of glue. The patch used in the semiconductor package of the present invention is a heat-resistant patch. When used, it only needs to be flatly affixed to the bottom surface of the conductor board. It does not need to use any Chinese paper standard (CNS) A4 specification (2) 0 X 297. Mm) 4 16222 476148 A7

經濟部智慧財產局員工消費合作社印製 膠黏劑黏接’免除膠黏劑殘留或貼片撕除時過度拉扯導致 半導體封裝件變形受損等疑慮，透過製程環境之溫度控制 亦得有效掌握貼片與導線板間之接合強度。 【圖示簡單說明】 以下兹以實施例配合所附圖示詳細說明本發明之特 點及功效： 第1圖係為習知之QFN半導體封裝件之剖面示意圖； 第2圖係為習知之QFN半導體封裝件出現溢膠現象 之局部放大圖； 第3圖係為本發明之QFN半導體封裝件之剖面示意 圍， 第4A至4F圖係為本發明中維持銲接信賴性結構之 整體製作流程圖；以及， 第5圖係為本發明之QFN半導體封裝件施以上片及 ^線作業之剖面示意圖。 【發明詳細說明】 以下即配合第3至5圖詳細揭露本發明維持導腳銲 接信賴性之QFN半導體封裝件之製作流程。 如第3圖所示，本發明之qFN半導體封裝件2係包 括有一導線架20，其中央部設一晶片座2〇〇，並於該晶片 座200外圍形成多條導腳201，該等導腳2〇1底側表面蝕 刻有複數個凹洞24; —半導體晶片21，係接置於該晶片 座200上，並藉由多條導電銲線22提供該半導體晶片21 與該等導腳2(H進行電性連結，以及一包覆半導體晶片 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 5 16222 (請先閱讀背面之注意事項Η e本頁) 裝 訂· ;線· 4/6148 經 部 智 慧 財 產 局 消 費 合 社 印 製 Α7 Β7 五、發明說明（6 ) 21、多條銲線22、部分晶片座200及導腳201之封裝膠 體23 〇 首先製備一導線板25,該導線板25之製作方式係將 —如鋼等材質之導電片（未圖示）經蝕刻（Etching )形 成多個呈矩陣列置之導線架20。參閱第4A圖，每一導線 架20中央係設有一晶片座2〇〇俾供該半導體晶片（未圖 示）接置，且於該晶片座200外圍一體形成有多數之導腳 参2〇1，相鄰導線架20間則以複數條匯流條（Bus bar) 202 進行連接。 第4B圖係為該等導腳201與匯流條202之局部放大 透視圖’該等導腳201及匯流條202與半導體晶片（未圖 示）接置面同側者係定義為頂面201a，202a，其相對之反 側面則定義作底面201 b，202b。如圖所示，在該等導腳201 以及匯流條202底面201 a，20 lb預定形成複數個的凹洞定 義開口位置240，而後，如第4C及4D圖所示，於導腳 #底面201b上覆蓋光阻26及光罩27，進行一選擇性曝光 (Selective Exposure)、顯影製程（Development)以及蚀 刻製程（Etching Process )而形成複數個凹洞24。（第4C 圖及第4D圖係以導腳201為例說明，惟匯流條底面202b 之凹洞24開設方法與導腳201完全相同，故不再重述。） 蝕刻完成導腳及匯流條底面201 b，202b具有多數凹洞 24之導線架20置入280至300。(：之高溫環境中，請參閱 第4E圖。此高溫環境下用一耐熱性貼片28平整地貼合 於導線架20底面俾完整覆蓋該等凹洞24開口使其内部呈 ^--------^--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 6 16222 476148 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（7 ) 現一密閉狀態，該耐熱性貼片28為一熱塑性絕緣貼片， 多為聚亞醢胺膠片等材質且該貼片28與該導線架（未圖 示）間無須塗敷任何膠黏劑，此時兩者之間並無任何接合 強度產生（如第4Fa圖所示）。之後將該導線架（未圖示） 移至室溫，此時存封於凹洞内之熱空氣遇冷收縮導致凹洞 24内顯現一低於大氣壓力之負壓狀態，該耐熱性貼片28 受到該負壓牽引而能穩固吸附於導腳201底面（如第4Fb 圖所示）。 接著請參第5圖，將其底面穩固貼附有貼片28之導 線架20進行一上片( Die Bonding )及銲線銲接程序（wire Bonding)，令使該半導體晶片21黏固於該晶片座2〇〇上， 並以銲設多條導電銲線22用以提供該晶片21與該等導腳 2 01電性連結。測試結果顯示該導線架2 〇裝置即使處於 上片烘烤（約150°C )以及銲線接置160至200°C之高溫 狀態下’該貼片28與導線架201間依然保有足夠的接合 強度，因而得以有效地避免導腳201晃動，提昇導腳2〇1 之銲接信賴性。 最後進行模壓製程俾以形成一封裝膠體23，回溯第 3圖所示，將該QFN半導體裝置置入兩件式半模模具組 (未圖示）内夾持俾構成一模穴（未圖示）藉以容納熔融 封裝樹脂（未圖示）灌注，貼片（請酌參第5圖28所示） 與導線架20間維持足夠之接合強度致使流動性封裝樹脂 (未圖示）無法滲入該等導腳2〇1底側表面，故而避免溢 膠現象之發生。待封裝樹脂固化俾形成包覆半導體晶片 請 先 閱 讀 背 δ 之 注 意 事 項 i 裝 訂 0 線 16222 經濟部智慧財產局員工消費合作社印製 476148 」 A7 ------ B7 五、發明說明（8 ) 21、多數銲線22以及部分導腳2〇1而使該晶片座與導腳 底側表面外露之封裝膠體23後，實施脫模同時剝除該耐 熱性貼片（未圖示），復施以切單作業，即製得本發明之 QFN半導體封裝件。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之實質技術内容範圍。本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中。任何他人所完成 参之技術實體，若與下述之申請專利範圍定義者係完全相 --------------裝-------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 同，或為一等效之變更 【符號標號說明】 ，均將視為涵蓋於此專利範圍之中 20 導線架 100,200 晶片座 101，201 導腳 202 匯流條 11,21 半導體晶片 12,22 導電銲線 220 銲點 13,23 封裝膠體 14 兩件式半模模具組 140 開槽形成塊 >141 上模 142 下模 143 模穴 15 溶融封裝樹脂 19 印刷電路板 190 對接點 24 凹洞 240 凹洞定義開口位置 25 導線板 26 光阻 27 光罩 28 耐熱性貼片 本纸張尺度適用中爛家標準（CNS)A4規格⑵Qx297公髮） % T6222The Intellectual Property Bureau of the Ministry of Economic Affairs 'employee consumer cooperatives print adhesives to' eliminate concerns about adhesive residues or excessive pulling during chip tearing, which can cause deformation and damage to semiconductor packages. The temperature control of the process environment can also effectively control the paste. The bonding strength between the sheet and the lead plate. [Brief description of the diagram] The following is a detailed description of the features and effects of the present invention with examples and accompanying drawings: Figure 1 is a schematic cross-sectional view of a conventional QFN semiconductor package; Figure 2 is a conventional QFN semiconductor package Figure 3 is a partial enlarged view of the occurrence of glue overflow; Figure 3 is a schematic cross-sectional view of the QFN semiconductor package of the present invention, and Figures 4A to 4F are flowcharts of the overall fabrication of a soldering reliable structure in the present invention; and, FIG. 5 is a schematic cross-sectional view of a QFN semiconductor package in accordance with the present invention, which is subjected to wafer and wire operations. [Detailed description of the invention] The manufacturing process of the QFN semiconductor package which maintains the reliability of the soldering of the lead pins according to the present invention is disclosed in detail with reference to Figs. 3 to 5 below. As shown in FIG. 3, the qFN semiconductor package 2 of the present invention includes a lead frame 20, a wafer holder 200 is provided at a central portion thereof, and a plurality of guide pins 201 are formed on the periphery of the wafer holder 200. A plurality of recesses 24 are etched on the bottom surface of the foot 201; the semiconductor wafer 21 is connected to the wafer holder 200, and the semiconductor wafer 21 and the guide pins 2 are provided by a plurality of conductive bonding wires 22. (H is used for electrical connection, and a coated semiconductor wafer. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 5 16222 (Please read the precautions on the back first Η this page) Binding ·; Wire · 4/6148 Printed by the Consumer Property Association of the Ministry of Intellectual Property Bureau A7 Β7 V. Description of the Invention (6) 21, Multiple bonding wires 22, some chip holders 200 and encapsulants 23 of the guide pins 201 〇 First prepare a wire board 25. The manufacturing method of the lead plate 25 is to etch (Etching) conductive plates (not shown) made of steel and other materials to form a plurality of lead frames 20 arranged in a matrix. See FIG. 4A, each lead frame 20 center is provided with a wafer holder 200 for the semiconductor wafer (not (Pictured), and a large number of guide pins 201 are integrally formed on the periphery of the wafer holder 200, and adjacent lead frames 20 are connected by a plurality of bus bars 202. FIG. 4B is A partially enlarged perspective view of the guide pins 201 and the bus bar 202 'The same sides of the connecting surfaces of the guide pins 201 and the bus bar 202 and the semiconductor wafer (not shown) are defined as the top surfaces 201a, 202a, and the opposite The opposite sides are defined as the bottom surfaces 201b, 202b. As shown in the figure, a plurality of recesses are planned to form openings 240 in the guide legs 201 and the bottom surfaces 201a, 20 lb of the bus bar 202, and then, as shown in Sections 4C and 4C, As shown in the 4D diagram, a photoresist 26 and a photomask 27 are covered on the bottom surface 201b of the guide pin #, and a selective exposure (Development Exposure), a development process (Etching Process) and an etching process (Etching Process) are formed to form a plurality of recesses 24. (Figures 4C and 4D are based on the guide pin 201 as an example, but the method of opening the recess 24 in the bottom surface 202b of the bus bar is exactly the same as the guide pin 201, so it will not be repeated.) The etching of the guide pin and the bus bar is not repeated. The lead frame 20 with a plurality of recesses 24 on the bottom surfaces 201 b and 202 b is placed in 280 To 300. (: In high temperature environment, please refer to Figure 4E. Under this high temperature environment, a heat-resistant patch 28 is used to flatly adhere to the bottom surface of the lead frame 20, and the openings of these recesses 24 are completely covered to make the interior ^ -------- ^ --------- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 6 16222 476148 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (7) It is in a sealed state. The heat-resistant patch 28 is a thermoplastic insulation patch, mostly made of polyurethane film and other materials. There is no need to apply any adhesive between the patch 28 and the lead frame (not shown), and at this time, there is no bond strength between the two (as shown in Figure 4Fa). The lead frame (not shown) is then moved to room temperature. At this time, the hot air stored in the cavity shrinks when it is cold, causing a negative pressure state below the atmospheric pressure to appear in the cavity 24. The heat-resistant patch 28 Being pulled by this negative pressure, it can be firmly adsorbed on the bottom surface of the guide leg 201 (as shown in Fig. 4Fb). Next, referring to FIG. 5, the lead frame 20 with the patch 28 firmly attached to the bottom surface is subjected to a die bonding and wire bonding process, so that the semiconductor wafer 21 is fixed to the wafer. A plurality of conductive bonding wires 22 are provided on the base 200 to provide electrical connection between the chip 21 and the guide pins 201. The test results show that the lead frame 20 device has sufficient bonding between the patch 28 and the lead frame 201 even when it is baked at a high temperature (about 150 ° C) and the bonding wire is placed at a high temperature of 160 to 200 ° C. Strength, so it can effectively prevent the guide pin 201 from shaking, and improve the welding reliability of the guide pin 201. Finally, the molding process is performed to form a packaging colloid 23. As shown in FIG. 3, the QFN semiconductor device is placed in a two-piece half-mold mold set (not shown), and the 俾 is formed into a cavity (not shown). ) In order to accommodate the potting of the molten encapsulation resin (not shown), the patch (see Fig. 5 and Fig. 28 as appropriate) maintains sufficient bonding strength with the lead frame 20 so that the fluid encapsulation resin (not shown) cannot penetrate into these The bottom surface of the guide leg 201 is prevented from overflowing. When the packaged resin is cured and the coated semiconductor wafer is formed, please read the precautions on the back δ. Binding 0 Line 16222 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476148 ”A7 ------ B7 V. Description of Invention (8) 21. After the majority of the bonding wires 22 and part of the guide pins 201 are used to expose the chip holder and the sealing gel 23 on the bottom surface of the guide pins, the mold release is performed and the heat-resistant patch (not shown) is peeled off at the same time. The single-cutting operation produces the QFN semiconductor package of the present invention. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity completed by others, if it is completely the same as the definition of the scope of patent application below -------------- install ------- order ----- ---- Wire (please read the precautions on the back before filling this page) The same or an equivalent change [Symbol Description] will be deemed to be covered by this patent. 20 Lead frame 100,200 chip holder 101, 201 Guide pins 202 Bus bars 11, 21 Semiconductor wafers 12, 22 Conductive bonding wires 220 Solder joints 13, 23 Encapsulants 14 Two-piece half-mold mold sets 140 Slotted blocks > 141 Upper mold 142 Lower mold 143 mold Cavity 15 Melting and sealing resin 19 Printed circuit board 190 Butt joints 24 Recesses 240 Recesses define opening positions 25 Lead boards 26 Photoresistors 27 Photomasks 28 Heat-resistance patches This paper applies the CNS A4 specification⑵Qx297 (Public)% T6222

Claims (1)

476148 A8 B8 C8 D8 申請專利範圍 經濟部智慧財產局員工消費合作社印製 •種半導體封裝件製法，係包含·· 先備一導線板，其具有一頂面與一相對之底面， 且該導線板係由複數個導線架所構成，各導線架内具 有一晶片座及多數形成於該晶片座外圍之導腳； 於該導線板底面開設有複數個凹部，並藉一覆蓋 層完整平貼於設有該等凹部之導線板表面；曰 將一半導體晶片黏置於該晶片座頂面，並以多數 導電元件導電連結該半導體晶片與該等導腳； 進行一封裝膠體製程藉由外露該晶片座與該等導 腳底面方式包覆該半導體晶片與多數第一導電元件， 而後剝除該覆蓋層；以及， 實施切單作業俾製得複數個封裝完成之半導體封 裝件。 2.如申請專利範圍第丨項之半導體封裝件製法，其中， 該半導體封裝件係為一 QFN半導體封裝件。 3·如申請專利範圍第丨項之半導體封裝件製法，其中， 該導線架與該半導體晶片接置方向同側者係定義為頂 面，與其反側者係定義為底面。 4·如申請專利範圍第1項之半導體封裝件製法，其中， 該等導線架係呈矩陣方式列置。 5·如申請專利範圍第4項之半導體封裝件製法，其中， 其矩陣列置之相鄰該導線架間係藉由複數條匯流條 (Bus Bar )進行連接。 6.如申請專利範圍第1項之半導體封裝件製法，其中， 1. 請 先 閱 讀 背 & 之 注 意 I 再m k 賣 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 16222 經濟部智慧財產局員工消費合作社印製 476148 A8 B8 C8 --------- -D8 六、^ — -- 該凹部係為一凹洞。 7·如申請專利範圍帛1項之半導體封裝件製法，其中， 該等凹部係開設於該導線板底面之導腳上。 8·如申請專利範圍第1或5項之半導體封裝件製法，其 中，該等凹部係開設於該導線板底面之匯流條上。八 9·如申7專利範圍第丨項之半導體封裝件製法，其中， 該覆蓋層係為一耐熱性貼片。 %〇·如申請專利範圍第9項之半導體封裝件製法，其中， s $ ”’、眭貼片係選自聚亞醯胺谬片、熱塑性絕緣膠劑 等所組紐群之一者。 u •如申請專利範圍第1項之半導體封裝件製法，其中， 該覆蓋層無須透過任何膠黏劑與該導線板表面進行黏 接。 12·如申請專利範圍第i項之半導體封裝件製法，其中， 該覆蓋層係完全蓋合該等凹部開口俾使該凹部内呈現 • 一密閉狀態。 13·如申請專利範圍第丨項之半導體封裝件製法，其中， 該導電元件係為一金線。 14· 一種半導體封襞件，係包含： 一導線架，係具有一頂面與一相對之底面，該導 線架中央設有一晶片座，其外圍並形成有多數之導腳； 複數個凹部，係形成於該導線架底面，得藉一覆 蓋層完整平貼於設有該等凹部之導線架表面； 一半導體晶片，係接置於該晶片座上； I n n ϋ ί -- I . . ί n 1 « n 1— n Ι·- - l HI m a I ·ϋ >ϋ i —>i ·· I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 10 L6222 476148 六、申請專利範圍 多數導電元件，俾供該半導 行電性連結;以及，"體晶片與該等導腳進 -封詩體’藉^整包㈣半導 數之導電元件。 a从及多 it如申請專利範圍第14項之半導體封裝件，1中， 導體封裝件係為一 QFN半導體封裝件。〃，該半 16.如申請專利範圍第14項之半導體封褒件，盆 線架與該半導體晶片接置方向同側者係定義為^導 與其反側者係為底面。 Γ7 ·如申請專利範圍第14項之半導體封裝件，其中， 兩導線架間係、以複數條匯流條（BusBar)進行連=目鄰 18. 如申請專利範圍第14項之半導體封裝 盆 。 部係為一凹洞。 八〒，該凹 19. 如申請專利範圍第14項之半導體封裝 苴 凹部係開設於該導線架底面之導腳上。 2〇.如申請專利範圍第14或17項之半導體封裝件，其中， 該等凹部係開設於該導線架底面之匯流條上。 21·如申請專利範圍第14項之半導體封裝件，其中，= 盍層係為一耐熱性貼片。 5覆 22·如申請專利範圍第14項之半導體封裝件，1 ^χ I 5該耐 熱性貼片係選自聚亞醯胺膠片、熱塑性絕緣 組組群之一者。 23.如申請專利範圍第14項之半導體封裝件，发 八甲’該覆 盍層無須透過任何膠黏劑與該導線板表面進行黏接 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 11 16222 請 先 閱 讀 背 面 之 注 意 事 項 再 Μ 11,寫 本 頁 Φ 經濟部智慧財產局員工消費合作社印製 476148 A8 B8 C8 D8 六、申請專利範圍 24. 如申請專利範圍第14項之半導體封裝件，其中，該覆 蓋層係完全封合該等凹部開口俾使該凹部内呈現一密 閉狀態。 25. 如申請專利範圍第14項之半導體封裝件，其中，該導 電元件係為一金線。 % (請先閱讀背面之注意事項再填寫本頁)476148 A8 B8 C8 D8 Patent application scope Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • Printed by semiconductor consumer package method, including: preparing a lead plate with a top surface and an opposite bottom surface, and the lead plate It is composed of a plurality of lead frames, each lead frame has a wafer holder and a plurality of guide legs formed on the periphery of the wafer holder; a plurality of recesses are formed on the bottom surface of the lead plate, and a cover layer is completely flat and pasted on the device. The surface of the wiring board with the recesses; that is, a semiconductor wafer is adhered to the top surface of the wafer holder, and the semiconductor wafer is electrically connected to the guide pins with most conductive elements; a sealing process is performed by exposing the wafer holder The semiconductor chip and most of the first conductive elements are covered with the bottom surface of the guide pins, and then the cover layer is peeled off; and a singulation operation is performed to obtain a plurality of packaged semiconductor packages. 2. The method for manufacturing a semiconductor package according to item 丨 of the application, wherein the semiconductor package is a QFN semiconductor package. 3. The method for manufacturing a semiconductor package according to item 丨 of the application, wherein the same side of the lead frame and the semiconductor wafer as the direction of connection is defined as the top surface, and the opposite side is defined as the bottom surface. 4. The method for manufacturing a semiconductor package according to item 1 of the scope of patent application, wherein the lead frames are arranged in a matrix manner. 5. The method for manufacturing a semiconductor package according to item 4 of the scope of patent application, wherein adjacent lead frames arranged in a matrix are connected by a plurality of bus bars. 6. For the manufacturing method of the semiconductor package item No. 1 of the scope of patent application, among which: 1. Please read the back & note I and then mk sell order. The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297). 16222) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476148 A8 B8 C8 --------- -D8 VI. ^-The recess is a recess. 7. The method of manufacturing a semiconductor package according to item 1 of the patent application, wherein the recesses are provided on the guide pins on the bottom surface of the lead plate. 8. If the method of manufacturing a semiconductor package according to item 1 or 5 of the patent application scope, wherein the recesses are provided on the bus bar on the bottom surface of the lead plate. 8. The method for manufacturing a semiconductor package according to item 7 of the patent claim 7, wherein the cover layer is a heat-resistant patch. % 〇 · Such as the method for manufacturing a semiconductor package according to item 9 of the scope of patent application, in which s $ "'and 眭 are selected from one of the group consisting of polyimide film, thermoplastic insulating adhesive, etc. u • For example, the method for manufacturing a semiconductor package according to item 1 of the patent scope, wherein the cover layer does not need to be adhered to the surface of the lead board through any adhesive. 12. The method for manufacturing a semiconductor package according to item i of the scope of patent, where: The covering layer completely covers the openings of the recesses so that the recesses appear in a closed state. 13 · As in the method for manufacturing a semiconductor package according to the scope of the patent application, wherein the conductive element is a gold wire. 14 · A semiconductor package includes: a lead frame having a top surface and an opposite bottom surface; a chip holder is provided in the center of the lead frame, and a plurality of guide pins are formed on the periphery of the lead frame; a plurality of recesses are formed on The bottom surface of the lead frame can be completely and flatly attached to the surface of the lead frame provided with the recesses by a covering layer; a semiconductor wafer is connected to the wafer holder; I nn ϋ ί-I.. Ί n 1 « n 1— n Ι ·--l HI ma I · ϋ > ϋ i — > i ·· I (Please read the notes on the back before filling out this page) This paper size applies Chinese National Standard (CNS) A4 specifications ( (210 X 297 mm) 10 L6222 476148 VI. Most of the conductive elements in the scope of the patent application, for the semi-conductor to be electrically connected; Semi-conducting conductive elements. A. The semiconductor package as described in item 14 of the scope of patent application. In 1, the conductor package is a QFN semiconductor package. Alas, the semi-item 16. In the semiconductor package, the side of the basin wire frame and the semiconductor wafer in the same direction is defined as the bottom surface and the opposite side as the bottom surface. Γ7 · Semiconductor package according to item 14 of the patent application, where two wires It is connected between multiple bus bars (BusBar) between the shelves = the neighbor 18. If the semiconductor package pot of the scope of the patent application is No. 14, the department is a recess. Hachi, the recess 19. If the scope of the patent application is No. The semiconductor package recessed part of item 14 is opened in On the guide pins on the bottom surface of the lead frame. 20. The semiconductor package of item 14 or 17 in the scope of patent application, wherein the recesses are provided on the bus bar on the bottom surface of the lead frame. Item of the semiconductor package, where = 盍 layer is a heat-resistant patch. 5 cover 22 · If the semiconductor package of the scope of application for item 14, 1 ^ χ I 5 The heat-resistant patch is selected from Poly Asia Glutamate film, one of the thermoplastic insulation group. 23. If the semiconductor package of the scope of patent application No. 14 is issued, the coating layer does not need to be bonded to the surface of the wiring board through any adhesive. Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 public love) 11 16222 Please read the precautions on the back before writing M 11, write this page 6. Scope of patent application 24. For the semiconductor package of item 14 of the scope of patent application, wherein the covering layer completely seals the openings of the recesses so that the recesses present a closed state. 25. The semiconductor package of claim 14 in which the conductive element is a gold wire. % (Please read the notes on the back before filling this page) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 12 16222Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 12 16222
TW090108740A 2001-04-12 2001-04-12 Semiconductor packaging piece and its manufacture method to improve lead bonding reliability TW476148B (en)

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