WO2012058074A2

WO2012058074A2 - Thermal isolation in 3d chip stacks using gap structures and contactless communications

Info

Publication number: WO2012058074A2
Application number: PCT/US2011/056957
Authority: WO
Inventors: Paul Damian Franzon; John Wilson
Original assignee: Rambus Inc.
Priority date: 2010-10-28
Filing date: 2011-10-19
Publication date: 2012-05-03
Also published as: WO2012058074A3

Abstract

A semiconductor package is disclosed. The semiconductor package includes a first semiconductor device having a first contactless signaling interface; and a second semiconductor device. The second semiconductor device has a second contactless signaling interface to electrically communicate with the first contactless signaling interface. The second semiconductor device is formed with a gap disposed proximate the second contactless signaling interface.

Description

THERMAL ISOLATION IN 3D CHIP STACKS USING GAP STRUCTURES AND

CONTACTLESS COMMUNICATIONS

TECHNICAL FIELD

[0001] The disclosure herein relates to chip-to-chip interfaces and more particularly to an apparatus and method for thermally isolating integrated circuit chips in 3D chip stacks.

BACKGROUND

[0002] Three-dimensional (3D) integrated circuit (IC) packaging techniques provide a space-efficient and low-cost way to assemble multiple IC chips. An important problem associated with 3D chip stacks is the lack of thermal isolation between adjacent chips. The problem is often apparent when a high performance processor is stacked with one or more DRAM die. The high performance processor might dissipate in excess of 100 W and operate at a junction temperature in excess of 100°C, when air-cooled through its backside. In contrast, a DRAM die stack typically operates at power levels of a few Watts or less, with junction temperatures of approximately 85°C or lower. The relatively low junction operating temperature is important as the DRAM device leakage characteristic generally doubles with each 10°C increase in operating temperature. As leakage increases, the DRAM refresh rate typically also needs to correspondingly increase. Increasing the refresh rate to the DRAM memory cells undesirably reduces the available memory bandwidth and increases DRAM power consumption. Simultaneously, it is important to be able to communicate between the DRAM(s) and processor, possibly at data rates in excess of a Terabyte per second.

[0003] What is needed and as yet unavailable is an apparatus and method for thermally isolating the DRAM from a high-powered processor in a 3D chip stack in a low-cost manner, while still being able to communicate across the method used for thermal isolation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.

[0005] FIG. 1 illustrates one embodiment of a 3D chip stack; [0006] FIGs. 2A - 2C illustrate embodiments of the thermal interface of FIG. 1 ;

[0007] FIG. 3 illustrates an exploded view of a portion of one embodiment of a thermal interface employing a vacuum gap with support structures; and

[0008] FIG. 4 illustrates an embodiment of a 3D chip stack employing power and ground connections to first and second IC chips via peripheral and through-silicon-via connections.

DETAILED DESCRIPTION

[0009] Packaging structures and associated methods are disclosed herein that improve thermal isolation characteristics between chips in 3D chip stacks while permitting high bandwidth communication. One embodiment of a packaged semiconductor device includes a first semiconductor device having a first contactless signaling interface, and a second semiconductor device. The second semiconductor device has a second contactless signaling interface to electrically communicate with the first contactless signaling interface. The second semiconductor device is formed with a gap disposed proximate the second contactless signaling interface. By implementing the formed gap, the thermal isolation of the second device is greatly improved, allowing for separate cooling paths to cool the semiconductor devices.

[0010] In a further embodiment, a semiconductor package is disclosed that includes a first

semiconductor device having a first surface formed with a first AC-coupled signaling interface and a first DC-coupled power interface. A second semiconductor device is disposed in a face-to-face orientation with the first semiconductor device. The second device has a second surface formed with a second AC-coupled signaling interface to electrically communicate with the first AC-coupled signaling interface. The second semiconductor device includes a third surface disposed opposite the second surface and formed with a second DC-coupled power interface. In this manner, the mechanical coupling between the first and second devices avoids any power-dissipating DC connections, instead providing for the DC couplings on a different surface of the second device.

[0011] In some embodiments, the first and second semiconductor devices comprise respective CPU and DRAM devices. In further embodiments, the gap formed in the second device comprises a thin vacuum gap to thermally isolate the DRAM from the processor. Capacitive or inductive coupling is then used to communicate between the chips. [0012] Referring to FIG. 1, a packaged semiconductor device is shown, generally designated 100, that includes a first semiconductor component 102 directly attached to a second semiconductor component 104 to form a 3D chip stack 106. The components may each comprise integrated circuit chips, printed circuit boards, or the like. The direct attachment of the components may take various forms, such as flip-chip or face-to-face bonding, and generally involves an attachment free from any intervening components, such as interposers or the like. In one embodiment, the first semiconductor device is embodied as a processor chip, such as a CPU or memory controller, while the second semiconductor device may be realized as a discrete DRAM component. The second semiconductor device includes a thermal isolator 108 configured to improve thermal isolation between the components.

[0013] To take advantage of the improved thermal isolation characteristics of the chip stack 106, a first cooling path 1 10 is disposed proximate the first semiconductor device 102 to prevent overheating of the first device. In a similar manner, a second cooling path 112 is disposed proximate the second semiconductor device 104. The respective cooling paths may form a portion of any form of cooling system and associated cooling media, such as air, liquid, plasma, or metal. By utilizing separate independent cooling paths for each device, enabled through use of the thermal isolator 108, overall cooling costs for cooling the entire semiconductor package 100 may be significantly reduced.

[0014] Further referring to FIG. 1, the semiconductor devices 102 and 104 include respective contactless signaling interfaces 114 and 1 16 to carry out electrical signaling communications between the stacked components. The contactless interfaces may include respective arrays of capacitive or inductive structures that cooperate to form capacitively coupled or inductively coupled interconnects that operate in accordance with one or more pulsed signaling protocols well-known to those skilled in the art. Each interface employs an array of metal or oxide structures that form one portion of the coupled interconnect. Detail 2A - 2C highlights a generic interconnect, with FIGs 2A - 2C illustrating specific embodiments consistent with the generic interconnect. The embodiments illustrated in FIGs 2A - 2C also illustrate various structures employed in alternative embodiments of the thermal interface 108.

[0015] Referring now to FIG. 2A, the first component 102 includes a first array of signal pads 202 that abut an engagement surface 204. The pads 202 overlay a matching array of signal pads 206 formed in a gap 208 in the second component 104. The gap 208 forms a cavity within the second device 104 such that the arrays of pads 202 and 206 are separated in a spaced-apart opposing orientation that prevents direct current (DC) connections for signaling purposes. Instead, AC-coupled connections are formed between the components to allow signaling in accordance with a contactless signaling protocol. In this manner, the directly opposing spaced-apart pads may cooperate to take on the form of series capacitors or mutually coupled inductors. With short-range, face-to-face communications between pad arrays, 50 femtoFarads (fF) of series capacitance gives a robust capacitive link that can support additional interconnects, though successful communications have been demonstrated down to 5 fF. In a similar manner, an inductance on the order of approximately 1 nanoHenry (nH) provides reasonable signaling. In many circumstances, inductive coupling can withstand a further chip-to-chip spacing than capacitive coupling. A standoff of up to 1 inductor radius is feasible.

[0016] Figure 2B illustrates a further embodiment of a thermal interface 108 that interfaces a plurality of solder balls or microbumps 210 between the first and second IC chips 102 and 104. The second component includes a gap 208 proximate to the surface of the IC, similar to that shown in Figure 2A. Use of the microbumps 210 enables a standardized mechanical attachment for stacking the two semiconductor devices. Moreover, the additional spacing between the chips 102 and 104 caused by the height of the microbumps forms additional volume for thermal isolation purposes to assist the thermal conductivity exhibited by the gap 208.

[0017] FIG. 2C shows an additional embodiment of a thermal interface 108 that partitions the gap 208 into multiple gaps bounded by oxide structures 212 or the like. Depending on the application and thermal conductivity requirements, a one-to-one correspondence between gaps and I/O interconnects may be realized. This may be contrasted to the shared gap structures of FIGs 2A and 2B.

[0018] FIG. 3 illustrates an exploded view of one embodiment of an interface structure within a semiconductor device that implements enhanced structural rigidity within the gap 108 (such as in FIG. 2A). A lowermost pad 302 serves as one end of a capacitive or inductive interconnect. Overlying the pad is a layer of oxide 304. An array of oxide pillars 306 are then formed on the oxide layer. The pillars may be constructed via suitable etching or thin film buildup techniques to form structures having a cross-sectional area of approximately Ι μιη² or less. Other configurations are envisioned as alternatives to the array of pillars, such as honeycomb or ridge-shaped structures. Varying the shapes of the structures may affect the level of "fill" within the gap, allowing for an additional measure of control over the thermal conductivity characteristics associated with the gap. The pillars lay beneath a second layer of oxide 308 formed parallel with the first layer 304. The second oxide layer cooperates with the first layer to form the gap 108 (such as in FIG. 2A), with the pillars 306 essentially defining standoffs that are vertically disposed therebetween. An engagement pad 310 is formed above the second layer of oxide to receive a solder ball 312.

[0019] Depending on the application, the gap structures of FIGs 2A - 2C and FIG. 3 may be evacuated of gas to form a vacuum, filled with gas such as air, or filled with an aerogel or the like to exhibit a desired thermal conductivity characteristic. Employing an aerogel provides not only thermal advantages, but also structural support advantages in the gap. Table 1 below lists the thermal conductivities for a variety of materials for comparison purposes. Generally, the lower the thermal conductivity value, the better the thermal isolation characteristics of the material.

Table 1. Thermal conductivities of relevant materials.

[0020] Using, the conductivity values listed in Table 1, it is possible to estimate the thermal performance for various chip stack configurations using the standard formula for temperature drop,

T = L/(kA) P,

where "L" is the length of a heat transfer path, "k" is the thermal conductivity, "A" is the cross-sectional area and "P" represents the power.

[0021] An important issue when employing capacitive or inductive interconnects involves delivering DC voltages and currents to, for example, establish power and ground levels. FIG. 4 illustrates a semiconductor package, generally designated 400, that delivers power and ground from a substrate 402, such as a printed circuit board or ceramic, to a first IC 404 via peripherally disposed solder balls 406 and a redistribution layer (not shown) formed along the surface of the first semiconductor chip. A second IC 408, such as a DRAM, receives power and ground from a backside array of through-silicon vias 410 that are respectively coupled to solder balls 412 interconnecting the DRAM 408 to the substrate 402. Through-silicon-via structures and corresponding fabrication methods are well-known to those skilled in the art and warrant no further disclosure herein.

[0022] Further referring to FIG. 4, the first and second semiconductor devices 404 and 408 employ respective AC-coupled signaling interfaces 414 and 416, configured in accordance with any of the embodiments described previously. A thermal isolator 418 is also employed and may be realized by any of the thermal isolator embodiments previously presented herein.

[0023] Table 2 provided below lists the thermal performance values for a variety of 3D chip stack configurations for comparison purposes. All of the results assume that the power P=100 W. A higher ΔΤ in the table indicates a better thermal isolation characteristic. Note, these results are not predictive, since they ignore heat spreading, convective heat paths, as well as the presence of other materials. However, they are useful for comparison purposes. Note, that at these temperatures, radiative heat transfer is negligible.

[0024] Scenarios 1 and 2 in Table 2 involve connection of a processor IC to a memory stack. It shows clearly how thermal isolation improves by using an interposer between the semiconductor devices. Case 2 may be thought of as a baseline for comparison purposes against the other cases outlined in Table 2.

[0025] Scenarios 3-6 employ capacitive coupling techniques. Case 3 represents straightforward capacitive coupling, in which a layer of oxide is provided between oppositely disposed contacts to form the series capacitor. If an air, or vacuum gap, is included in the series capacitor interconnect structure, such as described herein, the thermal isolation greatly improves.

[0026] Further referring to Table 2 below, although including a vacuum gap in the capacitor structure increases thermal conductivity, it may decrease the capacitance. Thus, it may be useful to minimize the gap thickness, and increase the effective area of the capacitor. For example, with a 50 nm vacuum gap, and a total of 1 μιη of silicon oxide, a 50 fF capacitance can be implemented in a 70 μιη by 70 μιη area, which still provides a dense interconnect structure. Table 2. Scenarios and simplified ΔΤ calculations.

[0027] Scenarios 7-9 from Table 2 above employ inductive coupling consistent with embodiments described herein. While full face to face bonding with an oxide gap may create a wide heat path, and limit the thermal isolation capabilities, thermal isolation may be significantly improved if the inductors are stacked using oxide pillars similar to the technique described with respect to FIG. 3, together with a vacuum gap. (Note: as well as ignoring heat spreading, convective heat transfer is also excluded in this simple calculation.)

[0028] Semiconductor packages employing capacitive coupling including a vacuum gap were generally modeled with simulation software such as Ansys. The volume around one bump was modeled to keep the models straightforward. A heat flux of 1 W/mm² was assumed for the first (CPU) chip. The backside of the chip was assumed to be connected to a first cooling path such as a heat sink that permitted application of a surface temperature of 370 K. The second semiconductor chip (DRAM) was modeled to produce a heat flux of 0.005 W/mm². The backside of the DRAM was assumed to be air cooled along a second cooling path to an ambient temperature of 300 K.

[0029] Further modeling parameters included a 50 nm vacuum gap, and an array of 1 μιη cross- sectionally square pillars. The CPU was modeled as operating at 372 K and the DRAM operating at 322 K. Thermal results reflected a thermal differential between the processor chip and the DRAM chip of 47°C, an excellent level of thermal isolation.

[0030] A variety of different thermal simulations were conducted for comparison purposes. A summary of the temperature of the two chips for several different scenarios is provided below in Table 3. It refers to selected cases listed in Table 2. Scenario 1 refers to the direct attach method without a formed gap. In that case, the DRAM was only 8°C cooler than the CPU. Scenario 6 from Table 2 incorporates capacitive coupling with a layer of oxide forming a separation between the devices. The oxide layer disposed between the devices only improves the isolation by an additional 1°C. In contrast, employing a formed vacuum gap in one of the semiconductor devices, and supported by an array of pillars provided an additional 41°C of thermal isolation. Increasing the formed vacuum gap beyond 50 nm provided little additional benefit. Further, the CPU temperature remained constant while the DRAM temperature varied dramatically with the different modeled scenarios.

Table 3

[0031] Table 4 below illustrates different percentages of Si02 fill in various gap embodiments, and the corresponding thermal resistivities exhibited. Generally speaking, the thermal resistivity is proportional, or exhibits a linear relationship to the percentage of Si02 fill within the formed gap.

Table 4

[0032] While a majority of the disclosure herein discusses various thermal isolator embodiments that avoid the costs involved with an interposer or other intervening component, in some circumstances it may be desirable to employ such an intervening device. Conforming the intervening device to include a thermal gap including a vacuum, aerogel, or the like is consistent with the teachings herein.

[0033] Those skilled in the art will appreciate the many benefits and advantages afforded by the embodiments described herein. By employing a formed gap between stacked semiconductor components, together with an AC-coupled signaling interface, significant thermal isolation may be achieved between the devices. By isolating the devices thermally, separate cooling paths may be employed, as needed, to cool each device. This is often more cost-effective than relying on a single cooling path to enhance cooling on one semiconductor device and relying on the reduction to indirectly affect the second device.

[0034] It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer- readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.).

[0035] When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

[0036] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be "asserted" when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be "deasserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be "activated" when a signal is asserted on the signal line, and "deactivated" when the signal is deasserted. Additionally, the prefix symbol "/" attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ) is also used to indicate an active low signal. The term "coupled" is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device "programming" may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term "exemplary" is used to express an example, not a preference or requirement.

[0037] While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS We Claim:

1. A semiconductor package comprising:

a first semiconductor device having a first contactless signaling interface;

a second semiconductor device disposed in a stacked relationship with the first semiconductor device and having a second contactless signaling interface to electrically communicate with the first contactless signaling interface; and

a thermal isolator disposed between the first and second contactless signaling interfaces to inhibit thermal conductivity between the first and second semiconductor devices.

2. The semiconductor package of claim 1 wherein the thermal isolator is formed in the second semiconductor device and comprises a gap disposed proximate the second contactless signaling interface.

3. The semiconductor package of claim 2 wherein the gap receives at least one from the group comprising a vacuum, a gas, or an aerogel.

4. The semiconductor package of claim 2 wherein the second semiconductor device includes spaced- apart parallel oxide layers, and wherein the gap is bounded by the oxide layers.

5. The semiconductor package of claim 4 wherein the second semiconductor device further includes an array of pillars disposed perpendicular to the oxide layers.

6. The semiconductor package of claim 1 wherein the first and second contactless signaling interfaces cooperate to form a capacitively -coupled interface.

7. The semiconductor package of claim 1 wherein the first and second contactless signaling interfaces cooperate to form an inductively-coupled interface.

8. The semiconductor package of claim 1 wherein the thermal isolator comprises an interposer.

9. The semiconductor package of claim 8 wherein the interposer is formed with a thermal gap to receive at least one from the group comprising a vacuum, a gas, or an aerogel.

10. The semiconductor package of claim 1 wherein the second contactless signaling interface is disposed opposite the first contactless signaling interface.

11. The semiconductor package of claim 1 and further including:

a first cooling path disposed in thermal communication with the first semiconductor device to direct thermal conductivity in a direction away from the thermal isolator.

12. The semiconductor package of claim 11 wherein the first cooling path includes a heatsink mounted to a surface of the semiconductor device opposite the first contactless signaling interface.

13. The semiconductor package of claim 11 and further including:

a second cooling path disposed in thermal communication with the second semiconductor device to direct thermal conductivity in a direction away from the thermal isolator.

14. The semiconductor package of claim 13 wherein the second cooling path comprises an air flow path coupled to the surface of the second semiconductor device.

15. The semiconductor package of any of claims 1-14 wherein the first semiconductor device comprises an integrated circuit memory controller and the second semiconductor device comprises an integrated circuit memory device.

16. A semiconductor package comprising: a first semiconductor device formed with a first contactless signaling interface and a first DC- coupled power interface; and

a second semiconductor device disposed in a stacked face-to-face orientation with the first semiconductor device and having a surface formed with a second contactless signaling interface to electrically communicate with the first contactless signaling interface, wherein the second semiconductor device includes a second surface formed with a second DC-coupled power interface.

17. The semiconductor package of claim 16 and further comprising:

a thermal isolator disposed between the first and second contactless interfaces to inhibit thermal conductivity between the first and second devices.

18. The semiconductor package of claim 17 wherein the thermal isolator is formed in the second semiconductor device and comprises a gap disposed proximate the second contactless signaling interface.

19. The semiconductor package of claim 18 wherein the gap receives at least one from the group comprising a vacuum, a gas, or an aerogel.

20. The semiconductor package according to claim 16 wherein the second DC-coupled power interface includes a plurality of through-silicon vias to deliver power to the second semiconductor device.

21. The semiconductor package according to claim 16 wherein the first and second contactless signaling interfaces cooperate to form a capacitively coupled signaling interface.

22. The semiconductor package according to claim 16 wherein the first and second contactless signaling interfaces cooperate to form an inductively coupled signaling interface.

23. A method of operating a stacked semiconductor package, the stacked semiconductor package including first and second semiconductor devices having respective contactless signaling interfaces disposed in a face-to-face relationship, the method comprising:

electrically communicating between the contactless signaling interfaces; and

inhibiting thermal conductivity between the semiconductor devices across the contactless signaling interfaces.

24. The method according to claim 23 wherein electrically communicating between the contactless signaling interfaces comprises:

electrically communicating across a gap disposed between the semiconductor interfaces, and wherein the gap inhibits the thermal conductivity between the semiconductor devices.

25. The method according to claim 24 wherein electrically communicating comprises capacitively coupling the respective signaling interfaces.

26. The method according to claim 24 wherein electrically communicating comprises inductively coupling the respective signaling interfaces.