CN104321866B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN104321866B
CN104321866B CN201280073539.9A CN201280073539A CN104321866B CN 104321866 B CN104321866 B CN 104321866B CN 201280073539 A CN201280073539 A CN 201280073539A CN 104321866 B CN104321866 B CN 104321866B
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chip
semiconductor chip
adhesives
wiring board
semiconductor
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CN201280073539.9A
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CN104321866A (zh
Inventor
绀野顺平
西田隆文
坂田贤治
木下顺弘
杉山道昭
木田刚
小野善宏
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

一种半导体器件的制造方法，在布线衬底上，通过粘接材料分别层叠俯视时的平面尺寸不同的第一半导体芯片和第二半导体芯片，其中，在平面尺寸相对小的第一半导体芯片上搭载平面尺寸相对大的第二半导体芯片。另外，搭载了第一及第二半导体芯片之后，用树脂封固第一及第二半导体芯片。这里，第二半导体芯片和布线衬底的间隙用树脂封固之前，预先通过搭载第一及第二半导体芯片时使用的粘接材料填塞。

Description

半导体器件的制造方法
技术领域
本发明涉及半导体器件及其制造技术，例如，涉及适用于层叠平面尺寸不同的多个半导体芯片而成的半导体器件的有效的技术。
背景技术
日本特开2005-191053号公报(专利文献1)记载了通过倒装芯片连接方式将半导体芯片搭载在封装衬底上的半导体器件的制造方法。专利文献1记载了在封装衬底上通过NCP(Non-Conductive Paste)地配置半导体芯片之后，推压芯片背面将半导体芯片连接在封装衬底上。
另外，在日本特开2010-251408号公报(专利文献2)和日本特开2011-187574号公报(专利文献3)记载了如下半导体器件，在层叠的多个半导体芯片上分别形成贯通电极，通过该贯通电极而使多个半导体芯片电连接。
另外，在日本特开2000-299431号公报(专利文献4)和日本特开2002-26236号公报(专利文献5)记载了以下内容。将第一半导体芯片(第一半导体元件)经由各向异性导电粘接剂(底部填充材料)搭载在电路衬底(衬底)上时，使各向异性导电粘接剂的一部分向第一半导体芯片的外部溢出。而且，在溢出的树脂即支承部及第一半导体芯片的上方经由粘接剂(芯片接合用粘接剂)搭载第二半导体芯片(第二半导体元件)。
现有技术文献
专利文献
专利文献1:日本特开2005-191053号公报
专利文献2:日本特开2010-251408号公报
专利文献3:日本特开2011-187574号公报
专利文献4:日本特开2000-299431号公报
专利文献5:日本特开2002-26236号公报
发明内容
本申请发明人研究了提高将平面尺寸(外形尺寸)不同的多个半导体芯片层叠在布线衬底上的半导体器件的性能的技术。作为其一个环节研究了以下技术：为提高半导体芯片间的传送速度，在多个半导体芯片中的配置在下级侧的半导体芯片上形成贯通电极，通过该贯通电极使多个半导体芯片相互电连接。其结果为，本申请发明人发现了以下问题：在下级侧的半导体芯片的平面尺寸比上级侧的半导体芯片的平面尺寸小的情况下，在半导体器件的可靠性这点产生问题。
其他课题和新的特征能够从本说明书的记载和附图明确。
一实施方式的半导体器件的制造方法包含在布线衬底上配置第一粘接材料之后，在上述布线衬底上搭载第一半导体芯片的工序。另外，半导体器件的制造方法包括在上述半导体芯片的第一背面上及从上述第一半导体芯片露出的上述第一粘接材料的露出面上配置了第二粘接材料之后，在上述第一半导体芯片的上述第一背面上搭载第二半导体芯片的工序。另外，半导体器件的制造方法包含用树脂封固上述第一半导体芯片及上述第二半导体芯片的工序。
这里，上述第一半导体芯片具有第一表面、形成在上述第一表面上的多个第一表面电极、与上述第一表面相反侧的第一背面、形成在第一背面上的多个第一背面电极、及从上述第一表面和上述第一背面中的一方朝向另一方贯穿地形成的多个贯通电极。另外，上述第二半导体芯片的平面尺寸比上述第一半导体芯片的平面尺寸大。另外，上述第二半导体片和上述布线衬底的间隙在被上述第一及第二粘接材料填塞了的状态下进行基于上述树脂的封固。
发明的效果
根据上述一实施方式，能够提高半导体器件的可靠性。
附图说明
图1是一实施方式的半导体器件的立体图。
图2是图1所示的半导体器件的仰视图。
图3是在去除了图1所示的封固体的状态下表示布线衬底上的半导体器件的内部构造的透视俯视图。
图4是沿图1的A-A线的剖视图。
图5是图4所示的A部的放大剖视图。
图6是表示图4所示的存储器芯片的表面侧的俯视图。
图7是表示图6所示的存储器芯片的背面侧的一例的俯视图。
图8是表示图4所示的逻辑芯片的表面侧的俯视图。
图9是表示图8所示的逻辑芯片的背面侧的一例的俯视图。
图10是图4的B部的放大剖视图。
图11是表示使用图1～图10说明的半导体器件的制造工序的概要的说明图。
图12是表示在图11所示的衬底准备工序中准备的布线衬底的整体构造的俯视图。
图13是图12所示的一个器件区域的放大俯视图。
图14是沿图13的A-A线的放大剖视图。
图15是表示图13的相反侧的面的放大俯视图。
图16是表示将粘接材料配置在图13所示的芯片搭载区域中的状态的放大俯视图。
图17是沿图16的A-A线的放大剖视图。
图18是示意地表示具有图7所示的贯通电极的半导体芯片的制造工序的概要的说明图。
图19是示意地表示接着图18的半导体芯片的制造工序的概要的说明图。
图20是表示将逻辑芯片LC搭载在图16所示的布线衬底的芯片搭载区域上的状态的放大俯视图。
图21是沿图20的A-A线的放大剖视图。
图22是表示图11所示的第一芯片搭载工序的详细流程的说明图，是示意地表示将半导体芯片载置在芯片搭载区域上的状态的说明图。
图23是表示图11所示的第一芯片搭载工序的详细流程的说明图，是表示拆下图22所示的输送夹具并将加热夹具压抵在半导体芯片的背面侧的状态的说明图。
图24是表示图11所示的第一芯片搭载工序的详细流程的说明图，是表示将半导体芯片加热并与布线衬底电连接的状态的说明图。
图25是表示将粘接材料配置在图20所示的半导体芯片的背面及其周围的状态的放大俯视图。
图26是沿图25的A-A线的放大剖视图。
图27是示意地表示图4所示的存储器芯片的层叠体的组装工序的概要的说明图。
图28是示意地表示接着图27的存储器芯片的层叠体的组装工序的概要的说明图。
图29是表示将存储器芯片的层叠体搭载在图25所示的逻辑芯片的背面上的状态的放大俯视图。
图30是沿图29的A-A线的放大剖视图。
图31是表示图11所示的第二芯片搭载工序的详细流程的说明图，是示意地表示将存储器芯片的层叠体载置在逻辑芯片上的状态的说明图。
图32是表示图11所示的第二芯片搭载工序的详细流程的说明图，是表示拆下图31所示的输送夹具并将加热夹具压抵在层叠体的背面侧的状态的说明图。
图33是表示图11所示的第二芯片搭载工序的详细流程的说明图，是表示在拆下了图31所示的保持夹具时，层叠体倾斜的状态的说明图。
图34是表示图11所示的第二芯片搭载工序的详细流程的说明图，是表示将层叠体加热并与逻辑芯片电连接的状态的说明图。
图35是表示在图30所示的布线衬底上形成封固体并封固了层叠的多个半导体芯片的状态的放大剖视图。
图36是表示图35所示的封固体的整体构造的俯视图。
图37是表示将图30所示的布线衬底配置在成型封固体的成形模具内的状态的主要部位剖视图。
图38是表示将树脂供给到图37所示的成型模具内的状态的主要部位剖视图。
图39是表示图37所示的成型模具内被树脂填满的状态的主要部位剖视图。
图40是表示从成型模具取出图39所示的布线衬底的状态的主要部位剖视图。
图41是表示将焊球接合在图35所示的布线衬底的多个接合区(land)上的状态的放大剖视图。
图42是表示使图41所示的多件同时加工的布线衬底单片化了的状态的剖视图。
图43是表示图4所示的半导体器件的变形例的概要的主要部位剖视图。
图44是表示图4所示的半导体器件的其他变形例的概要的主要部位剖视图。
图45是表示图44所示的半导体器件的变形例的概要的主要部位剖视图。
图46是图45的A部的放大剖视图。
图47是表示图4所示的半导体器件的其他变形例的概要的主要部位剖视图。
图48是图47的A部的放大剖视图。
图49是表示图4所示的半导体器件的其他变形例的主要部位剖视图。
图50是在与图31～图34不同的研究例中，表示层叠体倾斜的状态的说明图。
图51是表示图39的研究例的主要部位剖视图。
具体实施方式
(本申请的记载方式、基本术语·用法的说明)
在本申请中，实施方式的记载根据需要为方便分成多个章节等来记载，但除了特别明示了不是这样的情况以外，它们不是相互独立的，不论记载的前后，单一例的各部分的一方是另一方的一部分详细说明或者一部分或全部的变形例等。另外，作为原则，同样的部分省略反复的说明。另外，实施方式中的各构成要素除了特别明示了不是这样的情况、理论上限定其数量的情况及从语境明确可知不是这样的情况以外，都不是必须的。
同样地，在实施方式等的记载中，关于材料、组成等，提及“由A构成的X”等，除了特别明示不是这样的情况及从语境明确可知不是这样的情况以外，不能排除包含A以外的要素的情况。例如，关于成分，是“作为主要成分含有A的X”等的意思。例如，提及“硅部件”等，并不限于纯硅，当然还包括以SiGe(硅-锗)合金或其他硅为主要成分的多元合金、和包含其他的添加物等的部件。另外，提及金镀层、Cu层、镍镀层等，除了特别明示不是这样的情况以外，不仅指纯单质，还包括分别以金、Cu、镍等为主要成分的部件。
而且，提及特定的数值、数量时，除了特别明示不是这样的情况、理论上限定该数量的情况及从语境明确可知不是这样的情况以外，也可以是超过该特定数值的数值，还可以是小于该特定数值的数值。
另外，在实施方式的各图中，同一或同样的部分用同一或类似的符号或附图标记表示，作为原则不反复说明。
另外，在附图中，在变得繁琐的情况或与空隙之间的区别是明确的情况下，即使是截面也有省略剖面线等的情况。与其相关联地从说明等能够明确的情况下等，即使是平面上闭合的孔，也有省略背景的轮廓线的情况。而且，为了明示不是截面也不是空隙，或者为了明示区域的边界，有时标注剖面线或点阵图案。
(实施方式)
在本实施方式中，作为层叠多个半导体芯片而成的半导体器件的例子，选出在形成有运算处理电路的半导体芯片上层叠了形成有存储器电路的多个半导体芯片的实施方式进行说明。图1是本实施方式的半导体器件的立体图，图2是图1所示的半导体器件的仰视图。另外，图3是在去除了图1所示的封固体的状态下表示布线衬底上的半导体器件的内部构造的透视俯视图。另外，图4是沿图1的A-A线的剖视图。此外，在图1～图4中，为容易观察，减少了端子数地进行示出，但端子(接合引线2f、接合区2g、焊球5)的数量不限于图1～图4所示的方式。另外，在图3中，为容易观察逻辑芯片LC和存储器芯片MC4的俯视时的位置关系和平面尺寸的不同，用虚线表示逻辑芯片LC的轮廓。
＜半导体器件＞
首先，关于本实施方式的半导体器件1的概要结构，使用图1～图4进行说明。本实施方式的半导体器件1具有布线衬底2、搭载在布线衬底2上的多个半导体芯片3(参照图4)及封固多个半导体芯片3的封固体(树脂体)4。
如图4所示，布线衬底2具有搭载有多个半导体芯片3的上表面(面、主面、芯片搭载面)2a、与上表面2a相反侧的下表面(面、主面、安装面)2b、及配置在上表面2a和下表面2b之间的侧面2c，如图2及图3所示，俯视呈四边形的外形形状。在图2及图3所示的例子中，布线衬底2的平面尺寸(俯视时的尺寸、上表面2a及下表面2b的尺寸、外形尺寸)呈例如一边的长度为14mm左右的正方形。另外，布线衬底2的厚度(高度)，即，图4所示的上表面2a至下表面2b的距离为例如0.3mm～0.5mm左右。
布线衬底2是用于将搭载在上表面2a侧的半导体芯片3和未图示的安装衬底电连接的中介层，并具有电连接上表面2a侧和下表面2b侧的多个布线层(在图4所示的例子中是4层)。在各布线层上，形成有多个布线2d和将多个布线2d之间、及相邻的布线层之间进行绝缘的绝缘层(芯层)2e。另外，布线2d包括：形成在绝缘层2e的上表面或下表面上的布线2d1；沿厚度方向贯穿绝缘层2e地形成的层间导电通路即过孔布线2d2。
另外，在布线衬底2的上表面2a上，形成有与半导体芯片3电连接的端子即多个接合引线(端子、芯片搭载面侧端子、电极)2f。另一方面，在布线衬底2的下表面2b上形成有接合有多个焊球5的多个接合区2g，该焊球5是与未图示的安装衬底电连接的端子，即，半导体器件1的外部连接端子。多个接合引线2f和多个接合区2g经由多个布线2d分别被电连接。此外，与接合引线2f或接合区2g连接的布线2d与接合引线2f或接合区2g一体地形成，从而在图4中，将接合引线2f及接合区2g作为布线2d的一部分表示。
另外，布线衬底2的上表面2a及下表面2b被绝缘膜(阻焊膜)2h、2k覆盖。形成在布线衬底2的上表面2a上的布线2d被绝缘膜2h覆盖。在绝缘膜2h上形成有开口部，在该开口部中，多个接合引线2f的至少一部分(与半导体芯片3的接合部、接合区域)从绝缘膜2h露出。另外，形成在布线衬底2的下表面2b上的布线2d被绝缘膜2k覆盖。在绝缘膜2k上形成有开口部，在该开口部中，多个接合区2g的至少一部分(与焊球5的接合部)从绝缘膜2k露出。
另外，如图4所示，布线衬底2的下表面2b的多个接合区2g上所接合的多个焊球(外部端子、电极、外部电极)5如图2所示地被配置成行列状(阵列状、矩阵状)。另外，虽然在图2中省略了图示，但接合多个焊球5的多个接合区2g(参照图4)也配置成行列状(矩阵状)。像这样，将多个外部端子(焊球5、接合区2g)以行列状配置在布线衬底2的安装面侧的半导体器件称为面阵式的半导体器件。面阵式的半导体器件能够将布线衬底2的安装面(下表面2b)侧作为外部端子的配置空间而有效利用，从而即使外部端子数增大，也能够抑制半导体器件的安装面积的增大，从这点来说是优选的。也就是说，能够节省空间地安装伴随高功能化、高集成化而外部端子数增大的半导体器件。
另外，半导体器件1具有搭载在布线衬底2上的多个半导体芯片3。多个半导体芯片3被层叠在布线衬底2的上表面2a上。另外，多个半导体芯片3分别具有表面(主面、上表面)3a、与表面3a相反侧的背面(主面、下表面)3b、及位于表面3a和背面3b之间的侧面3c，如图3所示，俯视呈四边形的外形形状。像这样，通过层叠多个半导体芯片，即使在使半导体器件1高功能化的情况下，也能够减小安装面积。
在图3及图4所示的例子中，被搭载在最下级(最接近布线衬底2的位置)的半导体芯片3是形成有运算处理电路的逻辑芯片(半导体芯片)LC。另一方面，被搭载在逻辑芯片的上级的半导体芯片3是形成有存储在与逻辑芯片LC之间进行通信的数据的主存储电路(存储电路)的存储器芯片(半导体芯片)MC1、MC2、MC3、MC4。此外，在逻辑芯片LC中，除了形成有上述运算处理电路以外，还形成有控制存储器芯片MC1、MC2、MC3、MC4的主存储电路的动作的控制电路。另外，在逻辑芯片LC中，还形成有例如高速缓冲存储器等容量比上述主存储电路小的存储电路。另外，在逻辑芯片LC中还形成有在与未图示的外部设备之间进行信号的输入输出的外部接口电路。另外，在逻辑芯片LC中还形成有在与内部设备(例如存储器芯片MC1、MC2、MC3、MC4)之间进行信号的输入输出的内部接口电路。
如逻辑芯片LC那样，将某装置或系统的动作所需的电路集成地形成在一个半导体芯片3上的结构称为SoC(System on a Chip)。另外，如半导体器件1那样，将某装置或系统的动作所需的电路集成地形成在一个半导体器件1上的结构称为SIP(System InPackage)。
这里，所需的主存储电路的容量与工作的装置或系统相应地变化。由此，在图4所示的例子中，与作为SoC的逻辑芯片LC相独立地，搭载具有主存储电路的存储器芯片MC1、MC2、MC3、MC4，并电连接逻辑芯片LC和存储器芯片MC1、MC2、MC3、MC4。由此，能够提高逻辑芯片LC及存储器芯片MC1、MC2、MC3、MC4的通用性。此外，在图4中，示出了在一个逻辑芯片LC上层叠了四个存储器芯片MC1、MC2、MC3、MC4的例子，但半导体芯片3的层叠数具有各种各样的变形例。虽然省略了图示，但例如，作为最小限度的结构，能够适用于在一个逻辑芯片LC上搭载一个存储器芯片MC1的变形例。另外，电连接逻辑芯片LC和存储器芯片MC1、MC2、MC3、MC4的方法将在后面详细说明。
如上所述，从提高逻辑芯片LC及存储器芯片MC1、MC2、MC3、MC4的通用性的观点出发，优选逻辑芯片LC及存储器芯片MC1、MC2、MC3、MC4的平面尺寸(俯视时的尺寸、表面3a及背面3b的尺寸、外形尺寸)在能够实现各半导体芯片3的功能的范围内最小化。逻辑芯片LC通过提高电路元件的集成度，能够减小平面尺寸。另一方面，主存储电路的容量和传送速度(例如基于数据总线的宽度的数据传送量)与平面尺寸相应地变化，从而平面尺寸的小型化存在极限。
由此，在图4所示的例子中，存储器芯片MC4的平面尺寸比逻辑芯片LC的平面尺寸大。例如，存储器芯片MC4的平面尺寸是一条边的长度为8mm～10mm左右的四边形，而逻辑芯片LC的平面尺寸是一条边的长度为5mm～6mm左右的四边形。另外，虽然省略了图示，但图4所示的存储器芯片MC1、MC2、MC3的平面尺寸与存储器芯片MC4的平面尺寸相同。
另外，如上所述，在逻辑芯片LC中，形成有在与未图示的外部设备之间进行信号的输入输出的外部接口电路，从而从缩短与外部设备之间的传送距离的观点出发，多个半导体芯片3的层叠顺序优选为将逻辑芯片LC搭载在最下级，即，最接近布线衬底2的位置。也就是说，如半导体器件1那样地，成为在平面尺寸小的半导体芯片3(逻辑芯片LC)上层叠平面尺寸大的半导体芯片3(存储器芯片MC1、MC2、MC3、MC4)的结构。由此，如图4所示，在最下级的半导体芯片3(逻辑芯片LC)的周缘部的外侧的区域中，在上级侧的半导体芯片3(存储器芯片MC1)和布线衬底2的上表面2a之间产生间隙。
在本实施方式中，为填埋该间隙，在上级侧的半导体芯片3(存储器芯片MC1)和布线衬底2的上表面2a之间配置有粘接材料(绝缘性粘接材料)NCL。换言之，上级侧的半导体芯片3(存储器芯片MC1)和布线衬底2的上表面2a之间的间隙通过粘接材料NCL而被填塞。该粘接材料NCL包括：将逻辑芯片LC粘接固定在布线衬底2上的粘接材料(绝缘性粘接材料)NCL1；将存储器芯片MC1粘接固定在逻辑芯片LC上的粘接材料(绝缘性粘接材料)NCL2。
在本实施方式中，如图4所示，粘接材料NCL1的周缘部、尤其是侧面(与逻辑芯片LC的侧面并列的面)被粘接材料NCL2覆盖。而且，如图4所示，粘接材料NCL2以覆盖存储器芯片(至少存储器芯片MC1)的侧面的方式形成角部(fillet)。而且，该粘接材料NCL2的角部的一部分形成在比存储器芯片的周缘部(侧面)更靠外侧(从逻辑芯片LC远离的方向)。另外，粘接材料NCL1、NCL2分别由绝缘性(非导电性)的材料(例如树脂材料)形成。由此，彼此相邻的接合部(逻辑芯片LC和布线衬底2的接合部、逻辑芯片LC和存储器芯片MC1的接合部)之间能够电绝缘。关于通过粘接材料NCL填塞存储器芯片MC1和布线衬底2的上表面2a之间的间隙的详细方法及其效果，在说明后述的半导体器件的制造方法时详细说明。
另外，在图4所示的例子中，在多个存储器芯片MC1、MC2、MC3、MC4之间，配置与封固体4不同的封固体(芯片层叠体用封固体、芯片层叠体用树脂体)6，存储器芯片MC1、MC2、MC3、MC4的层叠体MCS通过封固体6被封固。封固体6以与多个存储器芯片MC1、MC2、MC3、MC4的表面3a及背面3b紧密贴合的方式被埋入，存储器芯片MC1、MC2、MC3、MC4的层叠体MCS通过各半导体芯片3间的接合部及封固体6成为一体。另外，封固体6由绝缘性(非导电性)的材料(例如树脂材料)形成，通过在存储器芯片MC1、MC2、MC3、MC4的各接合部配置封固体6，能够将设置在各接合部的多个电极间电绝缘。但是，如图4所示，存储器芯片MC1、MC2、MC3、MC4的层叠体MCS中的搭载在最下级(最接近逻辑芯片LC的位置)的存储器芯片MC1的表面4a从封固体6露出。另外，如图3及图4所示，存储器芯片MC1、MC2、MC3、MC4的层叠体MCS中的配置在最上级的存储器芯片MC4的背面4b从封固体6露出。
另外，半导体器件1具有封固多个半导体芯片3的封固体4。封固体4具有上表面(面、表面)4a、位于上表面4a的相反侧的下表面(面、背面)4b(参照图4)及位于上表面4a和下表面4b之间的侧面4c，俯视呈四边形的外形形状。在图1所示的例子中，封固体4的平面尺寸(从上表面4a侧俯视时的尺寸、上表面4a的外形尺寸)与布线衬底2的平面尺寸相同，封固体4的侧面4c与布线衬底2的侧面2c相连。另外，在图1所示的例子中，封固体4的平面尺寸(俯视时的尺寸)呈例如一条边的长度为14mm左右的正方形。
封固体4是保护多个半导体芯片3的树脂体，使多个半导体芯片3间及半导体芯片3和布线衬底2紧密贴合地形成封固体4，由此能够抑制对薄的半导体芯片3的损伤。另外，从提高封固体4作为保护部件的功能的观点出发，例如由以下的材料构成。封固体4要求容易与半导体芯片3及布线衬底2紧密贴合且在封固后要求具有一定程度的硬度，从而优选含有例如环氧类树脂等热固化性树脂。另外，为提高固化后的封固体4的功能，例如，优选将硅胶(二氧化硅；SiO2)颗粒等的填料颗粒混合到树脂材料中。例如从抑制形成了封固体4之后的热变形对半导体芯片3的损伤的观点出发，优选调整填料颗粒的混合比例，使半导体芯片3和封固体4的线膨胀系数接近。
＜半导体芯片的详细情况＞
以下，关于图3及图4所示的逻辑芯片LC及存储器芯片MC1、MC2、MC3、MC4的详细情况及各半导体芯片3的电连接方法进行说明。图5是图4所示的A部的放大剖视图。另外，图6是表示图4所示的存储器芯片的表面侧的俯视图，图7是表示图6所示的存储器芯片的背面侧的一例的俯视图。另外，图8是表示图4所示的逻辑芯片的表面侧的俯视图，图9是表示图8所示的逻辑芯片的背面侧的一例的俯视图。另外，图10是图4的B部的放大剖视图。此外，在图5～图9中，为容易观察，减少电极数量地显示，但电极(表面电极3ap、背面电极3bp、贯通电极3tsv)的数量不限于图5～图9所示的方式。另外，在图7中，示出了存储器芯片MC1、MC2、MC3的背面图，但没有形成背面电极3bp的存储器芯片MC4(参照图4)的背面的构造如图3所示，从而省略图示。
本申请发明人研究了提高SIP型的半导体器件的性能的技术，但作为其一个环节，关于使搭载在SIP上的多个半导体芯片间的信号传送速度提高到例如12Gbps(每秒12千兆位)以上的技术进行了研究。作为使搭载在SIP上的多个半导体芯片间的传送速度提高的方法，有增大内部接口的数据总线的宽度而使1次传送的数据量增加的方法(以下，记作总线宽度增大法)。另外，作为其他方法，有使每单位时间的传送次数增加的方法(以下，记作高时钟化)。另外，还有组合上述总线宽度增大法和时钟数增加法来适用的方法。使用图1～图4说明的半导体器件1是通过组合总线宽度增大化和高时钟化来适用而使内部接口的传送速度提高到12Gbps以上的半导体器件。
例如图4所示的存储器芯片MC1、MC2、MC3、MC4分别是具有512bit的数据总线的宽度的所谓宽I/O存储器。详细来说，存储器芯片MC1、MC2、MC3、MC4分别具有4个数据总线的宽度为128bit的通道，合计该4通道的总线宽度时，成为512bit。另外，各通道的每单位时间的传送次数被高时钟化，例如分别成为3Gbps以上。
像这样，组合高时钟化和总线宽度增大法来适用的情况下，需要使大量的数据线高速地工作，从而从减少噪声的影响的观点出发，需要缩短数据的传送距离。因此，如图4所示，逻辑芯片LC和存储器芯片MC1通过配置在逻辑芯片LC和存储器芯片MC1之间的导电性部件被电连接。另外，多个存储器芯片MC1、MC2、MC3、MC4分别通过配置在多个存储器芯片MC1、MC2、MC3、MC4之间的导电性部件被电连接。换言之，在半导体器件1中，在逻辑芯片LC和存储器芯片MC1之间的传送路径上，不含有布线衬底2和未图示的导线(接合导线)。另外，在半导体器件1中，在多个存储器芯片MC1、MC2、MC3、MC4间的传送路径上，不含有布线衬底2和未图示的导线(接合导线)。
在本实施方式中，作为直接连接多个半导体芯片3彼此的方法采用如下技术：形成沿厚度方向贯穿半导体芯片3的贯通电极，通过该贯通电极连接所层叠的半导体芯片3彼此。详细来说，逻辑芯片LC具有形成在表面3a上的多个表面电极(电极、焊垫)3ap、及形成在背面3b上的多个背面电极(电极、焊垫)3bp。另外，逻辑芯片LC具有从表面3a及背面3b中的一方朝向另一方贯穿地形成，并且电连接多个表面电极3ap和多个背面电极3bp的多个贯通电极3tsv。
半导体芯片3所具有的各电路形成在半导体芯片3的表面3a侧。详细来说，半导体芯片3具有例如由硅(Si)构成的半导体衬底(省略图示)，在半导体衬底的主面(元件形成面)上，形成有例如晶体管等的多个半导体元件(省略图示)。在半导体衬底的主面上(表面3a侧)，层叠有具有多个布线和对多个布线间进行绝缘的绝缘膜的布线层(省略图示)。布线层的多个布线分别与多个半导体元件电连接，并构成电路。形成在半导体芯片3的表面3a(参照图3)上的多个表面电极3ap通过设置在半导体衬底和表面3a之间的布线层与半导体元件电连接，构成了电路的一部分。
因此，如图5所示，形成沿厚度方向贯穿半导体芯片3的贯通电极3tsv，通过贯通电极3tsv电连接表面电极3ap和背面电极3bp，由此，能够电连接背面电极3bp和形成在表面3a侧的半导体芯片3的电路。也就是说，如图5所示，若通过凸起电极(导电性部件、凸块电极)7等的导电性部件电连接存储器芯片MC1的表面电极3ap和逻辑芯片LC的背面电极3bp，则存储器芯片MC1的电路和逻辑芯片LC的电路通过贯通电极3tsv被电连接。
在本实施方式中，搭载在存储器芯片MC1和布线衬底2之间的逻辑芯片LC具有多个贯通电极3tsv。由此，通过贯通电极3tsv电连接存储器芯片MC1和逻辑芯片LC，能够从逻辑芯片LC和存储器芯片MC1之间的传送路径排除布线衬底2和未图示的导线(接合导线)。其结果，能够减小逻辑芯片LC和存储器芯片MC1之间的传送路径中的阻抗成分，能够减少因高时钟化而产生的噪声的影响。换言之，在提高了逻辑芯片LC和存储器芯片MC1之间的信号传送速度的情况下，也能够提高传送可靠性。
另外，在图5所示的例子中，在逻辑芯片LC上，层叠有多个存储器芯片MC1、MC2、MC3、MC4，从而在该多个存储器芯片MC1、MC2、MC3、MC4间，也优选提高信号传送速度。因此，在多个存储器芯片MC1、MC2、MC3、MC4中的上下分别配置有半导体芯片3。存储器芯片MC1、MC2、MC3与逻辑芯片LC同样地具有多个贯通电极3tsv。详细来说，存储器芯片MC1、MC2、MC3分别具有形成在表面3a上的多个表面电极(电极、焊垫)3ap、及形成在背面3b上的多个背面电极(电极、焊垫)3bp。另外，存储器芯片MC1、MC2、MC3分别具有从表面3a及背面3b中的一方朝向另一方贯穿地形成，并且电连接多个表面电极3ap和多个背面电极3bp的多个贯通电极3tsv。
因此，与上述逻辑芯片LC的情况同样地，若通过凸起电极(导电性部件、凸块电极)7等的导电性部件电连接存储器芯片MC1、MC2、MC3、MC4中的上级侧的半导体芯片3的表面电极3ap和下级侧的半导体芯片3的背面电极3bp，则所层叠的多个半导体芯片3的电路通过贯通电极3tsv被电连接。
由此，能够从存储器芯片MC1、MC2、MC3、MC4之间的传送路径排除布线衬底2和未图示的导线(接合导线)。其结果，能够减少所层叠的多个存储器芯片MC1、MC2、MC3、MC4之间的传送路径中的阻抗成分，能够减小因高时钟化产生的噪声的影响。换言之，在提高了多个存储器芯片MC1、MC2、MC3、MC4之间的信号传送速度的情况下，也能够提高传送可靠性。
此外，在图5所示的例子中，搭载在最上级的存储器芯片MC4与存储器芯片MC3连接即可，从而虽然可以形成多个表面电极3ap，但没有形成多个背面电极3bp及多个贯通电极3tsv。像这样，搭载在最上级的存储器芯片MC4采用不具有多个背面电极3bp及多个贯通电极3tsv的构造，由此能够简化存储器芯片MC4的制造工序。但是，虽然省略图示，但作为变形例，关于存储器芯片MC4，也与存储器芯片MC1、MC2、MC3同样地，能够采用具有多个背面电极3bp及多个贯通电极3tsv的构造。该情况下，所层叠的多个存储器芯片MC1、MC2、MC3、MC4成为同一构造，由此能够提高制造效率。
另外，被配置在层叠的半导体芯片3之间并电连接上级侧的半导体芯片3的表面电极3ap和下级侧的半导体芯片3的3bp的凸起电极7在图5所示的例子中使用例如以下材料。即，凸起电极7是在形成为柱状(例如圆柱形)的以铜(Cu)为主成分的部件的前端层叠了镍(Ni)膜、焊料(例如SnAg)膜而成的金属部件，通过将前端的焊料膜接合在背面电极3bp上，而被电连接。但是，构成凸起电极7的材料能够在满足电气特性要求或接合强度要求的范围内适用各种变形例。例如，能够将焊料接合在表面电极3ap的露出面上，使该焊料成为凸起电极7。
另外，如图5所示的逻辑芯片LC和存储器芯片MC1、MC2、MC3那样地，具有贯通电极3tsv的半导体芯片3优选为厚度即表面3a和背面3b的分离距离薄(小)。若使半导体芯片3的厚度变薄，则能够缩短贯通电极3tsv的传送距离，从而能够减小阻抗成分，从这点来看是优选的。另外，在半导体衬底的厚度方向上形成开口部(包括通孔及不贯穿的孔)的情况下，孔的深度越深，加工精度越低。换言之，若使半导体芯片3的厚度变薄，则能够提高用于形成贯通电极3tsv的开口部的加工精度。由此，能够使多个贯通电极3tsv的直径(与半导体芯片3的厚度方向正交的方向的长度、宽度)齐整，从而容易控制多个传送路径的阻抗成分。
在图5所示的例子中，逻辑芯片LC的厚度T1比配置在逻辑芯片LC上的多个存储器芯片MC1、MC2、MC3、MC4的层叠体MCS(参照图4)的厚度TA薄。另外，逻辑芯片LC的厚度T1比多个存储器芯片MC1、MC2、MC3、MC4中的搭载在最上级、未形成贯通电极3tsv的存储器芯片MC4的厚度T2薄。例如，逻辑芯片LC的厚度T1为50μm。而存储器芯片MC4的厚度为80μm～100μm左右。另外，多个存储器芯片MC1、MC2、MC3、MC4的层叠体MCS(参照图4)的厚度TA为260μm左右。
如上所述，使半导体芯片3薄型化的情况下，在使半导体芯片3露出的状态下，会担心半导体芯片3损伤。根据本实施方式，如图4所示，使封固体4与多个半导体芯片3紧密贴合而封固。由此，封固体4作为半导体芯片3的保护部件发挥功能，能够抑制半导体芯片3的损伤。也就是说，根据本实施方式，通过利用树脂封固多个半导体芯片3，能够提高半导体器件1的可靠性(耐久性)。
另外，层叠具有贯通电极3tsv的半导体芯片3而成的半导体器件1的情况下，从传送距离缩短的观点出发，优选半导体芯片3和衬底2的间隔也窄。例如，在图5所示的例子中，逻辑芯片LC的表面3a和布线衬底2的上表面2a之间的间隔G1为例如10μm～20μm左右。另外，存储器芯片MC1的表面3a和布线衬底2的上表面2a之间的间隔G2为例如70μm～100μm左右。像这样，在层叠具有贯通电极3tsv的半导体芯片3而成的半导体器件1中，优选通过减小半导体芯片3的厚度及分离距离，实现传送距离的缩短。
另外，在本实施方式中，在表面电极3ap及背面电极3bp的俯视时的布局中，采用能够缩短存储器芯片MC1、MC2、MC3、MC4和逻辑芯片LC之间的传送距离的结构。
如图6所示，存储器芯片MC1、MC2、MC3、MC4所具有的多个表面电极3ap集中地配置在表面3a的中央部。如图7所示，存储器芯片MC1、MC2、MC3所具有的多个表面电极3ap集中地配置在表面3a的中央部。如图5所示，存储器芯片MC1、MC2、MC3、MC4的多个表面电极3ap和存储器芯片MC1、MC2、MC3的多个背面电极3bp分别沿厚度方向配置在重合的位置。
另外，如图8所示，逻辑芯片LC所具有的多个表面电极3ap中的一部分(多个表面电极3ap1)集中地配置在表面3a的中央部。另外，逻辑芯片LC所具有的多个表面电极3ap中的一部分(多个表面电极3ap2)沿着表面3a的边(侧面3c)被配置在表面3a的周缘部。图8所示的多个表面电极3ap中的配置在表面3a的中央部的多个表面电极3ap1通过图5所示的贯通电极3tcv与背面电极3bp电连接。也就是说，多个表面电极3ap1是内部接口用的电极。另一方面，图8所示的多个表面电极3ap中的配置在表面3a的周缘部的多个表面电极3ap2通过图4所示的布线衬底2与未图示的外部设备电连接。详细来说，如图10所示，表面电极3ap2通过凸起电极7及焊料等的接合材料8与接合引线2f电接合。也就是说，多个表面电极3ap2是外部接口用的电极。
从缩短多个半导体芯片3之间的传送距离的观点出发，尤其优选如图5所示地将内部接口用的表面电极3ap和背面电极3bp沿厚度方向配置在重合的位置并通过凸起电极7连接的方式。
另外，如上所述，逻辑芯片LC的平面尺寸比存储器芯片MC1、MC2、MC3、MC4的平面尺寸小。另外，如图3所示，在半导体器件1中，俯视时，以逻辑芯片LC的背面3b的中央部(中央区域)与存储器芯片MC4的中心部(中央区域)重合的方式被配置。也就是说，俯视时，存储器芯片MC4的四个侧面3c配置在比逻辑芯片LC的四个侧面3c更靠外侧。换言之，多个半导体芯片3以存储器芯片MC4的四个侧面3c位于逻辑芯片LC的四个侧面3c和布线衬底2的四个侧面2c之间的方式被层叠并搭载在布线衬底2上。另外，图4所示的存储器芯片MC1、MC2、MC3俯视时被配置在与存储器芯片MC4重合的位置(相同的位置)。
由此，俯视时，存储器芯片MC1、MC2、MC3、MC4的周缘部(表面3a及背面3b的周缘部)被配置在与逻辑芯片LC的外侧的周边区域重合的位置。换言之，在存储器芯片MC1、MC2、MC3、MC4的周缘部和布线衬底2之间，不存在逻辑芯片LC(例如参照图10)。
因此，为将图5所示的各半导体芯片3的内部接口用的表面电极3ap和背面电极3bp沿厚度方向配置在重合的位置，优选将至少内部接口用的表面电极3ap和背面电极3bp配置在沿厚度方向与逻辑芯片LC重合的位置。另外，在逻辑芯片LC的周缘部上，如图8所示，配置有外部接口用的多个表面电极3ap2。因此，在逻辑芯片LC的表面3a上，内部接口用的多个表面电极3ap1优选集中地配置在表面3a的中央部。
另外，如图6所示，在存储器芯片MC1、MC2、MC3、MC4的表面3a侧(详细来说，半导体衬底的主面上)，形成有多个存储器区域(存储电路元件排列区域)MR。在图6所示的例子中，形成有与上述4通道对应的四个存储器区域MR。在各存储器区域MR中以阵列状配置有多个存储器单元(存储电路元件)。这里，如图6所示，若将多个表面电极3ap集中地配置在表面3a的中央部，则能够以包围配置有表面电极组的区域的方式配置4通道量的存储器区域MR。其结果，能够使从各存储器区域MR到表面电极3ap的距离均等。也就是说，由于能够使多个通道的各自的传送距离等长，所以能够减少每个通道的传送速度的误差，从这点来说是优选的。
然而，将集中于图8所示的逻辑芯片LC的表面3a的中央部的表面电极3ap1作为内部接口专用的电极利用的情况下，即使不使表面电极3ap1与图5所示的布线衬底2电连接，也能够发挥功能。但是，如图5所示，将表面电极3ap1的一部分与布线衬底2的接合引线2f电连接的情况下，能够将表面电极3ap1的一部分作为外部接口用的电极利用，从这点来说是优选的。
例如，在存储器芯片MC1、MC2、MC3、MC4中形成有用于驱动未图示的存储器电路的未图示的驱动电路，但作为向该驱动电路供给电源电位(第一基准电位)和基准电位(与第一基准电位不同的第二基准电位，例如接地电位)的端子，考虑利用表面电极3ap1的一部分。通过使信号传送速度高时钟化来提高信号传送速度的情况下，从抑制因瞬间的电压降等导致的动作不稳定的观点出发，优选缩短电源的供给源和消耗电源的电路间的传送距离。因此，若将电源电位或基准电位供给到逻辑芯片LC的表面电极3ap1的一部分，能够缩短直到形成有消耗电源的电路的存储器芯片MC1、MC2、MC3、MC4的驱动电路的距离，从这点来说是优选的。
＜半导体器件的制造方法＞
以下，关于使用图1～图10说明的半导体器件1的制造工序进行说明。半导体器件1根据图11所示的流程被制造。图11是表示使用图1～图10说明的半导体器件的制造工序的概要的说明图。关于各工序的详细情况，使用图12～图42进行如下说明。
＜衬底准备工序＞
首先，在图11所示的衬底准备工序中，准备图12～图15所示的布线衬底20。图12是表示在图11所示的衬底准备工序中准备的布线衬底的整体构造的俯视图，图13是图12所示的一个器件区域的放大俯视图。另外，图14是沿图13的A-A线的放大剖视图。另外，图15是表示图13的相反侧的面的放大俯视图。此外，在图12～图15中，为容易观察，减少端子数地示出，但端子(接合引线2f、接合区2g)的数量不限于图12～图15所示的方式。
如图12所示，本工序中准备的布线衬底20在框部(外框)20b的内侧具有多个器件区域20a。详细来说，多个(在图12中是27个)器件区域20a以行列状配置。多个器件区域20a分别与图1～图4所示的布线衬底2相当。布线衬底20是具有多个器件区域20a和在各器件区域20a之间具有切割线(切割区域)20c的所谓的多件同时加工衬底。像这样，通过使用具有多个器件区域20a的多件同时加工衬底，能够提高制造效率。
另外，如图13及图14所示，在各器件区域20a中，分别形成有使用图4说明的布线衬底2的构成部件。布线衬底20具有上表面2a、上表面2a的相反侧的下表面2b、及电连接上表面2a侧和下表面2b侧的多个布线层(在图4所示的例子中是4层)。在各布线层中，形成有对多个布线2d和多个布线2d间、及相邻的布线层间进行绝缘的绝缘层(芯层)2e。另外，在布线2d中包括形成在绝缘层2e的上表面或下表面上的布线2d1、及沿厚度方向贯穿绝缘层2e地形成的层间导电通路即过孔布线2d2。
另外，如图13所示，布线衬底20的上表面2a包括在图11所示的第一芯片搭载工序中搭载图8所示的逻辑芯片LC的预定区域即芯片搭载区域(芯片搭载部)2p1。芯片搭载区域2p1存在于上表面2a中的器件区域20a的中央部。此外，由于图13示出了芯片搭载区域2p1的位置，所以用双点划线表示芯片搭载区域的轮廓，但芯片搭载区域2p1是如上所述地搭载逻辑芯片LC的预定区域，从而不需要实际能够观察到的边界线。
另外，布线衬底20的上表面2a形成有多个接合引线(端子、芯片搭载面侧端子、电极)2f。接合引线2f是在图11所示的第一芯片搭载工序中与形成在图8所示的逻辑芯片LC的表面3a上的多个表面电极3ap电连接的端子。在本实施方式中，以使逻辑芯片LC的表面3a侧与布线衬底20的上表面2a相对的所谓面朝下安装方式搭载逻辑芯片LC，从而多个接合引线2f的接合部形成在芯片搭载区域2p1的内侧。
另外，布线衬底20的上表面2a通过绝缘膜(阻焊膜)2h被覆盖。在绝缘膜2h上形成有开口部2hw，在该开口部2hw中，多个接合引线2f的至少一部分(与半导体芯片的接合部、接合区域)从绝缘膜2h露出。
另一方面，如图15所示，在布线衬底20的下表面2b上形成有多个接合区2g。布线衬底20的下表面2b通过绝缘膜(阻焊膜)2k被覆盖。在绝缘膜2k上形成有开口部2kw，在该开口部2kw中，多个接合区2g的至少一部分(与焊球5的接合部)从绝缘膜2k露出。
另外，如图14所示，多个接合引线2f和多个接合区2g通过多个布线2d分别被电连接。这些多个布线2d、多个接合引线2f及多个接合区2g等的导体图案例如由以铜(Cu)为主成分的金属材料形成。另外，多个布线2d、多个接合引线2f及多个接合区2g能够通过例如电解电镀法形成。另外，如图14所示，具有4层以上(在图14中是4层)的布线层的布线衬底20能够通过例如增层(build up)工艺形成。
＜第一粘接材料配置工序＞
以下，在图11所示的第一粘接材料配置工序中，如图16及图17所示，在布线衬底20的上表面2a的芯片搭载区域2p1上配置粘接材料NCL1。图16是表示将粘接材料配置在图13所示的芯片搭载区域的状态的放大俯视图，图17是沿图16的A-A线的放大剖视图。此外，图16中示出了芯片搭载区域2p1及芯片搭载区域2p2的位置，从而芯片搭载区域2p1、2p2的轮廓分别用双点划线表示，但芯片搭载区域2p1、2p2分别是搭载逻辑芯片LC及层叠体MCS的预定区域，从而不需要实际能够观察到的边界线。此外，以下，图示了芯片搭载区域2p1、2p2的情况下，同样地不需要实际能够观察到的边界线。
一般来说，实施如下方式，以面朝下安装方式(倒装芯片连接方式)将半导体芯片搭载在布线衬底上的情况下，电连接半导体芯片和布线衬底之后，利用树脂封固连接部分(后注入方式)。该情况下，从配置在半导体芯片和布线衬底之间的间隙附近的喷嘴供给树脂，利用毛细管现象将树脂埋入间隙。
另一方面，在本实施方式中，在后述的第一芯片搭载工序中将逻辑芯片LC(参照图8)搭载在布线衬底20上之前，将粘接材料NCL1配置在芯片搭载区域2p1，以从粘接材料NCL1上方压抵逻辑芯片LC并与布线衬底20电连接的方式(先涂布方式)，搭载逻辑芯片LC。
上述后注入方式的情况下，利用毛细管现象将树脂埋入间隙，从而对于一个器件区域20a来说的处理时间(注入树脂的时间)变长。另一方面，上述先涂布方式的情况下，在逻辑芯片LC的前端(例如，形成在图5或图10所示的凸起电极7的前端上的焊料)和接合引线2f的接合部接触的时刻，粘接材料NCL1已经被埋入布线衬底20和逻辑芯片LC之间。因此，与上述后注入方式相比，能够缩短对于一个器件区域20a来说的处理时间，能够提高制造效率，从这点来说是优选的。
另外，先涂布方式所使用的粘接材料NCL1如上所述地由绝缘性(非导电性)的材料(例如树脂材料)构成。
另外，粘接材料NCL1由通过施加能量而变硬(硬度变高)的树脂材料构成，在本实施方式中，包含例如热固化性树脂。另外，固化前的粘接材料NCL1比图5及图10所示的凸起电极7柔软，通过压抵逻辑芯片LC而变形。
另外，固化前的粘接材料NCL1因处理方法的不同，主要存在以下的两大区别。其一是由被称为NCP(Non-Conductive Paste)的糊状的树脂(绝缘材料糊料)构成，从未图示的喷嘴向芯片搭载区域2p1涂布。其二是由被称为NCF(Non-Conductive Film)的预先成型为薄膜状的树脂(绝缘材料薄膜)构成，直接以薄膜状态向芯片搭载区域2p1输送并粘贴。使用绝缘材料糊料(NCP)的情况下，不需要如绝缘材料薄膜(NCF)那样地粘贴的工序，从而与使用绝缘材料薄膜的情况相比，能够减小对半导体芯片等施加的应力。另一方面，使用绝缘材料薄膜(NCF)的情况下，由于保形性比绝缘材料糊料(NCP)高，所以容易控制配置粘接材料NCL1的范围和厚度。
详细情况在后面说明，但粘接材料NCL1优选控制配置范围和厚度，从而优选使用预先形成为薄膜状的绝缘材料薄膜(NCF)。在图16及图17所示的例子中，示出了将绝缘材料薄膜(NCF)即粘接材料NCL1配置在芯片搭载区域2p1上、与布线衬底20的上表面2a紧密贴合地粘贴的例子。但是，虽然省略图示，但作为变形例，还能够使用绝缘材料糊料(NCP)。
粘接材料NCL1具有在图11所示的第一芯片粘接工序中粘接固定逻辑芯片LC(参照图4)和布线衬底20的固定材料功能。另外，粘接材料NCL1具有通过封固逻辑芯片LC和布线衬底2的接合部来进行保护的封固材料功能。此外，上述封固功能包括：使向逻辑芯片LC和布线衬底2的接合部传递的应力分散并缓和来保护接合部的应力缓和功能。
从满足上述封固材料功能的观点出发，以包围逻辑芯片LC和布线衬底2的接合部的周围的方式配置粘接材料NCL1即可，从而仅在与芯片搭载区域2p1重合的区域配置粘接材料NCL1即可。另外，从提高上述固定材料功能的观点出发，优选使粘接材料NC1的一部分与图10所示的逻辑芯片LC的侧面3c紧密贴合，但如图16所示，不需要大幅度扩大到芯片搭载区域2p1的外侧地配置。
但是，在图16及图17所示的例子中，以覆盖比芯片搭载区域2p1更大的范围的方式配置粘接材料NCL1。图16所示的芯片搭载区域2p2是在图11所示的第二芯片搭载工序中搭载存储器芯片MC1、MC2、MC3、MC4(参照图4)的层叠体MCS(参照图4)的预定区域，内包芯片搭载区域2p1，并且平面尺寸比芯片搭载区域2p1大。在图16所示的例子中，粘接材料NCL1的周缘部被配置在芯片搭载区域2p1的周缘部和芯片搭载区域2p2的周缘部之间，并且配置在与芯片搭载区域2p2的周缘部接近的位置。换言之，粘接材料NCL1以覆盖到芯片搭载区域2p2的周缘部附近的方式被配置。详细来说，在图16所示的例子中，粘接材料NCL1成为与芯片搭载区域NCL1大致相同的平面尺寸。
如上所述，以覆盖比芯片搭载区域2p1更大的范围的方式配置粘接材料NCL1而得到的效果在后述的第二芯片搭载工序及封固工序中详细说明。
＜第一芯片准备工序＞
另外，在图11所示的第一芯片准备工序中，准备图8及图9所示的逻辑芯片LC。图18是示意地表示图7所示的具有贯通电极的半导体芯片的制造工序的概要的说明图。另外，图19是示意地表示接着图18的半导体芯片的制造工序的概要的说明图。此外，在图18及图19中，以贯通电极3tsv及与贯通电极3tsv电连接的背面电极3p的制造方法为中心进行说明，关于贯通电极3tsv以外的各种电路的形成工序省略图示及说明。另外，图18及图19所示的半导体芯片的制造方法除了能够适用于图4所示的逻辑芯片LC以外，还能够适用于存储器芯片MC1、MC2、MC3的制造方法。
首先，作为晶片准备工序，准备图18所示的晶片(半导体衬底)WH。晶片WH是例如由硅(Si)构成的半导体衬底，俯视呈圆形。晶片WH具有半导体元件形成面即表面(主面、上表面)WHs及表面WHs的相反侧的背面(主面、下表面)WHb。另外，晶片WH的厚度比图4所示的逻辑芯片LC和存储器芯片MC1、MC2、MC3的厚度厚，为例如数百μm左右。
然后，作为孔形成工序，形成了用于形成图5所示的贯通电极3tsv的孔(开孔、开口部)3tsh。在图18所示的例子中，将掩膜25配置在晶片WH的表面WHs上，通过实施蚀刻处理形成孔3tsh。此外，图4所示的逻辑芯片LC和存储器芯片MC1、MC2、MC3的半导体元件例如能够在本工序之后且在下一布线层形成工序之前形成。
然后，将例如铜(Cu)等的金属材料埋入孔3tsh内而形成贯通电极3tsv。然后，作为布线层形成工序，在晶片WH的表面WHs上形成布线层(芯片布线层)3d。在本工序中，形成图5和图10所示的多个表面电极3ap，分别电连接多个贯通电极3tsv和多个表面电极3ap。另外，在本工序中，通过布线层3d电连接图4所示的逻辑芯片LC或存储器芯片MC1、MC2、MC3的半导体元件和图5、图10所示的多个表面电极3ap。由此，逻辑芯片LC或存储器芯片MC1、MC2、MC3的半导体元件通过布线层3d被电连接。
然后，作为凸起电极形成工序，在表面电极3ap(参照图5、图10)上形成凸起电极7。另外，在凸起电极7的前端形成焊料层8a。该焊料层8a作为将图5所示的半导体芯片3搭载在布线衬底2或下层的半导体芯片3上时的接合材料发挥功能。
然后，作为图19所示的背面研磨工序，研磨晶片WH的背面WHb(参照图18)侧，使晶片WH的厚度变薄。由此，图5所示的半导体芯片3的背面3b露出。换言之，贯通电极3tsv沿厚度方向贯穿晶片WH。另外，多个贯通电极3tsv在晶片WH的背面3b中从晶片WH露出。在图19所示的例子中，在背面研磨工序中，在通过玻璃板等的支承基材26及保护表面WHs侧的凸起电极7的保护层27支承晶片WH的状态下，使用研磨夹具28进行研磨。
然后，在背面电极形成工序中，在背面3b上形成多个背面电极3bp，并与多个贯通电极3tsv电连接。
然后，作为单片化工序，沿切割线分割晶片WH，得到多个半导体芯片3。然后，根据需要进行检查，能够得到图4所示的半导体芯片3(逻辑芯片LC或存储器芯片MC1、MC2、MC3)。
＜第一芯片搭载工序＞
以下，在图11所示的第一芯片搭载工序中，如图20和图21所示，将逻辑芯片LC搭载在布线衬底2上。图20是表示将逻辑芯片LC搭载在图16所示的布线衬底的芯片搭载区域上的状态的放大俯视图。另外，图21是沿图20的A-A线的放大剖视图。另外，图22～图24是表示图11所示的第一芯片搭载工序的详细流程的说明图。图22是示意地表示将半导体芯片载置在芯片搭载区域上的状态的说明图。图23是表示拆下图22所示的输送夹具并将加热夹具压抵在半导体芯片的背面侧的状态的说明图。另外，图24是表示加热半导体芯片并与布线衬底电连接的状态的说明图。
在本工序中，如图21所示，以逻辑芯片LC的表面3a与布线衬底2的上表面2a相对的方式，通过所谓面朝下安装方式(倒装芯片连接方式)搭载逻辑芯片LC。另外，通过本工序，逻辑芯片LC和布线衬底2被电连接。详细来说，形成在逻辑芯片LC的表面上的多个表面电极3ap和形成在布线衬底2的上表面2a上的多个接合引线2f通过凸起电极7及接合材料8(参照图5、图10)被电连接。以下，关于本工序的详细流程使用图22～图24进行说明。
在本工序中，首先，如图22所示，将逻辑芯片LC(半导体芯片3)配置在布线衬底20的芯片搭载区域2p1上。逻辑芯片LC以背面3b侧被保持夹具30保持的状态被输送到芯片搭载区域2p1上，以表面3a与布线衬底20的上表面2a相对的方式被配置在接合材料NCL1上。保持夹具30具有吸附保持逻辑芯片LC的背面3b的保持面30a，以被保持面30a保持的状态输送逻辑芯片LC。
另外，在逻辑芯片LC的表面3a侧形成有凸起电极7，在凸起电极7的前端形成有焊料层8a。另一方面，在形成在布线衬底20的上表面2a上的接合引线2f的接合部，形成有与凸起电极7电连接的接合材料即焊料层8b。另外，若是在进行加热处理之前，则粘接材料NCL1是固化前的柔软的状态。由此，使保持夹具30接近布线衬底20时，凸起电极7被压入粘接材料NCL1的内部。
然后，如图23所示，将加热夹具31压抵在逻辑芯片LC的背面3b侧，朝向布线衬底20压抵逻辑芯片LC。如上所述，若是在进行加热处理之前，则粘接材料NCL1是固化前的柔软的状态，因此，通过加热夹具31压入逻辑芯片LC时，逻辑芯片LC接近布线衬底20。逻辑芯片LC接近布线衬底20时，形成在逻辑芯片LC的表面3a上的多个凸起电极7的前端(详细来说，焊料层8a)与接合引线2f的接合区域(详细来说焊料层8b)接触。
另外，粘接材料NCL1的厚度(上表面NCL1a和下表面NCL1b之间的距离)至少比凸起电极7的高度(突出高度)、接合引线2f的厚度及接合材料(焊料层8a、8b)的厚度的合计厚。由此，被加热夹具31压入时，逻辑芯片LC的表面3a侧的一部分被埋入粘接材料NCL1。换言之，逻辑芯片LC的侧面3c中的至少表面3a侧的一部分被埋入粘接材料NCL1。从保护逻辑芯片LC和布线衬底20的接合部的观点出发，粘接材料NCL1被埋入逻辑芯片LC和布线衬底20之间即可，但通过将逻辑芯片LC的表面3a侧的一部分埋入粘接材料NCL1，能够在后述的第二芯片搭载工序中，稳定地搭载半导体芯片。详细情况在第二芯片搭载工序中说明。
另外，在逻辑芯片LC中形成有背面电极3bp，从而需要防止柔软的粘接材料NCL1迂回到背面3b侧而覆盖背面电极3bp。因此，如图23所示，优选在加热夹具31和逻辑芯片LC之间隔设比加热夹具31及逻辑芯片LC柔软的部件(低弹性部件)例如树脂薄膜(薄膜)32，利用树脂薄膜32覆盖逻辑芯片LC的背面3b。若隔着树脂薄膜32压抵逻辑芯片LC，则树脂薄膜32与逻辑芯片LC的背面3b紧密贴合，从而即使加厚粘接材料NCL1的厚度，也能够抑制粘接材料NCL1迂回到逻辑芯片LC的背面3b。另外，通过利用树脂薄膜32覆盖配置有粘接材料NCL1的区域整体，能够使粘接材料NCL1的上表面NCL1a平坦。此外，本实施方式的树脂薄膜32由例如氟类树脂构成。
此外，在隔设有树脂薄膜32的状态下压抵加热夹具31时，成为树脂薄膜32咬入逻辑芯片LC的状态。在图23中，容易判断地示出了树脂薄膜32咬入逻辑芯片LC的状态，但只要粘接材料NCL1的上表面NCL1a的高度成为逻辑芯片的背面3b的高度以下，就能够抑制粘接材料NCL1迂回到逻辑芯片LC的背面3b。
然后，如图23所示，在逻辑芯片LC被加热夹具31压抵的状态下，通过加热夹具(热源)31加热逻辑芯片LC及粘接材料NCL1。在逻辑芯片LC和布线衬底20的接合部，图23所示的焊料层8a、8b分别熔融成为一体，由此成为图24所示的接合材料(焊料)8。也就是说，通过加热夹具(热源)31加热逻辑芯片LC，由此，凸起电极7和接合引线2f通过接合材料8被电连接。
另一方面，通过图23所示的加热夹具(热源)31加热粘接材料NCL1，粘接材料NCL1固化。由此，得到在逻辑芯片LC的一部分被埋入的状态下固化的粘接材料NCL1。另外，逻辑芯片LC的背面电极3bp被树脂薄膜32覆盖，从而从固化的粘接材料NCL1露出。此外，能够成为如下实施方式，不需要通过来自加热夹具(热源)31的热量使粘接材料NCL1完全固化，以能够固定逻辑芯片LC的程度使粘接材料NCL1所含有的热固化性树脂的一部分固化(预固化)之后，将布线衬底20向未图示的加热炉输送，使剩余的热固化性树脂固化(正式固化)。直到粘接材料NCL1所含有的热固化性树脂成分整体固化的正式固化处理完成之前，需要时间，但通过加热炉进行正式固化处理，能够提高制造效率。
＜第二粘接材料配置工序＞
以下，在图11所示的第二粘接材料配置工序中，如图25所示，在逻辑芯片LC(半导体芯片3)的背面3b上及从逻辑芯片LC露出的粘接材料NCL1的上表面(表面)NCL1a上，配置有粘接材料NCL2。图25是表示将粘接材料配置在图20所示的半导体芯片的背面及其周围的状态的放大俯视图，图26是沿图25的A-A线的放大剖视图。
如上述图5所示，在本实施方式的半导体器件1中，所层叠的多个半导体芯片3内的搭载在最下级(例如第一级)的逻辑芯片LC、及搭载在从下级开始数的第二级的存储器芯片MC1都以面朝下安装方式(倒装芯片连接方式)搭载。由此，如上述第一粘接材料配置工序中说明的那样，能够缩短对于一个器件区域20a(参照图25、图26)的处理时间，提高制造效率，从这点来说，优选采用上述先涂布方式。
另外，先涂布方式中使用的粘接材料NCL2如上所述地由绝缘性(非导电性)的材料(例如树脂材料)构成。
另外，粘接材料NCL2由通过施加能量而变硬(硬度变高)的树脂材料构成，在本实施方式中，包含例如热固化性树脂。另外，固化前的粘接材料NCL2比图5所示的凸起电极7柔软，通过压抵逻辑芯片LC而变形。
另外，固化前的粘接材料NCL2因处理方法的不同，大致分成被称为NCP的糊状的树脂(绝缘材料糊料)和被称为NCF的预先成型为薄膜状的树脂(绝缘材料薄膜)。作为本工序中使用的粘接材料NCL2，能够使用NCP及NCF的任意一方。在图25及图26所示的例子中，从喷嘴33(参照图26)喷出NCP，在逻辑芯片LC的背面3b上及从逻辑芯片LC露出的粘接材料NCL1的上表面(露出面、表面)NCL1a上配置粘接材料NCL2。
此外，关于从喷嘴33喷出糊状的粘接材料NCL2这点，与上述第一粘接材料配置工序中说明的后注入方式相同。但是，在本实施方式中，在搭载图4所示的存储器芯片MC1之前，预先搭载粘接材料NCL2。因此，与利用毛细管现象注入树脂的后注入方式相比，能够大幅提高粘接材料NCL2的涂布速度。
绝缘材料糊料(NCP)与绝缘材料薄膜(NCF)相比，能够以低荷重与涂布对象物(在本工序中是逻辑芯片LC)紧密贴合。另外，粘接材料NCL2不需要如图3所示地朝向存储器芯片MC4的侧面3c的周围大幅度扩展。因此，与上述第一粘接材料配置工序中说明的NCP1相比，容易控制厚度和配置范围。因此，从减少对于本工序时已经搭载的逻辑芯片LC的应力的观点出发，优选绝缘材料糊料(NCP)。但是，虽然省略图示，但作为变形例，作为粘接材料NCL2还能够使用绝缘材料薄膜(NCF)。
粘接材料NCL2具有在图11所示的第二芯片粘接工序中粘接固定存储器芯片MC1(参照图4)和逻辑芯片LC(参照图4)的固定材料功能。另外，粘接材料NCL2具有通过封固存储器芯片MC1和逻辑芯片LC的接合部来进行保护的封固材料功能。此外，上述封固功能包括：使传递到存储器芯片MC1和逻辑芯片LC的接合部的应力分散并松弛来保护接合部的应力松弛功能。
从满足上述封固材料功能的观点出发，以包围存储器芯片MC1和逻辑芯片LC的接合部的周围的方式配置粘接材料NCL2即可，从而仅在逻辑芯片的背面3b上配置粘接材料NCL2即可。但是，在本实施方式中，如图25所示，除了逻辑芯片的背面3b上以外，还在粘接材料NCL1的上表面NCL1a上配置粘接材料NCL2。像这样，还在粘接材料NCL1的上表面NCL1a上配置粘接材料NCL2，由此，在图11所示的第二芯片搭载工序中搭载存储器芯片MC1、MC2、MC3、MC4(参照图4)的层叠体MCS(参照图4)时，层叠体MCS难以倾斜。
另外，图25所示的芯片搭载区域2p2是在图11所示的第二芯片搭载工序中搭载存储器芯片MC1、MC2、MC3、MC4(参照图4)的层叠体MCS(参照图4)的预定区域。另外，在芯片搭载区域2p2，在图25所示的例子中，沿着俯视呈四边形的芯片搭载区域2p2的对角线以带状涂布粘接材料NCL2。像这样，在粘接材料NCL2的涂布区域中，涂布呈相互交叉的2条带形状的糊状的粘接材料NCL2的方式(称为交叉涂布方式)在后述的第二芯片搭载工序中，容易均等地扩展粘接材料NCL2，从这点来说是优选的。但是，在后述的第二芯片搭载工序中，只要是能够以不产生间隙的方式扩展粘接材料NCL2的方法，还能够使用与图25不同的涂布方法。
另外，粘接材料NCL2的端部被配置在芯片搭载区域2p2的外侧。换言之，在第二粘接材料配置工序中，配置粘接材料NCL2的范围比芯片搭载区域2p2宽。像这样，通过将粘接材料NCL2涂布在比芯片搭载区域2p2宽的范围内，在图11所示的第二芯片搭载工序中，能够如图4所示地填塞存储器芯片MC1的表面3a和布线衬底2的上表面2a之间的间隙。
＜第二芯片准备工序＞
另外，在图11所示的第二芯片准备工序中，准备图4所示的存储器芯片MC1、MC2、MC3、MC4。作为本实施方式的变形例，能够将存储器芯片MC1、MC2、MC3、MC4依次层叠在逻辑芯片LC上。但是，在本实施方式中，关于预先层叠存储器芯片MC1、MC2、MC3、MC4来形成图28所示的层叠体(存储器芯片层叠体、半导体芯片层叠体)MCS的实施方式进行说明。如下所述地形成存储器芯片MC1、MC2、MC3、MC4的层叠体MCS的情况下，例如，能够在与图11所示的第二芯片准备工序以外的工序不同的场所，与其他工序相独立地进行。例如，层叠体MCS还能够作为购买部件准备。由此，能够简化图11所示的组装工序，作为整体能够提高制造效率，从这点来说是有利的。
图27是示意地表示图4所示的存储器芯片的层叠体的组装工序的概要的说明图。另外，图28是示意地表示接着图27的存储器芯片的层叠体的组装工序的概要的说明图。此外，图27及图28所示的多个存储器芯片MC1、MC2、MC3、MC4的各自的制造方法能够采用使用图18及图19说明的半导体芯片的制造方法进行制造，从而省略说明。
首先，作为组装基材准备工序，准备用于组装图28所示的层叠体MCS的基材(组装基材)34。基材34具有层叠多个存储器芯片MC1、MC2、MC3、MC4的组装面34a，在组装面34a上设置有粘接层35。
接着，作为芯片层叠工序，将存储器芯片MC1、MC2、MC3、MC4层叠在基材34的组装面34a上。在图27所示的例子中，以层叠的各半导体芯片的背面3b与基材34的组装面34a相对的方式，按存储器芯片MC4、MC3、MC2、MC1的顺序依次层叠。各半导体芯片的凸起电极7和背面电极3bp通过例如接合材料8被接合。另外，在配置在最上级的存储器芯片MC1的凸起电极7的前端，在图11所示的第二芯片搭载工序中，形成用于电连接图26所示的逻辑芯片LC的背面电极3bp和图27所示的存储器芯片MC1的凸起电极7的接合材料8(例如焊料层8a)。
然后，在图28所示的层叠体封固工序中，在层叠的多个半导体芯片之间，供给树脂(底部填充树脂)，并形成封固体(芯片层叠体用封固体、芯片层叠体用树脂体)6。该封固体6通过上述第一粘接材料配置工序中说明的后注入方式形成。即，预先层叠了多个半导体芯片3之后，从喷嘴36供给底部填充树脂6a，并埋入所层叠的多个半导体芯片3之间。底部填充树脂6a的粘度比图11所示的封固工序中使用的封固用的树脂低，能够利用毛细管现象埋入多个半导体芯片3之间。然后，使埋入半导体芯片3之间的底部填充树脂6a固化并得到封固体6。
以该后注入方式形成封固体6的方法与所谓传递模塑(transfer molding)方式(详细情况在后面说明)相比，间隙的埋入特性优良，从而适用于所层叠的半导体芯片3之间的间隙窄的情况是有效的。另外，如图28所示地多级地形成有埋入底部填充树脂6a的间隙的情况下，能够对于多个间隙一并埋入底部填充树脂6a。由此，作为整体能够缩短处理时间。
然后，在组装基材除去工序中，将基材34及粘接层35从存储器芯片MC4的背面3b剥离并去除。作为去除基材34和粘接层35的方法，能够采用例如使粘接层35所含有的树脂成分(例如紫外线固化树脂)固化的方法。通过以上的工序，层叠了多个存储器芯片MC1、MC2、MC3、MC4，得到各存储器芯片MC1、MC2、MC3、MC4的连接部被封固体6封固的层叠体MCS。该层叠体MCS能够被视为具有形成有多个表面电极3ap的表面3a(存储器芯片MC1的表面3a)及位于表面3a的相反侧的背面3b(存储器芯片MC4的背面3b)的一个存储器芯片。
＜第二芯片搭载工序＞
以下，在图11所示的第二芯片搭载工序中，如图29和图30所示，在逻辑芯片LC上搭载多个存储器芯片MC1、MC2、MC3、MC4的层叠体MCS。图29是表示在图25所示的逻辑芯片的背面上搭载有存储器芯片的层叠体的状态的放大俯视图。另外，图30是沿图29的A-A线的放大剖视图。
在本工序中，如图30所示，以层叠体MCS的表面3a与逻辑芯片LC的背面3b(换言之，布线衬底20的上表面2a)相对的方式，通过所谓面朝下安装方式(倒装芯片连接方式)搭载层叠体MCS。另外，通过本工序电连接多个存储器芯片MC1、MC2、MC3、MC4和逻辑芯片LC。详细来说，如图5所示，形成在存储器芯片MC1(或者，层叠体MCS)的表面3a上的多个表面电极3ap和形成在逻辑芯片LC的背面3b上的多个背面电极3bp通过凸起电极7(及未图示的接合材料)被电连接。此外，在图5中，为容易观察，形成在图27所示的最上级的凸起电极7的前端上的接合材料8省略了图示。以下，关于本工序的详细流程使用图31～图33进行说明。
图31～图34是表示图11所示的第二芯片搭载工序的详细流程的说明图。图31是示意地表示在逻辑芯片上载置存储器芯片的层叠体的状态的说明图。图32是表示拆下图31所示的输送夹具并将加热夹具压抵在层叠体的背面侧的状态的说明图。另外，图33是表示在图31所示的保持夹具拆除时层叠体倾斜的状态的说明图。另外，图34是表示加热层叠体并与逻辑芯片电连接的状态的说明图。另外，图50是表示在与图31～图34不同的研究例中层叠体倾斜的状态的说明图。在图31～图34及图50中，为容易观察，将层叠体MCS视为一个半导体芯片3。
在本工序中，首先，如图31所示，在搭载于布线衬底20的逻辑芯片LC的背面3b上配置层叠体MCS(半导体芯片3)。层叠体MCS在背面3b侧被保持夹具30保持的状态下被输送到芯片搭载区域2p2上，以层叠体MCS的表面3a与逻辑芯片LC的背面3b相对的方式被配置在接合材料NCL2上。保持夹具30能够采用与使用图22说明的第一芯片搭载工序相同的部件。也就是说，保持夹具30具有吸附保持层叠体MCS的背面3b的保持面30a，并以保持面30a保持层叠体MCS的状态进行输送。
另外，在层叠体MCS的表面3a侧形成有凸起电极7，在凸起电极7的前端如使用图27说明形成有焊料层8a(接合材料8)。此外，在图31中，例示性地表示在背面电极3bp的露出面上没有配置接合材料的实施方式，但作为变形例，也可以将未图示的接合材料(例如焊料层)形成在背面电极3bp的露出面上。
另外，该阶段中的粘接材料NCL2是在进行加热处理之前，从而是柔软的状态。由此，配置在逻辑芯片LC上的层叠体MCS的凸起电极7如图31所示地埋入(压入)粘接材料NCL2内。
然后，如图32所示，将加热夹具31压抵在层叠体MCS的背面3b侧，朝向逻辑芯片LC及粘接材料NCL1压抵层叠体MCS。与粘接材料NCL1同样地，在进行加热处理之前，粘接材料NCL2是固化前的柔软的状态，从而通过加热夹具31压入层叠体MCS时，层叠体MCS接近逻辑芯片LC。层叠体MCS接近逻辑芯片LC时，形成在层叠体MCS的表面3a上的多个凸起电极7的前端(详细来说，焊料层8a)与形成在逻辑芯片LC的背面3b上的多个背面电极3bp(或背面电极3bp上的未图示的接合材料)接触。另外，涂布在层叠体MCS和逻辑芯片LC之间的粘接材料NCL2沿着逻辑芯片LC的背面3b及粘接材料NCL1的上表面NCL1a扩展，层叠体MCS和布线衬底2之间的间隙被粘接材料NCL1及粘接材料NCL2填塞。
这里，根据本申请发明人的研究，判明了在平面尺寸小的逻辑芯片LC上搭载平面尺寸大的层叠体MCS(半导体芯片3)的情况下，存在以下课题。即，判明了从图31所示的输送夹具更换成图32所示的加热夹具31时，存在平面尺寸大的层叠体MCS以凸起电极7为基点倾斜的情况。
例如图50所示的变形例那样地，粘接材料NCL1仅被配置在逻辑芯片LC和布线衬底20之间，未扩展到芯片搭载区域2p2的周缘部的情况下，存在层叠体MCS以凸起电极7的位置为基点倾斜的情况。像这样，半导体芯片3倾斜的程度在多个凸起电极7在表面3a上集中地配置在中央部的情况下容易变大。凸起电极7集中地配置在表面3a的中央部时，与配置在表面3a的周缘部的情况相比，层叠体MCS(半导体芯片3)的平衡容易变得不稳定。
另外，层叠体MCS开始倾斜时，倾斜的程度容易增大，直到与其他部件接触。例如在图50所示的例子中，层叠体MCS的表面3a的周缘部成为与布线衬底20的上表面2a接触的状态。层叠体MCS如图50所示地倾斜的情况下，在该倾斜的状态下，即使利用图32所示的加热夹具31推压层叠体MCS，也会发生凸起电极7和背面电极3bp的错位。
因此，在本实施方式中，如图33所示，以将粘接材料NCL1覆盖比芯片搭载区域2p1宽的范围的方式配置粘接材料NCL1。在图33所示的例子中，粘接材料NCL1覆盖到芯片搭载区域2p2的周缘部附近地配置。另外，粘接材料NCL1已经在第二芯片搭载工序之前实施了固化处理，从而比粘接材料NCL2硬。由此，如图33所示，在层叠体MCS的表面3a的周缘部与粘接材料NCL1接触的时刻，能够使倾斜程度的增加停止。换言之，在本实施方式中，以覆盖到芯片搭载区域2p2的周缘部附近的方式配置粘接材料NCL1，由此，在层叠体MCS倾斜的情况下，也能够减少其倾斜的程度。
其结果，如图32所示，若将加热夹具31(及树脂薄膜32)压抵在层叠体MCS上，能够修复层叠体MCS的倾斜。此时，若倾斜的程度小，则能够抑制凸起电极7和背面电极3bp的错位。像这样，通过覆盖搭载层叠体MCS的预定区域即芯片搭载区域2p2的大部分，能够抑制由层叠体MCS倾斜引起的凸起电极7和背面电极3bp的错位。
如上所述，从抑制凸起电极7和背面电极3bp的错位的观点出发，层叠体MCS(半导体芯片3)以凸起电极7为基点倾斜时，优选以层叠体MCS和粘接材料NCL1首先接触的程度的平面尺寸及厚度，形成粘接材料NCL1。详细来说，粘接材料NCL1的周缘部优选被配置在比芯片搭载区域2p1的周缘部更接近芯片搭载区域2p2的周缘部的位置。另外，特别优选以覆盖芯片搭载区域2p2整体的方式配置粘接材料NCL1。另一方面，若粘接材料NCL1的配置范围(粘接材料NCL1的平面尺寸)与芯片搭载区域2p1相比大幅度地增大，则粘接材料NCL1的使用量增加。另外，控制粘接材料NCL2扩展的范围却变得困难。因此，粘接材料NCL1的配置范围(粘接材料NCL1的平面尺寸)特别优选与芯片搭载区域2p2大致相同的大小。
另外，粘接材料NCL1的厚度优选为逻辑芯片LC的侧面3c中的逻辑芯片LC的表面3a侧的一半以上被粘接材料NCL1覆盖的程度的厚度。换言之，优选从截面观察以粘接材料NCL1的上表面NCL1a位于比逻辑芯片LC的侧面3c的中央部(一半的高度)更靠逻辑芯片LC的背面3b侧的方式形成粘接材料NCL1。但是，逻辑芯片LC的背面3b侧被粘接材料NCL1覆盖时，存在电连接背面电极3bp和凸起电极7时成为阻碍的情况。因此，粘接材料NCL1的上表面NCL1a的高度优选在逻辑芯片LC的背面3b以下的范围内尽可能地高。
从这样的观点出发，如上所述，粘接材料NCL1优选使用从容易控制配置范围和厚度的方面来说有利的绝缘材料薄膜(NCF)。
另外，如图32所示，将加热夹具31压抵在层叠体MCS上来扩展粘接材料NCL2的情况下，优选减小施加于逻辑芯片LC的应力。通过扩大固化的粘接材料NCL1的配置范围，能够使施加于逻辑芯片LC的荷重向粘接材料NCL1侧分散。因此，从减少第二芯片搭载工序中的逻辑芯片LC的应力的观点出发，优选扩大固化的粘接材料NCL1的配置范围。
此外，在图32所示的例子中，在层叠体MCS上没有形成背面电极3bp，从而在图32所示的加热夹具31和层叠体MCS之间没有隔设树脂薄膜32的实施方式能够作为变形例使用。但是，在图11所示的第一芯片搭载工序和第二芯片搭载工序中，通过使用相同的搭载装置(保持夹具30、加热夹具31、及树脂薄膜32)，能够抑制制造装置变得繁杂。因此，与第一芯片搭载工序同样地，优选隔着树脂薄膜32地以加热夹具31压抵层叠体MCS。
另外，如图50所示，即使在粘接材料NCL1的配置范围小的情况下，也能够填埋层叠体MCS和布线衬底20的间隙。也就是说，如上所述，若是凸起电极7和背面电极3bp没有错位的情况下，能够将图50所示的实施方式作为变形例使用。该情况下，只要增加粘接材料NCL2的涂布量(配置量)，在配置有粘接材料NCL1的区域的外侧也能够通过粘接材料NCL2填塞层叠体MCS和布线衬底20的间隙。但是，尤其是，在粘接材料NCL2使用绝缘材料糊料(NCP)的情况下，涂布量增加时，进行扩展的范围的控制变得困难。因此，从控制粘接材料NCL2的配置范围并可靠地填塞层叠体MCS和布线衬底20的间隙的观点出发，如图33所示，优选将粘接材料NCL1的周缘部配置比芯片搭载区域2p1的周缘部更靠近芯片搭载区域2p2的周缘部的位置。
然后，如图33所示，在将层叠体MCS压抵在加热夹具31上的状态下，通过加热夹具(热源)31加热逻辑芯片LC及粘接材料NCL2。在层叠体MCS和逻辑芯片LC的接合部上，使图33所示的焊料层8a熔融，对背面电极3bp浸润，由此成为图34所示的接合材料(焊料)8。也就是说，通过加热夹具(热源)31加热层叠体MCS，层叠体MCS的凸起电极7和逻辑芯片LC的背面电极3bp通过接合材料8被电连接。
另一方面，通过图32所示的加热夹具(热源)31加热粘接材料NCL1，由此，粘接材料NCL1固化(预固化)。由此，如图34所示，层叠体MCS和布线衬底20的间隙通过固化的粘接材料NCL1及粘接材料NCL2被填塞。层叠体MCS的侧面3c的表面3a侧的一部分被粘接材料NCL2覆盖。由此，能够提高层叠体MCS和逻辑芯片LC的粘接强度。此外，能够采用如下实施方式，不需要通过来自图32所示的加热夹具(热源)31的热量使粘接材料NCL2完全固化，以能够固定逻辑芯片LC的程度使粘接材料NCL2所含有的热固化性树脂的一部分固化(预固化)之后，将布线衬底20移动到未图示的加热炉，使剩余的热固化性树脂固化(正式固化)。直到粘接材料NCL2所含有的热固化性树脂成分整体固化的正式固化处理完成之前，需要花费时间，但通过利用加热炉进行正式固化处理，能够提高制造效率。
＜封固工序＞
以下，在图11所示的封固工序中，如图35所示，利用树脂封固布线衬底20的上表面2a、逻辑芯片LC及多个存储器芯片MC1、MC2、MC3、MC4的层叠体MCS，形成封固体4。图35是表示在图30所示的布线衬底上形成封固体来封固所层叠的多个半导体芯片的状态的放大剖视图。另外，图36是表示图35所示的封固体的整体构造的俯视图。
在本实施方式中，如图36所示，形成一并地封固多个器件区域20a的封固体4。这样的封固体4的形成方法被称为一并封固(Block Molding)方式，将通过该一并封固方式制造的半导体封装称为MAP(Multi Array Package)型的半导体器件。在一并封固方式中，能够减小各器件区域20a的间隔，从而1张布线衬底20中的有效面积变大。也就是说，能够从1张布线衬底20取得的产品个数增加。像这样，通过增大1张布线衬底20中的有效面积，能够使制造工序高效化。
另外，在本实施方式中，通过将加热软化的树脂压入成型模具内并成型之后，使树脂热固化、即所谓的传递模塑方式形成。通过传递模塑方式形成的封固体4，与例如封固图35所示的层叠体MCS的封固体6那样使液状的树脂固化的情况相比，耐久性高，从而作为保护部件是良好的。另外，例如，将硅胶(二氧化硅；SiO2)颗粒等的填料颗粒混合到热固化性树脂，由此能够提高封固体4的功能(例如，对于翘曲变形的抗性)。以下，关于本工序的详细流程使用图37～图40进行说明。
图37～图40是表示图11所示的封固工序的详细流程的说明图。图37是表示将图30所示的布线衬底配置在成型封固体的成型模具内的状态的主要部位剖视图。另外，图38是表示将树脂供给到图37所示的成型模具内的状态的主要部位剖视图，图39是表示利用树脂填满图37所示的成型模具内的状态的主要部位剖视图。另外，图40是表示从成型模具取出图39所示的布线衬底的状态的主要部位剖视图。另外，图51是表示对于图39的研究例的主要部位剖视图。在图37～图40及图51中，为容易观察，将层叠体MCS视为一个半导体芯片3来表示。
在本工序中，首先，准备图37所示的成型模具40(模具准备工序)。成型模具40是用于成型图35所示的封固体4的模具，设置有具有下表面(模具面)41a及形成在下表面41a上的型腔(凹部、凹陷部)41z的上模具(模具)41。另外，成型模具40设置有具有与上模具41的下表面(模具面)41a相对的上表面(模具面)42a的下模具(模具)42。
型腔41z是俯视呈四棱锥台形的槽(凹陷部)，具有底面及4个侧面。另外，在上模具41上分别形成有树脂4p(参照图38)向型腔41z的供给口即浇口部41g、和配置在与浇口部41g不同的位置(例如相对的位置)的排气部41v。浇口部41g形成在例如型腔41z的一个侧面。另外，排气部41v形成在与浇口部41g不同的型腔41z的侧面。像这样，将浇口部配置在型腔41z的侧面上的方式被称为侧浇口方式。
然后，在成型模具40的下模具42上配置布线衬底20(基材配置工序)。这里，形成在与下模具42组合的上模具41上的型腔41z的面积比布线衬底20的各器件区域20a大，以覆盖多个器件区域20a的方式配置一个型腔41z。换言之，型腔41z的周缘部被配置在布线衬底20的框部20b上。
然后，使上模具41和下模具42的距离接近，并利用上模具41和下模具42夹紧布线衬底20(夹紧工序)。由此，在型腔41z内，在浇口部41g及排气部41v以外的区域，上模具41(上模具41的下表面41a)和布线衬底20的上表面2a紧密贴合。另外，下模具42(下模具42的上表面42a)和布线衬底20的下表面2b紧密贴合。
然后，如图38所示，将树脂4p供给到型腔41z内，通过使其固化，形成封固体4(封固体形成工序)。在本工序中，使配置在未图示的端口部的树脂片加热软化，并从浇口部41g将树脂4p供给到型腔41z内。树脂片以例如热固化性树脂即环氧类的树脂为主成分，在比固化温度低的温度下加热而软化，并具有流动性提高的特性。因此，例如利用未图示的柱塞压入软化的树脂片时，如图38中标注的双点划线的箭头所示，软化的树脂4p从形成在成型模具40上的浇口部41g被压入型腔41z内(详细来说，布线衬底20的上表面2a上)。型腔41z内的气体通过树脂4p流入的压力从排气部41b排出，型腔41z内被树脂4p填满。其结果，搭载在布线衬底20的上表面2a侧的多个半导体芯片3(逻辑芯片LC及层叠体MCS)如图39所示地用树脂4p一并地封固。然后，通过加热型腔41z内，使树脂4p的至少一部分加热固化(预固化)。
这里，根据本申请发明人的研究，发现了：如图51所示，在层叠体MCS和布线衬底20之间存在未被粘接材料NCL1、NCL2填塞的间隙的情况下，从半导体器件的可靠性方面来说，存在以下课题。即，如图51所示判明了，在层叠体MCS和布线衬底20的间隙容易产生未填充树脂4p的气泡(空间)VD。在成品的半导体器件中，在层叠体MCS和布线衬底20之间残留有气泡VD时，热量施加于半导体器件时，封固体容易损坏。也就是说，成为可靠性降低的原因。
本申请发明人对于容易产生上述气泡VD的理由进行了进一步的研究，在将图51所示的逻辑芯片LC置换成图5所示的不具有贯通电极3tsv的半导体芯片的情况下，没有观察到成为可靠性降低的原因的气泡VD的发生。也就是说，判明了：存在容易产生上述气泡VD的现象在将形成有贯通电极3tsv的逻辑芯片LC搭载在下级侧的情况下尤其明显这样的课题。
容易产生气泡VD的原因是考虑到搭载在上级侧的层叠体MCS和布线衬底20的分离距离的关系。未形成贯通电极3tsv的半导体芯片的情况下，由于半导体芯片的厚度和电气特性的关联性低，所以即使是薄的部件，也是100μm左右的厚度。另一方面，如图5所示，形成贯通电极3tsv的逻辑芯片LC的情况下，若使逻辑芯片LC的厚度变薄，则贯通电极3tsv的高度(逻辑芯片LC的厚度方向的长度)变小，从而能够减小连接表面电极3ap和背面电极3bp的导电通路的阻抗。通过减小贯通电极3tsv的高度来提高加工精度，从而能够实现电路的集成化。由此，逻辑芯片LC与不存在贯通电极3tsv的半导体芯片相比，厚度变薄。另外，搭载在逻辑芯片LC上的层叠体MCS和布线衬底2(图51所示的布线衬底20)的分离距离即间隔G2与逻辑芯片LC的厚度T1对应地变小，从而间隔G2也变小。例如，本申请发明人研究的逻辑芯片LC的厚度T1为50μm，间隔G2为70μm～100μm左右。
另外，为将树脂4p埋入层叠体MCS和布线衬底20的间隙，需要以包围下级侧的逻辑芯片LC及其周围的粘接剂NCL1、NCL2的方式使树脂4p迂回，但层叠体MCS和布线衬底20的间隙窄时，静压电阻(电导)变大。尤其是，传递模塑方式中使用的树脂4p(参照图38)与使用图28说明的液态的底部填充树脂6a相比，粘性高，从而难以供给到窄的空间。另外，使树脂4p的供给压力上升时，成为半导体芯片3损伤的原因。
另外，如图51所示，在层叠体MCS和布线衬底20之间存在未被粘接材料NCL1、NCL2填塞的间隙的情况下，存在混合到树脂4p的多个填料颗粒FL中的粒径大的颗粒被夹在间隙的情况。填料颗粒FL被夹在层叠体MCS和布线衬底20之间时，成为填塞树脂4p的通路而产生气泡VD的原因。另外，存在如下情况：填料颗粒FL被压抵在层叠体MCS的表面3a(参照图5)，成为层叠体MCS损伤的原因。
通过使多个填料颗粒FL分散在树脂4p中，能够提高封固体4(参照图35)的功能。但是，填料颗粒FL的粒径是各种各样的，在粒径大的颗粒中，也存在具有例如100μm左右的粒径的填料颗粒FL。由此，存在如下情况：布线衬底20和层叠体MCS的间隔G2(参照图5)变小到70μm～100μm左右时，填料颗粒FL会被夹在布线衬底20和层叠体MCS的间隙。作为防止填料颗粒FL被夹持的现象的方法，考虑预先对混合入树脂4p的填料颗粒FL进行分级来排除粒径大的填料颗粒FL的方法。但是，该情况下，填料颗粒FL的分级作业需要时间。另外，不能使粒径大的填料颗粒FL包含于树脂4p时，材料选择的自由度降低。因此，例如粒径超过80μm的填料颗粒FL包含于树脂4p的情况下，填料颗粒FL不会夹在布线衬底20和层叠体MCS之间，从而是优选的。
因此，在本实施方式中，在封固工序之前，预先利用粘接材料NCL1及粘接材料NCL2填塞层叠体MCS中的不与逻辑芯片LC重合的部分和布线衬底20的上表面2a之间。也就是说，在封固工序之前预先使图51所示的产生气泡VD的区域(间隙)或者容易夹持填料颗粒FL的区域(间隙)不存在。其结果，如图39所示，能够防止或抑制气泡VD(参照图51)的发生。另外，例如粒径超过80μm的填料颗粒FL包含于树脂4p的情况下，也能够不使填料颗粒FL夹在布线衬底20和层叠体MCS之间。
此外，从抑制图51所示的气泡VD的发生和填料颗粒FL对层叠体MCS的损伤的观点出发，布线衬底20和层叠体MCS之间的部件也可以是粘接材料NCL1、NCL2中的任意一方。但是，如上所述，从控制粘接材料NCL1、NCL2的配置位置并可靠地填塞布线衬底20和层叠体MCS的间隙的观点出发，特别优选通过粘接材料NCL1、NCL2双方填塞。也就是说，如使用图16及图17说明的那样，在第一粘接材料配置工序中，优选将粘接材料NCL1的周缘部配置在比芯片搭载区域2p1的周缘部更接近芯片搭载区域2p2的周缘部的位置。另外，在第二粘接材料配置工序中，从减少粘接材料NCL2的涂布量来容易地控制粘接材料NCL2的配置范围的观点出发，粘接材料NCL1的厚度优选为逻辑芯片LC的侧面3c中的逻辑芯片LC的表面3a侧的一半以上被粘接材料NCL1覆盖的程度的厚度。
然后，如图40所示，从上述封固体形成工序中所使用的成型模具40取出形成有封固体4的布线衬底20(衬底取出工序)。在本工序中，使图39所示的上模具41和下模具42分离并取出布线衬底20。
然后，将从成型模具40取出的布线衬底20输送到未图示的加热炉(烘烤炉)，再对布线衬底20进行热处理(烘烤工序、正式固化工序)。在成型模具40内被加热的树脂4p成为树脂中的固化成分的一半以上(例如约70％左右)固化的所谓被称为预固化的状态。在该预固化的状态下，不是树脂4p中的全部的固化成分固化，但一半以上的固化成分固化，在该时刻，半导体芯片3被封固。但是，从封固体4的强度上的稳定性等的观点出发，优选使全部的固化成分完全固化，从而在烘烤工序中，进行使预固化的封固体4再次加热的所谓正式固化。像这样，通过将使树脂4p固化的工序分成两次，对于输送到成型模具40的下一个的布线衬底20迅速地实施封固工序。由此，能够提高制造效率。
另外，如图40所示，在封固体4的周缘部(框部20b上)，残留有浇口部树脂4g及排气部树脂4v。根据需要，若除去浇口部树脂4g及排气部树脂4v，如图36所示，则形成了对于分别搭载在多个器件区域20a的多个半导体芯片3(参照图35)一并地封固的封固体(树脂体)4。但是，浇口部树脂4g及排气部树脂4v是在后述的单片化工序中形成在被去除的框部20b上，能够省略除去它们的工序。
＜焊球安装工序＞
以下，在图11所示的焊球安装工序中，如图41所示，在形成在布线衬底20的下表面2b上的多个接合区2g，接合有成为外部端子的多个焊球5。图41是表示将焊球接合在图35所示的布线衬底的多个接合区上的状态的放大剖视图。
在本工序中，如图41所示地使布线衬底20上下翻转之后，在布线衬底20的下表面2b上露出的多个接合区2g上分别配置焊球5之后，通过加热来接合多个焊球5和接合区2g。根据本工序，多个焊球5通过布线衬底20与多个半导体芯片3(逻辑芯片LC及存储器芯片MC1、MC2、MC3、MC4)电连接。但是，本实施方式中说明的技术不仅仅限于适用于以阵列状接合焊球5的所谓BGA(Ball Grid Array)型的半导体器件。例如，作为本实施方式的变形例，能够适用于不形成焊球5并以使接合区2g露出的状态或将比焊球5薄的焊料糊料涂布在接合区2g上的状态出厂的所谓LGA(Land Grid Array)型的半导体器件。LGA型的半导体器件的情况下，能够省略焊球安装工序。
＜单片化工序＞
以下，在图11所示的单片化工序中，如图42所示，按每个器件区域20a分割布线衬底20。图42是表示使图41所示的多件同时加工布线衬底单片化的状态的剖视图。在本工序中，如图31所示，沿切割线(切割区域)20c切断布线衬底20及封固体4，得到单片化的多个半导体器件1(参照图4)。切断方法没有特别限定，但在图42所示的例子中，示出了如下实施方式，使用切割刀片(旋转刃)45对被粘接固定在带材料(切割胶带)46上的布线衬底20及封固体4，从布线衬底20的下表面2b侧进行切削加工来切断。但是，本实施方式中说明的技术不仅仅限于适用于使用具有多个器件区域20a的作为多件同时加工衬底的布线衬底20的情况。例如，能够适用于在与半导体器件1个量相当的布线衬底2(参照图4)上层叠了多个半导体芯片3的半导体器件。该情况下，能够省略单片化工序。
通过以上的各工序，能够得到使用图1～图10说明的半导体器件1。然后，进行外观检查或电气试验等的必要的检查、试验后，出厂或安装在未图示的安装衬底。
(变形例)
以上，基于实施方式具体说明了本发明人研发的发明，但本发明不限于上述实施方式，当然能够在不脱离其主旨的范围内进行各种变更。
＜变形例1＞
例如，在上述实施方式中，作为从半导体器件的可靠性的观点来说的课题说明了如下隐患：在第二芯片搭载工序中，平面尺寸大的层叠体MCS以凸起电极7为基点倾斜，由此，凸起电极7和背面电极3bp会发生错位。另外，还说明了在封固工序中，在层叠体MCS和布线衬底20的间隙中会形成气泡VD的隐患。另外，还说明了在封固工序中，粒径大(例如比层叠体MCS和布线衬底20的分离距离大)的填料颗粒FL夹在层叠体MCS和布线衬底20的间隙中时，层叠体MCS会损伤的隐患。上述课题是在与半导体器件的可靠性相关的方面是同样的，在比逻辑芯片LC用的芯片搭载区域2p1大的范围内配置粘接材料NCL这点，应对的主要部位是同样的，但为解决各课题的最小限度的结构严密地来说不同。图43及图44是表示上述实施方式中说明的半导体器件1的变形例的概要的主要部位剖视图。
首先，作为解决第二芯片搭载工序中说明的层叠体MCS以凸起电极7为基点倾斜而导致凸起电极7和背面电极3bp错位这一隐患的构造，考虑图43所示的半导体器件50。半导体器件50在层叠体MCS和布线衬底20之间存在间隙这点，与图4所示的半导体器件1不同。另外，半导体器件50在未形成图4所示的封固体4这点，与图4所示的半导体器件1不同。换言之，在半导体器件50的制造方法中，省略了上述实施方式中说明的封固工序。
也就是说，半导体器件50的制造方法的情况下，省略封固工序，从而不会产生封固工序中说明的课题。由此，至少实施抑制层叠体MCS以凸起电极7(参照图33)为基点倾斜的程度的对策即可。由此，层叠体MCS(半导体芯片3)以凸起电极7为基点倾斜时，以层叠体MCS和粘接材料NCL1首先接触的程度的平面尺寸及厚度，形成粘接材料NCL1即可。详细来说，粘接材料NCL1的周缘部被配置在比芯片搭载区域2p1的周缘部更接近芯片搭载区域2p2的周缘部的位置。另外，粘接材料NCL1的厚度如图43所示地优选为逻辑芯片LC的侧面3c中的逻辑芯片LC的表面3a侧的一半以上被粘接材料NCL1覆盖的程度的厚度。换言之，从截面观察，优选以粘接材料NCL1的上表面NCL1a位于比逻辑芯片LC的侧面3c的中央部(一半的高度)更靠逻辑芯片LC的背面3b侧的方式，形成粘接材料NCL1。或者，优选以粘接材料NCL1的上表面NCL1a位于与逻辑芯片LC的背面3b相同的高度的方式形成粘接材料NCL1。但是，从更可靠地抑制层叠体MCS以凸起电极7(参照图33)为基点倾斜的程度的观点出发，粘接材料NCL1优选以覆盖芯片搭载区域2p2的整体的方式配置。另外，在上述第二芯片搭载工序中，从更可靠地抑制半导体芯片2倾斜的观点出发，如使用图33说明的那样，优选以覆盖芯片搭载区域2p2的大部分的方式配置粘接材料NCL1。
另一方面，粘接材料NCL2的配置范围与粘接材料NCL1的配置范围相比，对于层叠体MCS的倾斜的影响更小，因此，如图43所示，能够配置在例如逻辑芯片LC的背面3b。但是，从提高粘接材料NCL2产生的粘接强度的观点出发，如上述实施方式中说明的图32所示，优选在逻辑芯片LC的背面3b及粘接材料NCL1的露出面(从逻辑芯片LC露出的部分的露出表面)上也配置粘接材料NCL2。
＜变形例2＞
以下，作为能够解决封固工序中说明的在层叠体MCS和布线衬底20的间隙形成气泡VD或者在层叠体MCS和布线衬底20的间隙夹着粒径大的填料颗粒FL这样的隐患的构造，考虑图44所示的半导体器件51。半导体器件51在粘接材料NCL1的配置范围成为与芯片搭载区域2p1大致相同的平面尺寸这点，与图4所示的半导体器件1不同。
不考虑上述实施方式中说明的第二芯片搭载工序中的层叠体MCS的倾斜的情况下，在封固工序之前填埋层叠体MCS和布线衬底20的间隙即可，从而能够减小粘接材料NCL1的平面尺寸。例如在图44所示的例子中，粘接材料NCL1的周缘部配置在比芯片搭载区域2p2的周缘部更靠近芯片搭载区域2p1的周缘部的位置。另外，逻辑芯片LC的侧面3c的背面3b侧的一半以上的区域从粘接材料NCL1露出。在半导体器件51这样的结构中，只要在封固工序之前，通过粘接材料NCL2填塞层叠体MCS和布线衬底20的间隙，就能够解决在层叠体MCS和布线衬底20的间隙形成气泡VD或者在层叠体MCS和布线衬底20的间隙夹着粒径大的填料颗粒FL这样的隐患。
但是，如上述实施方式所述，粘接材料NCL2使用绝缘性糊料(NCP)的情况下，粘接材料NCL2尤其会与粘接材料NCL1相仿地扩展。由此，从控制粘接材料NCL2的配置范围并可靠地填塞层叠体MCS和布线衬底20的间隙的观点出发，如图4所示，粘接材料NCL1的周缘部优选配置在比芯片搭载区域2p1的周缘部更接近芯片搭载区域2p2的周缘部的位置。
另外，作为通过粘接材料糊料NCL1解决夹持粒径大的填料颗粒FL这一隐患的构造，如图45及图46所示的半导体器件52那样地，粘接材料糊料NCL1优选覆盖芯片搭载区域2p2的大部分的方式配置。图45是表示图44所示的半导体器件的变形例的概要的主要部位剖视图。另外，图46是图45的A部的放大剖视图。
在图45及图46所示的半导体器件52中，芯片搭载区域2p2的大部分被粘接材料NCL1覆盖。详细来说，如图46所示，芯片搭载区域2p2中的未被粘接材料NCL1覆盖的部分的宽度(图46所示的间隔G3)比多个填料颗粒FL中的体积最大的填料颗粒FL(例如，直径比布线衬底20和层叠体MCS的间隔G2大的填料颗粒)的半径R1小。换言之，层叠体MCS的侧面3c和粘接材料NCL1的周缘部NCL1c直径的间隔G3(俯视时的分离距离或间隙)比多个填料颗粒FL中的体积最大的填料颗粒FL的半径R1小。
半导体器件52的情况下，在上述第二芯片搭载工序中，假设在粘接材料NCL1的周缘部NCL1c未被粘接材料NCL2覆盖的情况下，从能够通过粘接材料NCL1防止或抑制夹持填料颗粒FL这点来说是优选的。另外，在上述第二芯片搭载工序中，粘接材料NCL1的周缘部NCL1c被粘接材料NCL2覆盖的情况下，能够可靠地填塞层叠体MCS和布线衬底20的间隙。
另外，半导体器件52的情况下，芯片搭载区域2p2的一部分未被粘接材料NCL1覆盖，从而容易控制粘接材料NCL2的扩展，从这点来说是优选的。
＜变形例3＞
另外，在上述第二芯片搭载工序中，通过层叠体MCS倾斜，粘接材料NCL1的周缘部和层叠体MCS的表面3a接触，从抑制应力施加于形成在层叠体MCS上的存储器电路的观点来说，优选图47及图48所示的半导体器件53这样的结构。图47是表示图4所示的半导体器件的其他变形例的概要的主要部位剖视图。另外，图48是图47的A部的放大剖视图。
在图47及图48所示的半导体器件53中，在设置在层叠体MCS上的存储器区域MR的周缘部(最接近侧面3c的边)MRc和层叠体MCS的侧面3c之间配置有粘接材料NCL1的侧面NCL1c。
层叠体MCS例如图4所示地具有多个存储器芯片MC1、MC2、MC3、MC4，在各存储器芯片MC1、MC2、MC3、MC4上分别形成有存储器区域MR。此外，存储器区域MR的平面布局如使用图6说明的那样，省略重复的说明。
图47及图48所示的半导体器件53的情况下，俯视时，设置在层叠体MCS上的存储器区域MR的周缘部MRc比粘接材料NCL1的周缘部NCL1c更靠内侧配置。由此，在上述第二芯片搭载工序中，在层叠体MCS倾斜的情况下，存储器区域MR和粘接材料NCL1也变得难以接触。因此，在第二芯片搭载工序中，从能够防止或抑制应力施加于存储器区域MR这点来说是优选的。
＜变形例4＞
另外，半导体器件50、51、52及半导体器件53没有接合图4所示的焊球5，成为多个接合区2g作为外部端子露出的所谓LGA型的半导体器件。该情况下，能够省略上述实施方式中说明的焊球接合工序。
＜变形例5＞
另外，半导体器件50、51、52及半导体器件53能够例如将多个半导体芯片3层叠在与半导体器件1个量相当的布线衬底2上来制造。该情况下，能够省略上述实施方式中说明的单片化工序。
＜变形例6＞
另外，例如，在上述实施方式中，关于将层叠有多个存储器芯片MC1、MC2、MC3、MC4的层叠体MCS搭载在逻辑芯片LC的背面3b上的实施方式进行了说明，但层叠在上级的半导体芯片3的数量没有限定，也可以是例如1片。另外，在将多个半导体芯片3层叠在逻辑芯片LC的背面3b上的情况下，通过反复实施图11所示的第二粘接材料配置工序～第二芯片搭载工序的工序，能够例如图59所示的半导体器件55那样地，通过粘接材料NCL1、NCL2、NCL3、NCL4、NCL5依次层叠多个半导体芯片3。半导体器件55的情况下，由于依次层叠各半导体芯片3，所以组装工序所需的时间变长，但能够不使用图4所示的封固体6地以倒装芯片连接方式层叠多个半导体芯片3。
＜变形例7＞
另外，例如，在上述实施方式及变形例中，关于在与芯片搭载区域2p2相同的范围或者比芯片搭载区域2p2窄的范围内配置粘接材料NCL1的实施方式进行了说明。但是，作为变形例，还能够在比芯片搭载区域2p2大的范围内配置粘接材料NCL1。换言之，能够使粘接材料NCL1的平面尺寸比层叠体MCS的平面尺寸大。该情况下，在第二芯片搭载工序中，能够将粘接材料NCL2粘接在层叠体MCS的侧面3c上，从而容易形成角部。其结果，能够提高层叠体MCS和粘接材料NCL2的粘接强度。
＜变形例8＞
而且，在不脱离上述实施方式中说明的技术思想的主旨的范围内，能够组合变形例彼此地使用。
除此以外，实施方式记载的内容的一部分记载如下。
(1)一种半导体器件具有：
布线衬底，具有第一面、形成在上述第一面上的多个接合引线、与上述第一面相反侧的第二面、及形成在上述第二面且分别与上述多个接合引线电连接的多个接合区；
第一半导体芯片，具有第一表面、形成在上述第一表面上的多个第一表面电极、与上述第一表面相反侧的第一背面、形成在第一背面上的多个第一背面电极、及从上述第一表面和上述第一背面中的一方朝向另一方贯穿地形成且分别电连接上述多个第一表面电极和上述多个第一背面电极的多个贯通电极，以上述第一表面与上述布线衬底的上述第一面相对的方式通过第一粘接材料被搭载在上述布线衬底的上述第一面上；
第二半导体芯片，具有第二表面、形成在上述第二表面上的多个第二表面电极、分别与上述多个第二表面电极电连接的多个凸起电极、及与上述第二表面相反侧的第二背面，以上述第二半导体芯片的上述第二表面与上述第一半导体芯片的上述第一背面相对的方式通过第二粘接材料被搭载在上述第一半导体芯片上，
电连接上述多个第一表面电极和上述多个接合引线，
上述多个第二表面电极和上述多个第一背面电极通过上述多个凸起电极电连接，
上述第二半导体芯片的平面尺寸比上述第一半导体芯片的平面尺寸大，
上述第二半导体芯片被搭载在包含上述第一芯片搭载部且平面尺寸比上述第一芯片搭载部大的第二芯片搭载部上，
上述第一粘接材料的周缘部被配置在比上述第一芯片搭载部的周缘部更接近上述第二芯片搭载部的周缘部的位置。

Claims (17)

1.一种半导体器件的制造方法，其特征在于，包括以下工序：
(a)准备布线衬底的工序，该布线衬底具有第一面、形成在所述第一面上的多个接合引线、与所述第一面相反侧的第二面、及形成在所述第二面上且分别与所述多个接合引线电连接的多个接合区；
(b)将第一粘接材料配置在所述布线衬底的所述第一面上的工序；
(c)在所述(b)工序之后，将第一半导体芯片以所述第一半导体芯片的第一表面与所述布线衬底的所述第一面相对的方式通过所述第一粘接材料搭载在所述布线衬底的所述第一面上，并电连接所述多个接合引线和多个第一表面电极的工序，其中，所述第一半导体芯片具有所述第一表面、形成在所述第一表面上的所述多个第一表面电极、与所述第一表面相反侧的第一背面、形成在第一背面上的多个第一背面电极、及以从所述第一表面和所述第一背面中的一方朝向另一方贯穿的方式分别形成且分别电连接所述多个第一表面电极和所述多个第一背面电极的多个贯通电极；
(d)在所述(c)工序之后，在所述第一半导体芯片的所述第一背面上及从所述第一半导体芯片露出的所述第一粘接材料的表面上，配置第二粘接材料的工序；
(e)在所述(d)工序之后，将第二半导体芯片以所述第二半导体芯片的第二表面与所述第一半导体芯片的所述第一背面相对的方式通过所述第二粘接材料搭载在所述第一半导体芯片上，并电连接所述多个第一背面电极和多个第二表面电极的工序，其中，所述第二半导体芯片具有所述第二表面、形成在所述第二表面上的所述多个第二表面电极、及与所述第二表面相反侧的第二背面；
(f)在所述(e)工序之后，通过树脂封固所述布线衬底的所述第一面、所述第一半导体芯片及所述第二半导体芯片的工序，
其中，
在俯视时，所述第二半导体芯片的尺寸比所述第一半导体芯片的尺寸大，
在所述(e)工序之后且在所述(f)工序之前，所述第二半导体芯片中的与所述第一半导体芯片不重合的部分和所述布线衬底的所述第一面之间被所述第一粘接材料及第二粘接材料填塞。
2.如权利要求1所述的半导体器件的制造方法，其特征在于，
在所述(f)工序中，将所述布线衬底配置在成型模具内，通过将树脂供给到所述成型模具内，封固所述布线衬底的所述第一面、所述第一半导体芯片及所述第二半导体芯片，通过所述成型模具成型所述树脂。
3.如权利要求2所述的半导体器件的制造方法，其特征在于，
所述(c)工序中搭载的所述第一半导体芯片的厚度比所述(e)工序中搭载的所述第二半导体芯片的厚度薄。
4.如权利要求1所述的半导体器件的制造方法，其特征在于，
在所述(e)工序中，在平面尺寸比所述第一半导体芯片所搭载的第一芯片搭载部大的第二芯片搭载部上，搭载所述第二半导体芯片，
在所述(b)工序中，所述第一粘接材料的周缘部被配置在比所述第一芯片搭载部的周缘部更接近所述第二芯片搭载部的周缘部的位置。
5.如权利要求1所述的半导体器件的制造方法，其特征在于，
在所述(f)工序中，封固所述布线衬底的所述第一面、所述第一半导体芯片及所述第二半导体芯片的所述树脂含有多个填料颗粒。
6.如权利要求5所述的半导体器件的制造方法，其特征在于，
所述多个填料颗粒含有粒径比所述第二半导体芯片和所述布线衬底的所述第一面的分离距离大的填料颗粒。
7.如权利要求1所述的半导体器件的制造方法，其特征在于，
在所述(e)工序中，所述第二半导体芯片在所述第一半导体芯片上层叠有多个，
多个所述第二半导体芯片间通过与所述封固体不同的封固体被封固。
8.如权利要求7所述的半导体器件的制造方法，其特征在于，
在所述(f)工序中，封固所述布线衬底的所述第一面、所述第一半导体芯片的所述树脂比封固多个所述第二半导体芯片之间的所述封固体的粘度高。
9.如权利要求1所述的半导体器件的制造方法，其特征在于，
配置在所述布线衬底的所述第一面的第一芯片搭载部上的所述第一粘接材料是薄膜状的粘接材料。
10.如权利要求1所述的半导体器件的制造方法，其特征在于，
在所述(d)工序中，将糊状的所述第二粘接材料朝向所述第一半导体芯片的所述第一背面上及从所述第一半导体芯片露出的所述第一粘接材料的表面上涂布，由此配置所述第二粘接材料。
11.如权利要求1所述的半导体器件的制造方法，其特征在于，
在所述(c)工序中，所述第一半导体芯片的侧面中位于所述第一半导体芯片的所述表面侧的一半以上的侧面，被所述第一粘接材料覆盖。
12.一种半导体器件的制造方法，其特征在于，包括以下工序：
(a)准备布线衬底的工序，该布线衬底具有第一面、形成在所述第一面上的多个接合引线、与所述第一面相反侧的第二面、及形成在所述第二面上且分别与所述多个接合引线电连接的多个接合区；
(b)在所述布线衬底的所述第一面上配置第一粘接材料的工序；
(c)在所述(b)工序之后，将第一半导体芯片以所述第一半导体芯片的第一表面与所述布线衬底的所述第一面相对的方式通过所述第一粘接材料搭载在所述布线衬底的所述第一面上，并电连接所述多个接合引线和多个第一表面电极的工序，其中，所述第一半导体芯片具有所述第一表面、形成在所述第一表面上的所述多个第一表面电极、形成在所述第一表面侧且分别与所述多个第一表面电极电连接的多个第一电路、与所述第一表面相反侧的第一背面、形成在第一背面上的多个第一背面电极、及以从所述第一表面和所述第一背面中的一方朝向另一方贯穿的方式形成且分别电连接所述多个第一表面电极和所述多个第一背面电极的多个贯通电极；
(d)在所述(c)工序之后，在所述第一半导体芯片的所述第一背面上及从所述第一半导体芯片露出的所述第一粘接材料的表面上，配置第二粘接材料的工序；
(e)在所述(d)工序之后，将第二半导体芯片以所述第二半导体芯片的第二表面与所述第一半导体芯片的所述第一背面相对的方式通过所述第二粘接材料搭载在所述第一半导体芯片上，并电连接所述多个第一背面电极和多个第二表面电极的工序，其中，所述第二半导体芯片具有所述第二表面、形成在所述第二表面上的所述多个第二表面电极、形成在所述第二表面侧且分别与所述多个第二表面电极电连接的多个第二电路、及与所述第二表面相反侧的第二背面；
(f)在所述(e)工序之后，通过树脂封固所述布线衬底的所述第一面、所述第一半导体芯片及所述第二半导体芯片的工序，
其中，
在所述多个第二电路中包括存储电路，该存储电路将通过设置在所述第一半导体芯片和所述第二半导体芯片之间的多个第一凸起电极而在与所述第一半导体芯片之间进行通信的数据存储，
在所述多个第一电路中包括控制电路，该控制电路通过设置在所述第一半导体芯片和所述第二半导体芯片之间的多个第二凸起电极而控制所述第二半导体芯片的所述存储电路的动作，
在俯视时，所述第二半导体芯片的尺寸比所述第一半导体芯片的尺寸大，
在所述(e)工序之后且在所述(f)工序之前，所述第二半导体芯片中的与所述第一半导体芯片不重合的部分和所述布线衬底的所述第一面之间被所述第一粘接材料及第二粘接材料填塞。
13.一种半导体器件的制造方法，其特征在于，包括以下工序：
(a)准备布线衬底的工序，该布线衬底具有第一面、形成在所述第一面上的多个接合引线、与所述第一面相反侧的第二面、及形成在所述第二面上且分别与所述多个接合引线电连接的多个接合区；
(b)在所述布线衬底的所述第一面的第一芯片搭载部上配置第一粘接材料的工序；
(c)在所述(b)工序之后，将第一半导体芯片以所述第一半导体芯片的第一表面与所述布线衬底的所述第一面相对的方式搭载在所述布线衬底的所述第一芯片搭载部，并电连接所述多个接合引线和多个第一表面电极的工序，其中，所述第一半导体芯片具有所述第一表面、形成在所述第一表面上的所述多个第一表面电极、与所述第一表面相反侧的第一背面、形成在第一背面上的多个第一背面电极、及以从所述第一表面和所述第一背面中的一方朝向另一方贯穿的方式形成且分别电连接所述多个第一表面电极和所述多个第一背面电极的多个贯通电极；
(d)在所述(c)工序之后，在所述第一半导体芯片的所述第一背面上，配置第二粘接材料的工序；
(e)在所述(d)工序之后，将第二半导体芯片以所述第二半导体芯片的第二表面与所述第一半导体芯片的所述第一背面相对的方式通过所述第二粘接材料搭载在所述第一半导体芯片上，并电连接所述多个第一背面电极和多个第二表面电极的工序，其中，所述第二半导体芯片具有所述第二表面、形成在所述第二表面上的所述多个第二表面电极、分别与所述多个第二表面电极电连接的多个凸起电极、及与所述第二表面相反侧的第二背面，
其中，
在俯视时，所述第二半导体芯片的尺寸比所述第一半导体芯片的尺寸大，
在所述(e)工序中，在包含所述第一芯片搭载部且平面尺寸比所述第一芯片搭载部大的第二芯片搭载部上搭载所述第二半导体芯片，
在所述(b)工序中，所述第一粘接材料的周缘部被配置在比所述第一芯片搭载部的周缘部更接近所述第二芯片搭载部的周缘部的位置。
14.如权利要求13所述的半导体器件的制造方法，其特征在于，
在所述(c)工序中，所述第一半导体芯片的侧面中位于所述第一半导体芯片的所述表面侧的一半以上的侧面，通过所述第一粘接材料被覆盖。
15.如权利要求13所述的半导体器件的制造方法，其特征在于，
在所述(b)工序中，所述第一粘接材料的周缘部被配置在所述第一芯片搭载部的周缘部和所述第二芯片搭载部的周缘部之间。
16.如权利要求13所述的半导体器件的制造方法，其特征在于，
在所述(c)工序之后且在所述(d)工序之前，包含使所述第一粘接材料固化的工序。
17.如权利要求13所述的半导体器件的制造方法，其特征在于，
在所述(b)工序中，所述第一粘接材料以覆盖所述第二芯片搭载部整体的方式配置。
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