CN107808880A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN107808880A
CN107808880A CN201710054525.7A CN201710054525A CN107808880A CN 107808880 A CN107808880 A CN 107808880A CN 201710054525 A CN201710054525 A CN 201710054525A CN 107808880 A CN107808880 A CN 107808880A
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China
Prior art keywords
semiconductor chip
chip
face
manufacture method
semiconductor device
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CN201710054525.7A
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CN107808880B (zh
Inventor
唐金祐次
福田昌利
本间庄
本间庄一
小牟田直幸
尾山幸史
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明提供一种更高效地以树脂密封半导体芯片积层体的半导体装置的制造方法。所述半导体装置的制造方法是在具有第1凸块电极的第1半导体芯片的第1面上，使具有第2凸块电极及第1贯通电极的第2半导体芯片以所述第1凸块电极与所述第1贯通电极重叠的方式积层，在所述第2半导体芯片上，使具有第2贯通电极的第3半导体芯片以所述第2凸块电极与所述第2贯通电极重叠的方式积层而形成芯片积层体，将所述芯片积层体的所述第1及第2凸块电极利用回流焊机械连接于所述第1及第2贯通电极，在具有第2面的第1衬底上，以所述第1面朝向所述第2面侧的方式搭载所述芯片积层体，将所述第2面上及所述第1、第2及第3半导体芯片间树脂密封。

Description

半导体装置的制造方法
相关申请
本申请享有以日本专利申请2016-176671号(申请日：2016年9月9日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置的制造方法。
背景技术
在NAND(NOR-AND：与非)型闪存等要求高容量的器件中，提出有将半导体芯片多段积层并树脂密封的方法。关于各半导体芯片，为使信号提取的传递速度更高速化，而基于TSV(Through Silicon VIA：硅穿孔)方式的积层方式受到关注。
发明内容
本发明的实施方式提供一种更高效地以树脂密封半导体芯片积层体的半导体装置的制造方法。
实施方式的半导体装置的制造方法是在具有第1凸块电极的第1半导体芯片的第1面上，使具有第2凸块电极及第1贯通电极的第2半导体芯片以所述第1凸块电极与所述第1贯通电极重叠的方式积层，在所述第2半导体芯片上，使具有第2贯通电极的第3半导体芯片以所述第2凸块电极与所述第2贯通电极重叠的方式积层而形成芯片积层体，将所述芯片积层体的所述第1及第2凸块电极利用回流焊机械连接于所述第1及第2贯通电极，在具有第2面的第1衬底上，以所述第1面朝向所述第2面侧的方式搭载所述芯片积层体，将所述第2面上及所述第1、第2及第3半导体芯片间树脂密封。
附图说明
图1是表示第1实施方式的半导体装置的构成的剖视图。
图2是表示第1实施方式的半导体装置的构成的剖视图。
图3(a)及(b)是说明第1实施方式的半导体装置的制造方法的图。
图4(a)及(b)是说明第1实施方式的半导体装置的制造方法的图。
图5是说明第1实施方式的半导体装置的制造方法的图。
图6是说明第1实施方式的半导体装置的制造方法的图。
图7是说明第1实施方式的半导体装置的制造方法的图。
图8是表示第2实施方式的半导体装置的构成的图。
图9(a)及(b)是说明第2实施方式的半导体装置的制造方法的图。
图10(a)及(b)是说明第2实施方式的半导体装置的制造方法的图。
具体实施方式
(第1实施方式)
以下，参照图1至图7对第1实施方式的半导体装置进行说明。另外，在以下的附图的记载中，对相同的部分以相同的符号表示。但是，附图为示意性图，厚度与平面尺寸的关系、比率等与实物不同。
图1是表示第1实施方式的半导体装置的构成的剖视图。如图1所示，本实施方式的半导体装置具备包含支撑衬底1、半导体芯片2、贯通电极3、半导体芯片4(逻辑LSI(Large-scale integrated circuit：大规模集成电路))及金属凸块5的芯片积层体、配线衬底6以及树脂模具7。
本实施方式的半导体装置是在配线衬底6上倒装连接包含支撑衬底1及半导体芯片2的芯片积层体，并以树脂模塑包含半导体芯片2间的配线衬底6上的芯片积层体。
支撑衬底1具有与配线衬底6对向的第1面1a及作为第1面1a的相反面的第2面1b。在支撑衬底1的第1面1a，经由粘接剂11粘接着半导体芯片2-1。
支撑衬底1使用例如引线框架等金属板、硅衬底或膜材料等。粘接剂11包含例如芯片粘接薄膜(die attach film)。
在半导体芯片2-1的支撑衬底1的相反面，形成多个金属凸块5，金属凸块5电连接于形成在半导体芯片2-2的贯通电极3。此外，同样地，半导体芯片2-2的贯通电极3经由金属凸块5电连接于形成在半导体芯片2-3的贯通电极3。在半导体芯片2-3的配线衬底6侧的面上形成着未图示的再配线。半导体芯片2-3的贯通电极3经由金属凸块5而与半导体芯片4电连接。将支撑衬底1、半导体芯片2及半导体芯片4合并制成芯片积层体。
半导体芯片2包含例如NAND型闪存等存储器芯片。半导体芯片2、4可使用硅衬底、SiC或GaN等衬底等，并不特别限定。
设置在半导体芯片2-2、2-3的贯通电极(Through Silicon Via：TSV)3向半导体芯片2-1、2-2传送电位或信号。
半导体芯片2与共通的半导体芯片4并联连接(总线连接)。也就是说，对利用贯通电极3在芯片积层方向形成的共通的数据总线，并联连接着多条半导体芯片2的数据输入输出线。
金属凸块5例如使用Au、Ni、Cu、Sn、Bi、Zn、In或其合金。此外，也可取代金属凸块而使用包含Au、Ni、Cu、Al、Pd或其合金的电极垫。
本实施方式的半导体芯片2的数量例如显示有3个，但是半导体芯片2的数量并不特别限定。此外，金属凸块5的个数也不特别限定。
配线衬底6具有树脂制的绝缘层61及金属制的配线层62。绝缘层61具有核心层与增层。在配线衬底6上，以相对于配线衬底6而言半导体芯片4最近、支撑衬底1最远的方式搭载芯片积层体。
例如在图1中，配线衬底6具有作为芯片积层体的搭载面的第1面6a及作为第1面6a的相反面的第2面6b。在配线衬底6的第2面6b形成着外部连接端子9。在将半导体装置用作BGA(Ball Grid Array：球栅阵列)封装的情况下，外部连接端子9使用具有焊球、焊料镀覆、镀Au等的突起端子。在将半导体装置用作LGA(Land Grid Array：焊盘栅格阵列)封包的情况下，外部连接端子9使用金属垫。
在配线衬底6的第1面6a设置内部连接端子10。内部连接端子10例如经由焊料凸块8等连接于设置在除去半导体芯片4后的芯片积层体的最下段的半导体芯片2-3的第1面6a侧的面上的电极垫2-3a。内部连接端子10在与芯片积层体连接时作为连接部(连接垫)发挥功能，且经由配线衬底6的配线网而与外部连接端子9电连接。
位于配线衬底6的第1面6a上的芯片积层体、金属凸块5及焊料凸块8整体以树脂模具7覆盖而密封。
另外，如图2所示，也可在半导体芯片2及4间设置粘接剂12，以及在配线衬底6与芯片积层体之间设置粘接剂13。由此，半导体芯片2间、以及配线衬底6与芯片积层体的连接变得牢固，而能够减少偏移。
接下来，对本实施方式的半导体装置的制造方法进行说明。
图3至图7是依制造工序顺序表示本实施方式的半导体装置的制造方法的剖视图。
如图3(a)所示，在形成有金属凸块5的半导体芯片2-1的与形成着金属凸块5的面(第1面)为相反侧的面上设置粘接剂11，而使该半导体芯片2-1粘接于支撑衬底1的第1面1a。
接着，如图3(b)所示，将预先形成有贯通电极3且具有金属凸块5的半导体芯片2-2积层在半导体芯片2-1上。贯通电极3的形成例如是利用BSV(Back Side VIA：背侧穿孔)方式的晶片工艺而进行。另外，所谓BSV方式是指如下方法：在衬底正面形成具有半导体元件与配线的LSI及表电极，且从衬底背面朝向配线形成孔洞，在孔洞内埋入金属，由此形成TSV。
此处，以形成在半导体芯片2-2的贯通电极3与形成在半导体芯片2-1的金属凸块5沿相对于支撑衬底1大致垂直的Z轴上下重叠的方式积层。以相同方式将具有贯通电极3的半导体芯片2-3积层在半导体芯片2-2上(图4(a))。在半导体芯片2-3的例如与半导体芯片2-2为相反侧的面上具有再配线(未图示)与电极垫2-3a。另外，在半导体芯片2的积层中，也可使用如下方法：不在半导体芯片2-1预先形成金属凸块5，而在半导体芯片2-2及2-3的支撑衬底1侧的面上预先形成金属凸块5，并像上述那样积层。
接着，如图4(b)所示，将形成着金属凸块5的半导体芯片4积层在半导体芯片2-3上。此时，以例如金属凸块5位于半导体芯片2-3的贯通电极3上的方式搭载。另外，也可在半导体芯片2-3的与配线衬底6对向的面上形成再配线。在此情况下，在再配线上搭载金属凸块5。以此方式完成芯片积层体。
在所述的芯片积层体中，在使各个半导体芯片2积层时的温度小于金属凸块5的熔融温度下进行，由此使半导体芯片间不机械连接。由此，在积层半导体芯片时，能够减少因为反复进行金属凸块5的熔融或凝固而导致金属凸块5变脆，从而致使半导体芯片2的连接部断裂的担忧。
另外，因为像所述那样在制造中途不将半导体芯片2间的金属凸块5机械连接，所以有如下担忧，即，在制造工序中，在半导体芯片2的上下重叠的金属凸块5彼此产生位置偏移。因此，为防止位置偏移，理想的是在积层所有半导体芯片而形成芯片积层体后且进行树脂密封之前，进行芯片积层体的还原回流焊。此外，也可使用如图2所示那样预先在半导体芯片2的表面形成粘接剂(具有粘接性的树脂)12，使用粘接剂12使半导体芯片之间固定的方法。
接着，如图5所示，在具有配线的配线衬底6的第1面6a的内部连接端子10上形成焊料凸块8，且将像所述那样制造的芯片积层体倒装安装在第1面6a。此时，使形成在半导体芯片2-3的电极垫2-3a与配线衬底6上的焊料凸块8与配线衬底6重叠。此外，也可在倒装安装时的温度小于形成在配线衬底6的焊料凸块8的熔融温度下进行。
另外，也可使用如下方法：在安装芯片积层体之前，在配线衬底6上预先形成粘接剂13，如图2所示那样使芯片积层体与配线衬底6固定。
接着，将搭载着芯片积层体的配线衬底6在还原气氛中加热，而使半导体芯片的金属凸块5及配线衬底6的焊料凸块8熔融。由此，使半导体芯片2之间及芯片积层体与配线衬底6电连接。
接着，如图6所示，将包含半导体芯片2之间及芯片积层体与配线衬底6之间在内的配线衬底6上利用传递模塑以树脂模具7统一密封。
如图7所示，在配线衬底6的第2面6b形成外部连接端子9。最后，将半导体装置进行分段(切割)(未图示)。
以如上所述的方式完成本实施方式的半导体装置。
根据本实施方式的半导体装置的制造方法，在形成芯片积层体后，无需以底部填充剂等一次在芯片间填充树脂，可利用传递模塑统一将整体树脂密封。因此能够削减工序数。
此外，在形成芯片积层体时，因为在将所有半导体芯片积层之后通过曝露在还原气氛中而一次使金属凸块与贯通电极连接，所以能够减少因为反复进行金属凸块的熔融及凝固而导致金属凸块变脆，从而致使半导体芯片的连接部断裂的担忧。
(第2实施方式)
接下来，一边参照图8及图9一边对第2实施方式进行说明。
第2实施方式与第1实施方式相比，不同点在于不使用支撑衬底，除此以外与第1实施方式相同。
图8是表示第2实施方式的半导体装置的构成的剖视图。如图8所示，本实施方式的半导体装置与第1实施方式相比不使用支撑衬底。也就是说，配线衬底上的芯片积层体的最上段成为半导体芯片2-1。另外，其他构成因为与第1实施方式相同所以省略其说明。
第2实施方式的半导体装置的制造方法是如图9(a)所示那样在预先形成有金属凸块5的半导体芯片2-1上，积层预先形成有贯通电极3及金属凸块5的半导体芯片2-2。此时，在相对于半导体芯片2-1大致垂直的Z轴方向上，以半导体芯片2-1的金属凸块5与半导体芯片2-2的贯通电极3的位置重叠的方式积层。随后的工序因为与第1实施方式相同所以省略说明。另外，也可如图9(b)所示，在半导体芯片2及4间、以及芯片积层体与配线衬底6之间使用粘接剂12、13。
以上，根据本实施方式的半导体装置，具有与第1实施方式相同的效果，且进而与第1实施方式相比能够不使用支撑衬底而形成芯片积层体，所以能够削减工序数及费用。
接下来，一边参照图10一边对第2实施方式的另一制造方法进行说明。
另一制造方法与第2实施方式的制造方法相比，不同点在于使用胶带材料。另外，除此以外与第2实施方式相同。
如图10(a)所示，准备具有粘接性的胶带材料100，在其之上粘接形成有金属凸块的半导体芯片2-1。胶带材料100例如只要单面具有粘接性，那么其形状或材质不限。随后，与第2实施方式同样地形成芯片积层体。在将芯片积层体的金属凸块利用还原气氛等电连接之后，使胶带材料100从芯片积层体剥离。胶带材料100的剥离使用例如拾取工具A及吸附工具B等。
在图10(b)中示出了使用拾取工具A及吸附工具B的胶带材料100的剥离方法。利用拾取工具A，将芯片积层体顶起，同时利用吸附工具B吸附芯片积层体的半导体芯片4，由此能够使胶带材料100从芯片积层体剥离。另外，此时所吸附的半导体芯片也可为半导体芯片2。随后的制造方法正如第2实施方式所示那样。
以上，根据本实施方式的半导体装置的另一制造方法，具有与第1实施方式相同的效果，且进而与第1实施方式相比于后剥离胶带材料，所以能够削减半导体装置的面积。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为例子而提出，并不意图限定发明的范围。这些新颖的实施方式能以其他多种方式实施，可以在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 支撑衬底
1a、6a 第1面
1b、6b 第2面
2 半导体芯片
3 贯通电极
4 半导体芯片(逻辑LSI)
5 金属凸块
6 配线衬底
7 树脂模具
8 焊料凸块
9 外部连接端子
10 内部连接端子
11、12、13 粘接剂
61 绝缘层
62 配线层
100 胶带材料

Claims (9)

1.一种半导体装置的制造方法，在具有第1凸块电极的第1半导体芯片的第1面上，使具有第2凸块电极及第1贯通电极的第2半导体芯片以所述第1凸块电极与所述第1贯通电极重叠的方式积层；
在所述第2半导体芯片上，使具有第2贯通电极的第3半导体芯片以所述第2凸块电极与所述第2贯通电极重叠的方式积层而形成芯片积层体；
将所述芯片积层体的所述第1及第2凸块电极利用回流焊机械连接于所述第1及第2贯通电极；
在具有第2面的第1衬底上，以所述第1面朝向所述第2面侧的方式搭载所述芯片积层体；
将所述第2面上及所述第1、第2及第3半导体芯片间树脂密封。
2.一种半导体装置的制造方法，在第1半导体芯片的第1面上，使具有第1凸块电极及第1贯通电极的第2半导体芯片以所述第1凸块电极与所述第1面相接的方式积层；
在所述第2半导体芯片上，使具有第2凸块电极及第2贯通电极的第3半导体芯片以所述第2凸块电极与所述第1贯通电极重叠的方式积层而形成芯片积层体；
将所述芯片积层体的所述第1及第2凸块电极利用回流焊机械连接于所述第1及第2贯通电极；
在具有第2面的第1衬底上，以所述第1面朝向所述第2面侧的方式搭载所述芯片积层体；
将所述第2面上及所述第1、第2及第3半导体芯片间树脂密封。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
在所述第1半导体芯片的所述第1面的相反面介隔第1树脂设置第2衬底。
4.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
使所述第1半导体芯片的所述第1面的相反面粘接于胶带材料。
5.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述回流焊是在还原气氛中进行。
6.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述树脂密封是利用传递模塑进行。
7.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述第1及第2凸块电极是包含Au、Ni、Cu、Sn、Bi、Zn、In及其合金的任一个的金属凸块，或包含Au、Ni、Cu、Al、Pd及其合金的任一个的电极垫。
8.根据权利要求4所述的半导体装置的制造方法，其特征在于：
在形成所述芯片积层体后，
使用拾取工具或吸附工具剥离所述胶带材料。
9.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
在所述第1、第2及第3半导体芯片间、或所述芯片积层体及所述第1衬底之间还具有粘接树脂。
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CN110299344A (zh) * 2018-03-22 2019-10-01 东芝存储器株式会社 半导体装置
CN110299344B (zh) * 2018-03-22 2023-09-19 铠侠股份有限公司 半导体装置
CN112466828A (zh) * 2019-09-06 2021-03-09 铠侠股份有限公司 半导体装置
CN112466828B (zh) * 2019-09-06 2024-01-30 铠侠股份有限公司 半导体装置

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US20180076187A1 (en) 2018-03-15
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