CN102800662A - 层叠型半导体装置及其制造方法 - Google Patents

层叠型半导体装置及其制造方法 Download PDF

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Publication number
CN102800662A
CN102800662A CN2012101700613A CN201210170061A CN102800662A CN 102800662 A CN102800662 A CN 102800662A CN 2012101700613 A CN2012101700613 A CN 2012101700613A CN 201210170061 A CN201210170061 A CN 201210170061A CN 102800662 A CN102800662 A CN 102800662A
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mentioned
semiconductor chip
projection
projected electrode
zone
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CN102800662B (zh
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筑山慧至
福田昌利
渡部博
沟口庆太
小牟田直幸
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Abstract

本发明提供层叠型半导体装置及其制造方法。实施方式的层叠型半导体装置具备:具有第1凸起电极的第1半导体芯片;具有第2凸起电极的第2半导体芯片。一边将凸起电极彼此连接,一边层叠第1及第2半导体芯片。在第1及第2半导体芯片的至少一方,设置阻挡用突起和粘接用突起。阻挡用突起与第1及第2半导体芯片的另一方以非粘接状态接触。粘接用突起与第1及第2半导体芯片粘接。

Description

层叠型半导体装置及其制造方法
技术领域
这里公开的实施方式一般地说涉及层叠型半导体装置及其制造方法。
背景技术
为了实现半导体装置的小型化、高功能化,在一个封装内层叠多个半导体芯片并密封的SiP(System in Package,系统级封装)构造的半导体装置已经实用化。SiP构造的半导体装置中,要求高速收发半导体芯片间的电气信号。这样的场合,在半导体芯片间的电气连接采用微凸起。微凸起具有例如5~50μm左右的直径,以10~100μm左右的间距在半导体芯片的表面形成。
用微凸起连接半导体芯片间的场合,在使设置于上下的半导体芯片的凸起彼此对位后,一边加热一边压接上下的半导体芯片,使凸起彼此连接。在上下的半导体芯片间的间隙,填充底部填充树脂,以提高连接可靠性等。凸起连接时,芯片间的间隙若过度减少,则发生凸起的过度压碎和/或伴随其的短路。因而,要求维持上下的半导体芯片间的间隙。而且,凸起连接后若半导体芯片发生翘曲,则可能在凸起间产生连接不良(断开不良)。因而,要求提高填充底部填充树脂前的半导体芯片间的连接强度。
发明内容
层叠型半导体装置中,存在提高填充底部填充树脂前的半导体芯片间的连接强度的课题。
根据一个实施方式,提供一种层叠型半导体装置,具备:第1半导体芯片,其具有具备第1连接区域和除上述第1连接区域以外的第1非连接区域的第1表面;第2半导体芯片,其具有具备与上述第1连接区域对向的第2连接区域和除上述第2连接区域以外的第2非连接区域的第2表面,层叠在上述第1半导体芯片上;第1凸起连接部,其设置在上述第1表面的上述第1连接区域和上述第2表面的上述第2连接区域之间,以电气连接上述第1半导体芯片和上述第2半导体芯片;阻挡用突起,其在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域局部地设置,且与上述第1非连接区域及上述第2非连接区域的另一方的区域以非粘接状态接触;粘接用突起,其在上述第1表面的上述第1非连接区域和上述第2表面的上述第2非连接区域之间局部地设置,与上述第1及第2表面粘接;和底部填充树脂,其在上述第1半导体芯片的上述第1表面和上述第2半导体芯片的上述第2表面之间的间隙填充。
附图说明
图1是第1实施方式的层叠型半导体装置的截面图。
图2A至图2C是第1实施方式的层叠型半导体装置的第1制造工序的截面图。
图3A及图3B是第1实施方式的制造工序采用的第1及第2半导体芯片的凸起电极形成面的第1例的平面图。
图4是表示图3A及图3B所示第1半导体芯片和第2半导体芯片的组合状态的平面透视图。
图5是半导体芯片的厚度和半导体芯片单体的翘曲量的关系示图。
图6A及图6B是第1实施方式的制造工序采用的第1及第2半导体芯片的凸起电极形成面的第2例的平面图。
图7是表示图6A及图6B所示第1半导体芯片和第2半导体芯片的组合状态的平面透视图。
图8A至图8C是第1实施方式的层叠型半导体装置的第2制造工序的截面图。
图9是第2实施方式的层叠型半导体装置的截面图。
图10是采用图9所示层叠型半导体装置的半导体封装的截面图。
图11是图10所示半导体封装的第1变形例的截面图。
图12是图10所示半导体封装的第2变形例的截面图。
图13是图10所示半导体封装的第3变形例的截面图。
图14A至图14F是第2实施方式的层叠型半导体装置的制造工序的截面图。
图15是第3实施方式的层叠型半导体装置的截面图。
图16A至图16C是第3实施方式的层叠型半导体装置的制造工序的截面图。
图17A及图17B是第3实施方式的制造工序采用的第1及第2半导体芯片的凸起电极形成面的平面图。
图18是表示图17A及图17B所示第1半导体芯片和第2半导体芯片的组合状态的平面透视图。
图19是第3实施方式的层叠型半导体装置的其他例的截面图。
图20A及图20B是第4实施方式的制造工序采用的第1及第2半导体芯片的凸起电极形成面的第1例的平面图。
图21是表示图20A及图20B所示第1半导体芯片和第2半导体芯片的组合状态的平面透视图。
图22A及图22B是第4实施方式的制造工序采用的第1及第2半导体芯片的凸起电极形成面的第2例的平面图。
图23是表示图22A及图22B所示第1半导体芯片和第2半导体芯片的组合状态的平面透视图。
图24是第5实施方式的层叠型半导体装置的截面图。
图25A至图25C是第5实施方式的层叠型半导体装置的制造工序的截面图。
图26A及图26B是第6实施方式的制造工序采用的第1及第2半导体芯片的凸起电极形成面的平面图。
具体实施方式
(第1实施方式)
参照附图说明第1实施方式的层叠型半导体装置及其制造方法。图1是第1实施方式的层叠型半导体装置的图。图2A至图2C、图3A至图3C及图4是第1实施方式的层叠型半导体装置的制造工序的示图。层叠型半导体装置1具备第1半导体芯片2和第2半导体芯片3。第1半导体芯片2的顶面(第1表面)2a具有第1连接区域,在第1连接区域内形成第1凸起电极4。
第2半导体芯片3的底面(第2表面)3a具有与第1连接区域对向(对置)的第2连接区域,在第2连接区域内形成第2凸起电极5。第2半导体芯片3在将第2凸起电极5与第1凸起电极4连接的同时,在第1半导体芯片2上层叠。即,第1半导体芯片2和第2半导体芯片3经由第1凸起电极4和第2凸起电极5的连接体(凸起连接部)6,电气及机械地连接。连接区域是指半导体芯片2、3的表面2a、3a中的凸起电极4、5的形成区域。凸起电极4、5是指形成电气及机械地连接第1半导体芯片2和第2半导体芯片3的凸起连接部的电极。
在第1及第2半导体芯片2、3的两方形成凸起电极4、5的场合,作为凸起电极4、5的构成,例示了焊料/焊料、Au/焊料、焊料/Au、Au/Au等的组合。作为形成凸起电极4、5的焊料,例示包括向Sn添加Cu、Ag、Bi、In等的Sn合金的无Pb焊料。作为无Pb焊料的具体例,有Sn-Cu合金、Sn-Ag合金、Sn-Ag-Cu合金等。形成凸起电极4、5的金属也可以用Cu、Ni、Sn、Pd、Ag等取代Au。这些金属不限于单层膜,也可以是多个金属的层叠膜。作为凸起电极4、5的形状,例举了半球状、柱状等的突起形状,但是也可以是衬垫(焊盘)那样的平坦形状。作为凸起电极4、5的组合,例举了突起体彼此的组合、突起体和平坦体的组合等。
在第1半导体芯片2的顶面2a中的第1连接区域以外的区域(第1非连接区域)及第2半导体芯片3的底面3a中的第2连接区域以外的区域(第2非连接区域)的至少一方的区域,局部地设置阻挡用突起7,使得第1半导体芯片2和第2半导体芯片3之间的间隙(缝隙)成为设定的凸起电极4、5的连接高度(凸起连接部6的设定高度)。即,压接第1半导体芯片2和第2半导体芯片3时,它们的间隙(缝隙)由阻挡用突起7规定,因此,可以抑制凸起连接部6的过度压碎和/或凸起电极4、5间的连接不良(断开不良)等的发生。阻挡用突起7的前端与第1非连接区域及第2非连接区域的另一方的区域以非粘接状态接触。
而且,在第1半导体芯片2的顶面2a中的第1非连接区域及第2半导体芯片3的底面3a中的第2非连接区域的至少一方的区域,局部地设置粘接用突起8,使得在连接第1凸起电极4和第2凸起电极5时,强化第1半导体芯片2和第2半导体芯片3的连接状态。在第1及第2非连接区域的至少一方的区域设置的粘接用突起8与第1及第2非连接区域的另一方的区域粘接。粘接用突起8在第1非连接区域和第2非连接区域之间局部地设置,与第1半导体芯片2的顶面2a和第2半导体芯片3的底面3a分别粘接。
在经由凸起连接部6连接的第1半导体芯片2和第2半导体芯片3之间的间隙,填充底部填充树脂9。通过在第1半导体芯片2的第1非连接区域和第2半导体芯片3的第2非连接区域之间设置粘接用突起8,可以提高底部填充树脂9填充前的第1半导体芯片2和第2半导体芯片3的连接强度。即,第1半导体芯片2和第2半导体芯片3在底部填充树脂9填充以前,除了第1凸起电极4和第2凸起电极5的连接部6,还通过粘接用突起8连接。从而,可以提高底部填充树脂9填充前的连接强度。
设置在第1半导体芯片2的凸起电极4和设置在第2半导体芯片3的凸起电极5在例如加热的同时通过压接而连接。半导体芯片2、3的表面,通常设置聚酰亚胺树脂膜这样的有机绝缘膜作为保护膜。构成半导体芯片2、3的硅基板的热膨胀系数为3ppm左右,而聚酰亚胺树脂的热膨胀系数大到35ppm左右。因而,半导体芯片2、3容易发生翘曲,尤其是半导体芯片2、3的厚度越薄,有翘曲量越大的倾向。从而,凸起电极4、5连接时或连接后,可能因半导体芯片2、3的翘曲导致凸起电极4、5的连接部6断裂。
图5表示半导体芯片的厚度和常温的半导体芯片的翘曲量的关系的一例。这里表示1边的长度为12mm的半导体芯片的单体的模拟翘曲量。如图5所示,半导体芯片2、3的厚度越薄,翘曲量越大。半导体芯片2、3若产生大的翘曲,则连接第1凸起电极4和第2凸起电极5的凸起连接部6可能断裂。半导体芯片2、3的厚度为100μm的场合的不良发生率为0%,为90μm的场合的不良发生率为10%,为80μm的场合的不良发生率为30%。相对这些,半导体芯片2、3的厚度若成为70μm,则不良发生率成为约100%。
对此,通过除了凸起连接部6还用粘接用突起8连接第1半导体芯片2和第2半导体芯片3,提高第1半导体芯片2和第2半导体芯片3的连接强度。因而,可以抑制热压接或回流焊接(reflow)等引起凸起连接后(底部填充树脂9的填充前)的半导体芯片2、3的翘曲。从而,可以抑制因半导体芯片2、3的翘曲导致底部填充树脂9的填充前第1凸起电极4和第2凸起电极5的凸起连接部6断裂。从而,可以抑制连接不良的发生。
半导体芯片2、3的厚度越薄,半导体芯片2、3的翘曲越容易导致凸起连接部6的断裂发生。实施方式的层叠型半导体装置1在采用厚度100μm以下的半导体芯片2、3的场合是有效的,而且在采用厚度70μm以下的半导体芯片2、3的场合更有效。而且,在凸起电极4、5的形成面积小的场合有效。从而,层叠型半导体装置1在凸起电极4、5的形成面积相对于半导体芯片2、3的表面2a、3a的比率为5%以下的场合有效,而且在1%以下的场合更有效。
层叠型半导体装置1在采用直径60μm以下的凸起电极4、5的场合有效,而且在采用直径40μm以下的凸起电极4、5的场合更有效。凸起电极4、5的直径考虑连接稳定性等,优选在5μm以上。后述的其他实施方式的层叠型半导体装置也同样。第1凸起电极4的直径和第2凸起电极5的直径可以大致相同,也可以不同。例如,第2凸起电极5设为突起形状,第1凸起电极4设为衬垫形状的场合,通过使第1凸起电极4的直径比第2凸起电极5大,可以提高第2凸起电极5对第1凸起电极4的连接性。
而且,粘接用突起8在半导体芯片2、3间局部地设置,因此,可以提高第1半导体芯片2和第2半导体芯片3的对位(对准)精度和/或第1凸起电极4和第2凸起电极5的连接性。在半导体芯片间的间隙全体配置兼备粘接功能和密封功能的热固化性绝缘树脂层的方法中,在第1半导体芯片和第2半导体芯片对位时,对准标志的检测精度降低。微凸起的形成间距越狭小,要求越高的对位精度。层叠型半导体装置1中,粘接用突起8以不覆盖对准标志的方式局部地设置,因此可以提高对准标志的检测精度,从而提高对位精度。
在半导体芯片间的间隙全体配置的热固化性绝缘树脂层,虽然有渗入第1凸起电极和第2凸起电极之间的危险,但是局部地设置的粘接用突起8不会降低凸起电极4、5间的连接性。从而,可以提高第1凸起电极4和第2凸起电极5的连接性。而且,在半导体芯片的间隙全体配置的热固化性绝缘树脂层,在半导体芯片间的连接时和/或粘接时,容易发生卷入空洞(void)。连接区域发生的空洞可能产生凸起连接部未被树脂覆盖的状态,因此可能在电极间发生短路。层叠型半导体装置1中,用粘接用突起8提高半导体芯片2、3间的连接强度的同时,将凸起电极4、5间连接,其上填充底部填充树脂9。因而,可以在可靠地覆盖凸起连接部6的状态下密封。从而,可以提高层叠型半导体装置1的可靠性。
上述层叠型半导体装置1例如如下制作。层叠型半导体装置1的制造工序参照图2A至图2C、图3A至图3C及图4说明。如图2A所示,准备具有第1凸起电极4的第1半导体芯片2和具有第2凸起电极5的第2半导体芯片3。图2A中,阻挡用突起7在第2半导体芯片3的底面3a中的第2非连接区域形成。粘接用突起8在第1半导体芯片2的顶面2a中的第1非连接区域形成。阻挡用突起7及粘接用突起8可以在第1及第2非连接区域的至少一方形成,也可以在例如两方的区域形成。
阻挡用突起7优选由例如聚酰亚胺树脂、苯酚树脂、环氧树脂、苯并环丁烯树脂等形成。粘接用突起8优选由例如环氧树脂、聚酰亚胺树脂、丙烯酸树脂、苯酚树脂等的热固化性树脂形成。阻挡用突起7、粘接用突起8可以采用光刻技术形成,或者采用利用分配器的涂敷技术形成。粘接用突起8也可以通过薄膜的粘接形成。涂敷液状的热固化性树脂组成物,形成粘接用突起8的场合,半导体芯片2、3粘接前优选设为半固化状态。或,优选用快速固化型的材料,可以缩短半导体芯片2、3的粘接、连接时的时间。
图3表示阻挡用突起7及粘接用突起8的配置例。图3A表示第1半导体芯片2的顶面(凸起电极形成面)2a。图3B表示第2半导体芯片3的底面(凸起电极形成面)3a。凸起电极4、5分别在半导体芯片2、3的表面2a、3a的中央附近配置,阻挡用突起7在第2半导体芯片3的表面全体配置,表面全体包含凸起电极4、5的周围。粘接用突起8在阻挡用突起7间配置。图4表示第1半导体芯片2与第2半导体芯片3组合状态下的阻挡用突起7和粘接用突起8的配置。
图3表示了具有与直径20~1000μm左右的阻挡用突起7同样形状的粘接用突起8,但是粘接用突起8的形状不限于此。通过液状树脂的涂敷、薄膜的粘接等形成粘接用突起8的场合,优选具有某程度的面积。如图6B所示,配置阻挡用突起7时,不在第2半导体芯片3的表面全体配置,在一部分形成空白区域(阻挡用突起7的未配置区域)。如图6A所示,在与阻挡用突起7的未配置区域对应的区域配置粘接用突起8。图7表示阻挡用突起7和粘接用突起8的组合配置。通过采用这样的配置,提高通过液状树脂的涂敷、薄膜的粘接等形成粘接用突起8的形成性。图6A、图6B及图7表示在半导体芯片2、3的四角配置凸起电极4、5的构造。
如图2A所示,在载物台11上载置且吸附保持的第1半导体芯片2上,配置在吸附头部12保持的第2半导体芯片3。由图示省略的拍摄机等检测第1及第2半导体芯片2、3的对准标志,使第2半导体芯片3在第1半导体芯片2上对位。然后,如图2B所示,由阻挡用突起7维持半导体芯片2、3间的间隙的同时,将第1半导体芯片2和第2半导体芯片3加热到凸起电极4、5的连接温度以上且构成粘接用突起8的热固化性树脂的固化温度以上的温度并压接。通过这样的热压接工序,将第1凸起电极4和第2凸起电极5连接,并将粘接用突起8与第1及第2半导体芯片2、3的表面2a、3a粘接。凸起电极4、5的连接温度是指由焊料形成凸起电极4、5的至少一方的场合,焊料的熔点以上的温度。
第1凸起电极4和第2凸起电极5的连接工序,也可以预先在不足凸起电极4、5的连接温度且构成粘接用突起8的热固化性树脂开始固化而呈现粘接性的温度及时间以上的情况下,暂时固定第1凸起电极4和第2凸起电极5后,加热到凸起电极4、5的连接温度以上的温度并压接而实施。或,也可以在暂时固定第1凸起电极4和第2凸起电极5后,用凸起电极4、5的连接温度以上的温度进行回流焊接,将第1凸起电极4和第2凸起电极5连接。
粘接用突起8例如在暂时固定第1凸起电极4和第2凸起电极5后,用构成粘接用突起8的热固化性树脂的固化温度以上的温度进行硬化(cure,固化)处理,从而与第1及第2半导体芯片2、3的表面2a、3a粘接。硬化处理工序在凸起电极4、5的热压接或回流焊接工序前实施。或,也可以通过用构成粘接用突起8的热固化性树脂的固化温度以上的温度实施第1凸起电极4和第2凸起电极5的暂时固定,在凸起电极4、5的暂时固定的同时,将粘接用突起8与第1及第2半导体芯片2、3的表面2a、3a粘接。另外,在加热到凸起电极4、5的连接温度以上且构成粘接用突起8的热固化性树脂的固化温度以上的温度并压接的场合,也可以辅助地实施粘接用突起8的硬化处理工序和/或凸起电极4、5的热压接或回流焊接工序。
然后,如图2C所示,通过在第1半导体芯片2和第2半导体芯片3之间的间隙填充底部填充树脂9并固化,制造层叠型半导体装置1。这里虽然图示省略,但层叠型半导体装置1在具有外部连接端子的布线基板和/或引线框架等的电路基体材料上搭载,用作SiP构造的半导体装置等。层叠型半导体装置1和电路基体材料的连接通过倒装芯片接合、线接合等实施。
如上所述,底部填充树脂9填充前的阶段中,第1半导体芯片2和第2半导体芯片3通过凸起连接部6以及粘接用突起8连接,因此可以抑制热压接或者回流焊接后的半导体芯片2、3的翘曲。从而,可以抑制因半导体芯片2、3的翘曲导致底部填充树脂9的填充前第1凸起电极4和第2凸起电极5的连接断裂。因此,可以抑制凸起电极4、5间的连接不良(断开不良)的发生。
图8A至图8C表示层叠型半导体装置1的第2制造工序。如图8A所示,阻挡用突起7的高度h优选比第1凸起电极4的高度H1和第2凸起电极5的高度H2的合计高度(H1+H2)低。通过满足这样的条件(h<H1+H2),可以更可靠地连接第1凸起电极4和第2凸起电极5。如图8B所示,使第2凸起电极5与第1凸起电极4接触。该阶段中,阻挡用突起7与第1半导体芯片2的表面不接触。而且,如图8C所示,例如使第2凸起电极5变形,直到阻挡用突起7与第1半导体芯片2的表面接触。
使第2凸起电极5变形的工序可以是加热到第1凸起电极4和第2凸起电极5连接的温度并压接的工序,或在构成粘接用突起8的热固化性树脂开始固化呈现粘接性的温度及时间以上暂时固定第1凸起电极4和第2凸起电极5的工序。第1凸起电极4和第2凸起电极5暂时固定时,然后实施加热到凸起电极4、5的连接温度以上的温度并加压的工序和/或回流焊接工序。通过满足上述条件(h<H1+H2),可以防止阻挡用突起7维持的间隔变得过宽,第1凸起电极4和第2凸起电极5的连接变得不充分(凸起电极4、5的接触状态不充分)。
如上所述,通过本实施方式,在层叠型半导体装置中,可以提高底部填充树脂填充前的半导体芯片间的连接强度。
(第2实施方式)
说明第2实施方式的层叠型半导体装置。图9是第2实施方式的层叠型半导体装置的图。与第1实施方式相同的部分附上相同符号,省略了一部分说明。图9所示层叠型半导体装置20具有将第1半导体芯片21和第2半导体芯片22和第3半导体芯片23层叠的构造。这里,说明了层叠第1至第3半导体芯片21、22、23的层叠型半导体装置20,但是半导体芯片的层叠数也可以4层以上。该场合,通过反复第3半导体芯片23的层叠工序,可以获得层叠了必要数的半导体芯片的层叠型半导体装置。
第1半导体芯片21的顶面(第1表面)具有第1连接区域,在第1连接区域内形成第1凸起电极4。第2半导体芯片22的底面(第2表面)具有第2连接区域,在第2连接区域内形成第2凸起电极5。第2半导体芯片22在将第2凸起电极5与第1凸起电极4连接的同时,在第1半导体芯片21上层叠。第1半导体芯片21和第2半导体芯片22与第1实施方式同样,经由第1凸起电极4和第2凸起电极5的凸起连接部6A而电气及机械地连接。
为了在第2半导体芯片22上层叠第3半导体芯片23,第2半导体芯片22的顶面(第3表面)具有第3连接区域,在第3连接区域内设置第3凸起电极24。第2凸起电极5和第3凸起电极24经由设置在第2半导体芯片22内的贯通电极(Through Silicon Via:TSV)25A电气连接。第3半导体芯片23的底面(第4表面)具有第4连接区域,在第4连接区域内形成第4凸起电极26。第2半导体芯片22和第3半导体芯片23经由第3凸起电极24和第4凸起电极26的凸起连接部25B电气及机械地连接。第4凸起电极26,经由在第3半导体芯片23的顶面设置的电极27和贯通电极(TSV)25B,电气连接。
在第1半导体芯片21的顶面中的第1非连接区域及第2半导体芯片22的底面中的第2非连接区域的至少一方的区域,分别局部地设置第1阻挡用突起7A及第1粘接用突起8A。阻挡用突起7A的前端与第1及第2非连接区域的另一方的区域以非粘接状态接触。在第1及第2非连接区域的至少一方的区域设置的粘接用突起8A与第1及第2非连接区域的另一方的区域粘接。粘接用突起8在第1非连接区域和第2非连接区域之间局部地设置,与第1半导体芯片21的顶面和第2半导体芯片22的底面分别粘接。
同样,在第2半导体芯片22的顶面中的第3非连接区域及第3半导体芯片23的底面中的第4非连接区域的至少一方的区域,分别局部地设置第2阻挡用突起7B及第2粘接用突起8B。阻挡用突起7B的前端与第3及第4非连接区域的另一方的区域以非粘接状态接触。在第3及第4非连接区域的至少一方的区域设置的粘接用突起8B与第3及第4非连接区域的另一方的区域粘接。粘接用突起8B在第3非连接区域和第4非连接区域之间局部地设置,与第2半导体芯片22的顶面和第3半导体芯片23的底面分别粘接。
如上所述,即使层叠3个半导体芯片21、22、23或者更多的半导体芯片的场合,通过用粘接用突起8A、8B提高底部填充树脂填充前的半导体芯片间的连接强度,也可以抑制热压接或者回流焊接后的半导体芯片的翘曲。从而,可以抑制第1及第2凸起电极4、5间和第3及第4凸起电极24、26间的连接不良(断开不良)。阻挡用突起7A、7B及粘接用突起8A、8B的形成材料、形成处所、配置形状等与第1实施方式同样。
第2实施方式的层叠型半导体装置20用作例如图10所示的半导体封装30。图10所示半导体封装30中,层叠型半导体装置20在具有外部连接端子31和内部连接端子32的布线基板33上搭载。布线基板33的内部连接端子32经由在层叠型半导体装置20的最上级的半导体芯片23的顶面形成的再布线层34和接合线35,与层叠型半导体装置20电气连接。在布线基板33上,形成将层叠型半导体装置20与接合线35等一起密封的树脂密封层36。
层叠型半导体装置20和布线基板33的电气连接也可以通过倒装芯片接合实施。图11表示将层叠型半导体装置20和布线基板32进行了倒装芯片接合的状态。为了将层叠型半导体装置20进行倒装芯片接合,在第1半导体芯片21的底面设置第5凸起电极28。第5凸起电极28和第1凸起电极4经由在第1半导体芯片21内设置的贯通电极(TSV)25C电气连接。第1半导体芯片21在基板33上安装。基板33和第1半导体芯片21经由在基板33的内部连接端子32上设置的第6凸起电极29和第5凸起电极28的连接体(凸起连接部)6C而电气及机械地连接。
在第1半导体芯片21的底面中的非连接区域及基板33的表面的至少一方的区域,分别局部地设置第3阻挡用突起7C及第3粘接用突起8C。阻挡用突起7C的前端与第1半导体芯片21的底面中的非连接区域及基板33的表面的另一方的区域以非粘接状态接触。在第1半导体芯片21的底面中的非连接区域及基板33的表面的至少一方的区域设置的粘接用突起8C与第1半导体芯片21的底面中的非连接区域及基板33的表面的另一方的区域粘接。
图12表示图10所示半导体封装30的变形例。构成层叠型半导体装置20的半导体芯片21~23为NAND型闪速存储器这样的存储器芯片的场合,也可以在层叠型半导体装置20上搭载在控制器芯片、接口芯片这样的在外部装置之间进行数据通信的半导体芯片37。半导体芯片37经由焊料凸起38与层叠型半导体装置20连接。层叠型半导体装置20经由半导体芯片37、接合线35等与布线基板33电气连接。如图13所示,层叠型半导体装置20也可以经由在位于层叠顺序的最上级(纸面最下级)的半导体芯片37设置的焊料凸起39,与布线基板33电气及机械地连接。
接着,参照图14A至图14F说明第2实施方式的层叠型半导体装置20的制造工序。图14A至图14F省略了载物台11和吸附头部12的图示,但是基本与第1实施方式同样实施层叠工序。如图14A所示,使具有第1凸起电极4和第1粘接用突起8A的第1半导体芯片21与具有第2凸起电极5和第1阻挡用突起7A的第2半导体芯片22对位。如图14B所示,在构成第1粘接用突起8A的热固化性树脂开始固化而呈现粘接性的温度及时间以上,暂时固定第1凸起电极4和第2凸起电极5。
然后,如图14C所示,在第2半导体芯片22的顶面中的第3非连接区域形成第2粘接用突起8B。第2粘接用突起8B优选通过例如利用分配器的涂敷、薄膜的粘接等而形成。如图14D所示,将具有第4凸起电极26和第2阻挡用突起7B的第3半导体芯片23与第2半导体芯片22对位。如图14E所示,在构成粘接用突起8A、8B的热固化性树脂开始固化而呈现粘接性的温度及时间以上,暂时固定第3凸起电极24和第4凸起电极26。
将第1至第3半导体芯片21、22、23的层叠体加热到凸起电极4、5、24、25的连接温度以上且构成粘接用突起8A、8B的热固化性树脂的固化温度以上的温度并压接。通过热压接芯片层叠体,将第1凸起电极4和第2凸起电极5、第3凸起电极24和第4凸起电极26连接,并将第1粘接用突起8A与第1及第2半导体芯片2、3的表面粘接,而且将第2粘接用突起8B与第2及第3半导体芯片3、25的表面粘接。这里,说明了凸起电极间的连接和粘接用突起的固化同时实施的场合,但是粘接用突起的固化和凸起电极间的连接也可以由不同工序实施。
粘接用突起的固化工序(硬化工序)将例如第1凸起电极4和第2凸起电极5暂时固定且第3凸起电极24和第4凸起电极26暂时固定的芯片层叠体配置在烤炉内后,加热到构成粘接用突起8A、8B的热固化性树脂的固化温度以上的温度而实施。通过热处理芯片层叠体,使粘接用突起8A、8B固化,将第1半导体芯片21和第2半导体芯片22之间用粘接用突起8A粘接,且将第2半导体芯片22和第3半导体芯片23之间用粘接用突起8B粘接。
粘接用突起8A、8B的硬化处理也可以与凸起电极的暂时固定同时实施。该场合,凸起电极的暂时固定以粘接用构成突起8A、8B的热固化性树脂的固化温度以上的温度实施。粘接用突起8A、8B的硬化工序中,粘接用突起8A、8B的固化反应若不充分,则粘接用突起8A、8B和半导体芯片21、22、23的粘接不充分,因此可能产生剥离,凸起连接部6断裂,发生连接不良。从而,优选在维持粘接性的范围使粘接用突起8A、8B充分固化。
然后,将半导体芯片间用粘接用突起8A、8B粘接的芯片层叠体以凸起电极的连接温度以上的温度进行压接或回流焊接。压接工序通过加热并压接粘接用突起8A、8B固化后的芯片层叠体而实施。采用回流焊接工序的场合,将半导体芯片间用粘接用突起8A、8B粘接的芯片层叠体配置在回流焊接炉内。在将回流焊接炉内设为还原气氛的状态下,通过加热到凸起电极的连接温度以上的温度,将第1凸起电极4和第2凸起电极5连接,并将第3凸起电极24和第4凸起电极26连接。回流焊接工序优选在还原气氛中实施。从而,可以除去凸起电极的表面氧化膜,获得凸起连接部。
如图14F所示,在第1半导体芯片21和第2半导体芯片22的间隙及第2半导体芯片22和第3半导体芯片23的间隙分别填充底部填充树脂9并固化。这样,制造第2实施方式的层叠型半导体装置20。即使层叠3个或者以上的半导体芯片的场合,通过用粘接用突起8A、8B提高底部填充树脂9填充前的半导体芯片间的连接强度,可以抑制热压接或者回流焊接后的半导体芯片的翘曲。从而,可以抑制第1及第2凸起电极4、5间和第3及第4凸起电极24、26间的连接不良(断开不良)。
层叠第1至第3半导体芯片21、22、23时,最上级的半导体芯片23优选加热到凸起电极的连接温度以上的温度并压接。其他的半导体芯片21、22加热到不足凸起电极的连接温度的温度并压接。从而,提高芯片层叠体的强度。若用凸起电极的连接温度以上的温度压接全部半导体芯片21、22、23,则对半导体芯片21、22、23的热负载增大。通过仅仅将最上级的半导体芯片23加热到凸起电极的连接温度以上的温度并压接,可以降低对半导体芯片21、22、23的热负载,并提高芯片层叠体的强度。
通过用凸起电极的连接温度以上的温度热压接最上级的半导体芯片23,连接第1凸起电极4和第2凸起电极5及第3凸起电极24和第4凸起电极26。该场合,也可以与半导体芯片23的热压接工序独立地实施将前述的粘接用突起8A、8B硬化处理的工序以及芯片层叠体的压接或回流焊接的工序。另外,也不排除用凸起电极的连接温度以上的温度压接全部半导体芯片21、22、23的工序的适用。
如图12所示的半导体封装,在第1至第3半导体芯片21、22、23和最上级的半导体芯片37的尺寸不同的场合和凸起电极的排列不同的场合,优选将第3半导体芯片23及最上级的半导体芯片37分别加热到凸起电极的连接温度以上的温度并压接。其他的半导体芯片21、22加热到不足凸起电极的连接温度的温度并压接。
如上所述,通过本实施方式,在层叠型半导体装置中,可以提高底部填充树脂填充前的半导体芯片间的连接强度。
(第3实施方式)
参照图15及图16A至图16C说明第3实施方式的层叠型半导体装置的构成和制造工序。第3实施方式的层叠型半导体装置40具有阻挡兼粘接用突起41,取代第1及第2实施方式中的阻挡用突起7及粘接用突起8。与第1及第2实施方式相同的部分附上相同符号,省略了一部分说明。
图15所示层叠型半导体装置40具备:具有阻挡兼粘接用突起41和第1凸起电极4的第1半导体芯片2;具有第2凸起电极5的第2半导体芯片3。第1半导体芯片2和第2半导体芯片3经由第1凸起电极4和第2凸起电极5的连接体(凸起连接部6),电气及机械地连接。阻挡兼粘接用突起41在第1半导体芯片2的顶面(第1表面)2a中的非连接区域局部地设置,与第1半导体芯片2的顶面2a和第2半导体芯片3的底面3a分别粘接。在第1半导体芯片2和第2半导体芯片3之间的间隙,填充底部填充树脂。
在第1半导体芯片2的顶面2a设置的阻挡兼粘接用突起41在压接第1半导体芯片2和第2半导体芯片3时保持它们的间隙(缝隙),且在加热时与第2半导体芯片3的底面3a粘接。从而,与采用阻挡用突起7和粘接用突起8的第1实施方式同样,可以在维持压接时的第1半导体芯片2和第2半导体芯片3之间的间隙(缝隙)的同时,提高底部填充树脂填充前的第1半导体芯片2和第2半导体芯片3的连接强度。从而,可以提高凸起电极4、5间的连接可靠性。
阻挡兼粘接用突起41用具有例如感光性及热固化性的树脂(例如含有感光剂的热固化性树脂/感光性粘接剂树脂等)形成。若采用感光性及热固化性树脂,则在突起41的形成阶段中,因为紫外线等的照射而固化,因此可以起到阻挡的功能。而且,由于在加热时热固化,因此,与第1及第2半导体芯片2、3的表面牢固粘接,起到粘接剂(粘接用突起)的功能。阻挡兼粘接用突起41不限于由具有感光性及热固化性的树脂形成,例如也可以在耐热树脂制突起的前端形成粘接剂层。从而,可以获得同样的阻挡功能和粘接功能。阻挡兼粘接用突起41也可以设置在第2半导体芯片3的底面3a。
第3实施方式的层叠型半导体装置40例如如下制作。如图16A所示,准备具有第1凸起电极4和阻挡兼粘接用突起41的第1半导体芯片2和具有第2凸起电极5的第2半导体芯片3。图17A、图17B及图18表示阻挡兼粘接用突起41的配置例。图17A表示第1半导体芯片2的顶面(凸起电极形成面)2a。图17B表示第2半导体芯片3的底面(凸起电极形成面)3a。图18表示第1半导体芯片2和第2半导体芯片3的组合状态。阻挡兼粘接用突起41在第1半导体芯片2的表面全体配置,表面全体包含在半导体芯片2的中央附近存在的凸起电极4的周围。
接着,与第1实施方式同样,使第1半导体芯片2和第2半导体芯片3对位。如图16B所示,用阻挡兼粘接用突起41维持间隙的同时,将第1半导体芯片2和第2半导体芯片3压接并加热。通过这样的热压接工序,连接第1凸起电极4和第2凸起电极5,并将阻挡兼粘接用突起41与第1及第2半导体芯片2、3的表面2a、3a粘接。
第1凸起电极4和第2凸起电极5的连接工序也可以预先在不足凸起电极4、5的连接温度且构成阻挡兼粘接用突起41的热固化性树脂开始固化而呈现粘接性的温度及时间以上,暂时固定第1凸起电极4和第2凸起电极5,然后,以构成阻挡兼粘接用突起41的热固化性树脂的固化温度以上的温度硬化处理后,加热到凸起电极4、5的连接温度以上的温度并压接而实施。也可以取代热压接工序,采用回流焊接工序。阻挡兼粘接用突起41的硬化处理也可以与凸起电极4、5的暂时固定同时实施。
然后,如图16C所示,通过在第1半导体芯片2和第2半导体芯片3之间的间隙填充底部填充树脂9并固化,制造层叠型半导体装置40。底部填充树脂9填充前的阶段中,第1半导体芯片2和第2半导体芯片3通过凸起连接部6以及阻挡兼粘接用突起41连接,因此可以抑制热压接或者回流焊接后的半导体芯片2、3的翘曲。从而,可以抑制因半导体芯片2、3的翘曲导致底部填充树脂9填充前第1凸起电极4和第2凸起电极5的连接断裂而造成连接不良(断开不良)的发生。
层叠3个以上的半导体芯片的场合,反复实施半导体芯片的层叠工序即可。图19表示层叠3个半导体芯片21、22、23构成的层叠型半导体装置42。这样的层叠型半导体装置42例如如下制作。首先,使具有第1凸起电极4的第1半导体芯片21和具有第2凸起电极5和第1阻挡兼粘接用突起41A的第2半导体芯片22对位。阻挡兼粘接用突起41A的高度优选比第1凸起电极4的高度和第2凸起电极5的高度的合计高度低。在第2半导体芯片22的顶面预先设置第2凸起电极24。
使凸起电极4、5变形,直到第1凸起电极4和第2凸起电极5接触,而且阻挡兼粘接用突起41A与第2半导体芯片22接触。暂时固定第1凸起电极4和第2凸起电极5。半导体芯片21、22层叠时的温度优选不足凸起电极4、5的连接温度,且在构成阻挡兼粘接用突起41A的热固化性树脂开始固化而呈现粘接性的温度以上。从而,凸起电极4、5软化,变得容易以低负载变形,而且在阻挡兼粘接用突起41A呈现粘接性。但是,加热温度若过高,则阻挡兼粘接用突起41A的固化反应可能急剧进行。优选考虑这样的点来设定温度。
使具有第4凸起电极26和第2阻挡兼粘接用突起41B的第3半导体芯片23与第2半导体芯片22对位后,暂时固定第3凸起电极24和第4凸起电极25。凸起电极24、25的暂时固定工序在与凸起电极4、5的暂时固定工序在同样的条件下实施。或,如第2实施方式说明,也可以是仅仅最上级的半导体芯片23的层叠工序以凸起电极的连接温度以上的温度实施。从而,提高芯片层叠体的粘接强度。
将第1至第3半导体芯片21、22、23的层叠体加热到凸起电极的连接温度以上且构成阻挡兼粘接用突起41A、41B的热固化性树脂的固化温度以上的温度并压接。从而,将第1凸起电极4和第2凸起电极5、第3凸起电极24和第4凸起电极26连接,并将第1及第2阻挡兼粘接用突起41A、41B与对向的半导体芯片21、22的表面粘接。然后,在第1半导体芯片21和第2半导体芯片22的间隙及第2半导体芯片22和第3半导体芯片23的间隙分别填充底部填充树脂并固化。
这里,说明了凸起电极间的连接和阻挡兼粘接用突起41A、41B的固化同时实施的场合,但是阻挡兼粘接用突起的固化和凸起电极间的连接也可以由不同工序实施。阻挡兼粘接用突起41A、41B的固化工序,例如通过在将第1凸起电极4和第2凸起电极5暂时固定且第3凸起电极24和第4凸起电极26暂时固定的芯片层叠体配置在烤炉内后,加热到构成阻挡兼粘接用突起41A、41B的热固化性树脂的固化温度以上的温度而实施。阻挡兼粘接用突起41A、41B的硬化处理也可以与凸起电极的暂时固定同时实施。该场合,凸起电极的暂时固定以阻挡兼粘接用构成突起41A、41B的热固化性树脂的固化温度以上的温度实施。
然后,将半导体芯片间用阻挡兼粘接用突起41A、41B粘接的芯片层叠体以凸起电极的连接温度以上的温度进行压接或回流焊接。压接工序及回流焊接工序如第2实施方式所述。阻挡兼粘接用突起41A、41B的固化工序中,阻挡兼粘接用突起41A、41B的固化反应若不充分,则阻挡兼粘接用突起41A、41B和半导体芯片21、22、23的粘接不充分,因此可能产生剥离,凸起连接部6断裂,发生连接不良。从而,优选在维持粘接性的范围使阻挡兼粘接用突起41A、41B充分固化。
如上所述,通过本实施方式,在层叠型半导体装置中,可以提高底部填充树脂填充前的半导体芯片间的连接强度。
(第4实施方式)
参照图20A、图20B、图21、图22A、图22B及图23说明第4实施方式的层叠型半导体装置的构成。第4实施方式的层叠型半导体装置,具有抑制底部填充树脂向第1及第2实施方式中的粘接用突起8或第3实施方式中的阻挡兼粘接用突起41渗出的功能。另外,其他构成与第1至第3实施方式相同,因此这里省略说明。
图20A及图20B表示了具有底部填充树脂的渗出抑制功能的粘接用突起8的配置例。图20A表示第1半导体芯片2的顶面2a。图20B表示第2半导体芯片3的底面3a。图21表示第1半导体芯片2和第2半导体芯片3的组合状态。粘接用突起8沿半导体芯片2的对向的2个外形边设置在半导体芯片2的外周区域。若采用这样的粘接用突起8,则可以抑制底部填充树脂从底部填充树脂的注入边和与其对向的边以外渗出。
图22A及图22B表示具有底部填充树脂的渗出抑制功能的阻挡兼粘接用突起41的配置例。图22A表示第1半导体芯片2的顶面2a。图22B表示第2半导体芯片3的底面3a。图23表示第1半导体芯片2和第2半导体芯片3的组合状态。阻挡兼粘接用突起41设置在半导体芯片2的外周区域和凸起电极4的周围。半导体芯片2的外周区域中,阻挡兼粘接用突起41沿除了底部填充树脂的注入边的外形边而配置。若采用这样的阻挡兼粘接用突起41,则可抑制底部填充树脂从底部填充树脂的注入边以外渗出。
沿半导体芯片2的3个外形边配置阻挡兼粘接用突起41的场合,底部填充树脂的填充以例如在减压下填充后向大气压开放的方法、减压下或者大气压下填充后在加压下硬化的方法来实施是有效的。这些方法是通过差压压碎填充时发生的空洞的方法。特别地说,如图22A所示配置阻挡兼粘接用突起41的场合,可以有效施加压力,有效压碎空洞。图20A、图20B及图21所示粘接用突起8的配置也可以适用于阻挡兼粘接用突起41。图22A、图22B及图23所示阻挡兼粘接用突起41的配置也可以适用于粘接用突起8。
如上所述,通过本实施方式,在层叠型半导体装置中,可以提高底部填充树脂填充前的半导体芯片间的连接强度。
(第5实施方式)
参照图24、图25A至图25C、图26A及图26B说明第5实施方式的层叠型半导体装置的构成和制造工序。第5实施方式的层叠型半导体装置50,具备在阻挡用突起7及粘接用突起8的接触面或者阻挡兼粘接用突起41的接触面设置的有机绝缘膜51。其他构成基本与第1至第3实施方式相同。与第1至第3实施方式相同的部分附上相同符号,省略了一部分说明。这里,主要说明采用阻挡兼粘接用突起41的层叠型半导体装置50,但是采用阻挡用突起7及粘接用突起8的场合也同样。
图24所示层叠型半导体装置50具备:具有第1凸起电极4的第1半导体芯片2;具有第2凸起电极5和阻挡兼粘接用突起41的第2半导体芯片3。第1半导体芯片2和第2半导体芯片3经由第1凸起电极4和第2凸起电极5的凸起连接部6电气及机械地连接。阻挡兼粘接用突起41在第2半导体芯片3的底面3a中的非连接区域局部地设置,与第1半导体芯片2粘接。在第1半导体芯片2和第2半导体芯片3之间填充底部填充树脂9。
在第1半导体芯片2的顶面2a,除了第1凸起电极4,还有形成包括Al布线膜等的表面布线52的情况。表面布线52根据期望的图形而形成,因此,有表面布线52存在的部分和不存在的部分。由于表面布线52的有无,在第1半导体芯片2的顶面2a产生1~2μm左右的凹凸。在表面布线52不存在的部分配置的阻挡兼粘接用突起41和第1半导体芯片2的顶面2a之间产生间隙,无法起到阻挡物和粘接剂的功能。因而,第5实施方式的层叠型半导体装置50中,第1半导体芯片2的顶面2a中的非连接区域用有机绝缘膜51覆盖。
通过用有机绝缘膜51覆盖第1半导体芯片2的顶面2a中的非连接区域,可以使阻挡兼粘接用突起41的接触高度均一,使全部阻挡兼粘接用突起41起到阻挡物及粘接剂的良好功能。有机绝缘膜51采用聚酰亚胺系树脂、苯酚系树脂等的热固化性树脂。有机绝缘膜51优选包括固化温度250℃以下的热固化性树脂、例如低温固化的聚酰亚胺系树脂、苯酚系树脂。有机绝缘膜51由例如旋涂的涂敷工序、光刻工序和显影工序形成。
有机绝缘膜51在阻挡兼粘接用突起41的粘接面形成。图24所示层叠型半导体装置50中,阻挡兼粘接用突起41预先设置在第2半导体芯片3的底面3a,因此,有机绝缘膜51设置在第1半导体芯片2的顶面2a的非连接区域。阻挡兼粘接用突起41设置在第1半导体芯片2的顶面2a的场合,有机绝缘膜51设置在第2半导体芯片3的底面3a的非连接区域。取代阻挡兼粘接用突起41而采用阻挡用突起7及粘接用突起8的场合也同样。有机绝缘膜51设置在与形成了阻挡用突起7、粘接用突起8的芯片面对向的半导体芯片的面的非连接区域。
有机绝缘膜51除了使阻挡兼粘接用突起41的接触面的高度均一即接触面平坦化的效果外,还具有提高阻挡兼粘接用突起41的粘接可靠性的效果。阻挡兼粘接用突起41具有例如80~200ppm/℃左右的线膨胀系数,而在半导体芯片2的表面设置的无机绝缘膜的线膨胀系数为例如0.1~10ppm/℃左右。因而,在不形成有机绝缘膜51的场合,因阻挡兼粘接用突起41和无机绝缘膜的热膨胀差,容易产生剥离。相对地,有机绝缘膜51的线膨胀系数为例如40~70ppm/℃左右,因此与阻挡兼粘接用突起41的热膨胀差降低。从而,可以抑制阻挡兼粘接用突起41的剥离。
有机绝缘膜51的线膨胀系数比阻挡兼粘接用突起41小的场合,可以将线膨胀系数大的阻挡兼粘接用突起41的高度减少有机绝缘膜51的膜厚的量。从而,阻挡兼粘接用突起41的高度方向的变动减少,因此阻挡兼粘接用突起41的粘接可靠性提高。为了降低阻挡兼粘接用突起41的高度,有机绝缘膜51除了在阻挡兼粘接用突起41的粘接面(第1半导体芯片2的顶面2a),在阻挡兼粘接用突起41的形成面(第2半导体芯片3的底面3a)形成也是有效的。取代阻挡兼粘接用突起41而采用阻挡用突起7及粘接用突起8的场合也同样。
第5实施方式的层叠型半导体装置50例如如下制作。如图25A所示,准备具有第1凸起电极4的第1半导体芯片2和具有第2凸起电极5和阻挡兼粘接用突起41的第2半导体芯片3。图26A及图26B表示阻挡兼粘接用突起41及有机绝缘膜51的形成例。图26A表示第1半导体芯片2的顶面2a。图26B表示第2半导体芯片3的底面3a。有机绝缘膜51在第1半导体芯片2的顶面2a的非连接区域,即除了凸起电极4的形成位置的区域全体形成。
使第1半导体芯片2和第2半导体芯片3对位后,如图25B所示,使凸起电极4、5变形,直到第1凸起电极4和第2凸起电极5接触,而且阻挡兼粘接用突起41A与有机绝缘膜51接触。暂时固定第1凸起电极4和第2凸起电极5。将第1及第2半导体芯片2、3的层叠体加热到凸起电极的连接温度以上且构成阻挡兼粘接用突起41A、41B的热固化性树脂的固化温度以上的温度并压接。通过热压接芯片层叠体,连接第1凸起电极4和第2凸起电极5,并将阻挡兼粘接用突起41与设置在第1半导体芯片的顶面2a的有机绝缘膜51粘接。也可以取代芯片层叠体的热压接工序,采用第1至第3实施方式说明的粘接剂的硬化工序和凸起电极的连接工序的组合。
然后,与前述第3实施方式同样,通过在第1半导体芯片2和第2半导体芯片3之间的间隙填充底部填充树脂并固化,制造层叠型半导体装置50。这里,说明了2个半导体芯片2、3层叠的场合,但是3个或以上的半导体芯片层叠的场合也同样。3个或以上的半导体芯片层叠时的构成如第2及第3实施方式所示。取代阻挡兼粘接用突起41而采用阻挡用突起7及粘接用突起8时的构成如第1及第2实施方式所示。
如上所述,通过本实施方式,在层叠型半导体装置中,可以提高底部填充树脂填充前的半导体芯片间的连接强度。
另外,第1至第5实施方式的构成可以分别组合,也可以部分置换。虽然说明了本发明的几个实施方式,但是这些实施方式只是作为例示,而不是限定发明的范围。这些新实施方式可以其他各种各样的形态实施,在不脱离发明的要旨的范围,可以进行各种省略、置换、变更。这些实施方式及其变形是发明的范围和要旨所包含的,同时也是权利要求的范围所述的发明及其均等的范围所包含的。

Claims (20)

1.一种层叠型半导体装置,其特征在于,具备:
第1半导体芯片,其具有具备第1连接区域和除上述第1连接区域以外的第1非连接区域的第1表面;
第2半导体芯片,其具有具备与上述第1连接区域对向的第2连接区域和除上述第2连接区域以外的第2非连接区域的第2表面,层叠在上述第1半导体芯片上;
第1凸起连接部,其设置在上述第1表面的上述第1连接区域和上述第2表面的上述第2连接区域之间,以电气连接上述第1半导体芯片和上述第2半导体芯片;
阻挡用突起,其在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域局部地设置,且与上述第1非连接区域及上述第2非连接区域的另一方的区域以非粘接状态接触;
粘接用突起,其在上述第1表面的上述第1非连接区域和上述第2表面的上述第2非连接区域之间局部地设置,与上述第1及第2表面粘接;和
底部填充树脂,其在上述第1半导体芯片的上述第1表面和上述第2半导体芯片的上述第2表面之间的间隙填充。
2.如权利要求1所述的层叠型半导体装置,其特征在于,
还具备在上述第2半导体芯片上层叠的第3半导体芯片,
上述第2半导体芯片具有具备第3连接区域和除上述第3连接区域以外的第3非连接区域的、位于上述第2表面的相反侧的第3表面,
上述第3半导体芯片具有具备与上述第3连接区域对向的第4连接区域和除上述第4连接区域以外的第4非连接区域的第4表面,且在上述第2半导体芯片上层叠,
上述第2半导体芯片和上述第3半导体芯片通过在上述第3表面的上述第3连接区域和上述第4表面的上述第4连接区域之间设置的第2凸起连接部电气连接,
在上述第2半导体芯片的上述第3表面和上述第3半导体芯片的上述第4表面之间配置有阻挡用突起,其在上述第3表面的上述第3非连接区域及上述第4表面的上述第4非连接区域的至少一方的区域局部地设置,且与上述第3非连接区域及上述第4非连接区域的另一方的区域以非粘接状态接触,
在上述第3表面的上述第3非连接区域和上述第4表面的上述第4非连接区域之间,局部地配置有与上述第3及第4表面粘接的粘接用突起,
在上述第2半导体芯片的上述第3表面和上述第3半导体芯片的上述第4表面之间的间隙,填充有底部填充树脂。
3.如权利要求2所述的层叠型半导体装置,其特征在于,
第3凸起电极经由在上述第2半导体芯片内设置的贯通电极,与第2凸起电极电气连接。
4.如权利要求1所述的层叠型半导体装置,其特征在于,
上述粘接用突起设置在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域,在上述第1非连接区域及上述第2非连接区域的至少另一方的区域设置有机绝缘膜。
5.如权利要求1所述的层叠型半导体装置,其特征在于,
还具备基板,其具有具备连接端子的表面,
上述第1半导体芯片具有具备第5连接区域和除上述第5连接区域以外的第5非连接区域的、位于上述第1表面的相反侧的第5表面,且在上述基板上安装,
上述基板和上述第1半导体芯片通过设置在上述第5表面的上述第5连接区域和上述基板的上述连接端子之间的第3凸起连接部电气连接,
在上述基板的上述表面和上述第1半导体芯片的上述第5表面之间配置有阻挡用突起,其在上述第5表面的上述第5非连接区域及上述基板的上述表面的至少一方的区域局部地设置,且与上述第5非连接区域及上述基板的上述表面的另一方的区域以非粘接状态接触,
在上述基板的上述表面和上述第5表面的上述第5非连接区域之间,局部地配置有与上述基板的上述表面及上述第5表面粘接的粘接用突起,
在上述基板的上述表面和上述第1半导体芯片的上述第5表面之间的间隙,填充有底部填充树脂。
6.一种层叠型半导体装置,其特征在于,具备:
第1半导体芯片,其具有具备第1连接区域和除上述第1连接区域以外的第1非连接区域的第1表面;
第2半导体芯片,其具有具备与上述第1连接区域对向的第2连接区域和除上述第2连接区域以外的第2非连接区域的第2表面,层叠在上述第1半导体芯片上;
第1凸起连接部,其设置在上述第1表面的上述第1连接区域和上述第2表面的上述第2连接区域之间,以电气连接上述第1半导体芯片和上述第2半导体芯片;
阻挡兼粘接用突起,其在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域局部地设置,且与上述第1非连接区域及上述第2非连接区域的另一方的区域粘接;和
底部填充树脂,其在上述第1半导体芯片的上述第1表面和上述第2半导体芯片的上述第2表面之间的间隙填充。
7.如权利要求6所述的层叠型半导体装置,其特征在于,
还具备在上述第2半导体芯片上层叠的第3半导体芯片,
上述第2半导体芯片具有具备第3连接区域和除上述第3连接区域以外的第3非连接区域的、位于上述第2表面的相反侧的第3表面,
上述第3半导体芯片具有具备与上述第3连接区域对向的第4连接区域和除上述第4连接区域以外的第4非连接区域的第4表面,且在上述第2半导体芯片上层叠,
上述第2半导体芯片和上述第3半导体芯片通过在上述第3表面的上述第3连接区域和上述第4表面的上述第4连接区域之间设置的第2凸起连接部电气连接,
在上述第2半导体芯片的上述第3表面和上述第3半导体芯片的上述第4表面之间配置有阻挡兼粘接用突起,其在上述第3表面的上述第3非连接区域及上述第4表面的上述第4非连接区域的至少一方的区域局部地设置,且与上述第3非连接区域及上述第4非连接区域的另一方的区域粘接,
在上述第2半导体芯片的上述第3表面和上述第3半导体芯片的上述第4表面之间的间隙,填充有底部填充树脂。
8.如权利要求7所述的层叠型半导体装置,其特征在于,
第3凸起电极经由在上述第2半导体芯片内设置的贯通电极,与第2凸起电极电气连接。
9.如权利要求6所述的层叠型半导体装置,其特征在于,
上述阻挡兼粘接用突起设置在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域,在上述第1非连接区域及上述第2非连接区域的至少另一方的区域设置有机绝缘膜。
10.如权利要求6所述的层叠型半导体装置,其特征在于,
还具备基板,其具有具备连接端子的表面,
上述第1半导体芯片具有具备第5连接区域和除上述第5连接区域以外的第5非连接区域的、位于上述第1表面的相反侧的第5表面,且在上述基板上安装,
上述基板和上述第1半导体芯片通过设置在上述第5表面的上述第5连接区域和上述基板的上述连接端子之间的第3凸起连接部电气连接,
在上述基板的上述表面和上述第1半导体芯片的上述第5表面之间配置有阻挡兼粘接用突起,其在上述第5表面的上述第5非连接区域及上述基板的上述表面的至少一方的区域局部地设置,且与上述第5非连接区域及上述基板的上述表面的另一方的区域粘接,
在上述基板的上述表面和上述第1半导体芯片的上述第5表面之间的间隙,填充有底部填充树脂。
11.一种层叠型半导体装置的制造方法,其特征在于,具备:
准备具有第1表面的第1半导体芯片的步骤,上述第一表面具备第1连接区域、除上述第1连接区域以外的第1非连接区域以及在上述第1连接区域设置的第1凸起电极;
准备具有第2表面的第2半导体芯片的步骤,上述第2表面具备与上述第1连接区域对应的第2连接区域、除上述第2连接区域以外的第2非连接区域以及在上述第2连接区域设置的第2凸起电极;
在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域,局部地形成阻挡用突起及粘接用突起或阻挡兼粘接用突起的步骤;
一边使上述第1凸起电极和上述第2凸起电极对位,一边在上述第1半导体芯片上层叠上述第2半导体芯片的步骤;
一边由上述阻挡用突起或上述阻挡兼粘接用突起维持上述第1半导体芯片的上述第1表面和上述第2半导体芯片的上述第2表面之间的间隙,一边使上述第1凸起电极和上述第2凸起电极接触并加热,将上述第1凸起电极和上述第2凸起电极连接,并使上述粘接用突起或上述阻挡兼粘接用突起与上述第1非连接区域及上述第2非连接区域的另一方的区域粘接的步骤;和
在上述第1半导体芯片的上述第1表面和上述第2半导体芯片的上述第2表面之间的间隙填充底部填充树脂的步骤。
12.如权利要求11所述的层叠型半导体装置的制造方法,其特征在于,
上述阻挡用突起及上述粘接用突起在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域形成,
上述阻挡用突起与上述第1非连接区域及上述第2非连接区域的另一方的区域以非粘接状态接触,
上述粘接用突起与上述第1非连接区域及上述第2非连接区域的另一方的区域粘接。
13.如权利要求11所述的层叠型半导体装置的制造方法,其特征在于,
上述阻挡兼粘接用突起在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域形成,
上述阻挡兼粘接用突起与上述第1非连接区域及上述第2非连接区域的另一方的区域粘接。
14.如权利要求11所述的层叠型半导体装置的制造方法,其特征在于,
上述阻挡用突起或上述阻挡兼粘接用突起设置在上述第1表面的上述第1非连接区域及上述第2表面的上述第2非连接区域的至少一方的区域,在上述第1非连接区域及上述第2非连接区域的至少另一方的区域设置有机绝缘膜。
15.如权利要求11所述的层叠型半导体装置的制造方法,其特征在于,
上述第2半导体芯片具有第3表面,该第3表面具备第3连接区域、除上述第3连接区域以外的第3非连接区域以及在上述第3连接区域设置的第3凸起电极,并位于上述第2表面的相反侧,
上述第3凸起电极经由设置在上述第2半导体芯片内的贯通电极,与上述第2凸起电极电气连接。
16.如权利要求15所述的层叠型半导体装置的制造方法,其特征在于,还具备:
准备具有第4表面的第3半导体芯片的步骤,上述第4表面具备与上述第3连接区域对应的第4连接区域、除上述第4连接区域以外的第4非连接区域以及在上述第4连接区域设置的第4凸起电极;
在上述第3表面的上述第3非连接区域及上述第4表面的上述第4非连接区域的至少一方的区域,局部地形成阻挡用突起及粘接用突起或阻挡兼粘接用突起的步骤;
一边使上述第3凸起电极和上述第4凸起电极对位,一边在上述第2半导体芯片上层叠上述第3半导体芯片的步骤;
一边由上述阻挡用突起或上述阻挡兼粘接用突起维持上述第2半导体芯片和上述第3半导体芯片之间的间隙,一边使上述第3凸起电极和上述第4凸起电极接触并加热,将上述第3凸起电极和上述第4凸起电极连接,并使上述粘接用突起或上述阻挡兼粘接用突起与上述第3非连接区域及上述第4非连接区域的另一方的区域粘接的步骤;和
在上述第2半导体芯片的上述第3表面和上述第3半导体芯片的上述第4表面之间的间隙填充底部填充树脂的步骤。
17.如权利要求16所述的层叠型半导体装置的制造方法,其特征在于,
上述阻挡用突起或上述阻挡兼粘接用突起具有热固化性,
将上述第1凸起电极与上述第2凸起电极接触的上述第1半导体芯片和上述第2半导体芯片的层叠体,以小于上述第1及第2凸起电极的连接温度且上述阻挡用突起或上述阻挡兼粘接用突起开始固化而呈现粘接性的温度压接,从而暂时固定上述第1凸起电极和上述第2凸起电极,
将上述第1凸起电极和上述第2凸起电极被暂时固定且上述第3凸起电极与上述第4凸起电极接触的上述第1半导体芯片和上述第2半导体芯片和上述第3半导体芯片的层叠体,以小于上述第1至第4凸起电极的连接温度且上述阻挡用突起或上述阻挡兼粘接用突起开始固化而呈现粘接性的温度压接,从而暂时固定上述第3凸起电极和上述第4凸起电极,
将上述凸起电极之间被暂时固定的上述第1半导体芯片和上述第2半导体芯片和上述第3半导体芯片的层叠体,加热到上述第1至第4凸起电极的连接温度以上且上述阻挡用突起或上述阻挡兼粘接用突起的热固化温度以上的温度并压接。
18.如权利要求16所述的层叠型半导体装置的制造方法,其特征在于,
上述阻挡用突起或上述阻挡兼粘接用突起具有热固化性,
将上述第1凸起电极与上述第2凸起电极接触的上述第1半导体芯片和上述第2半导体芯片的层叠体,以小于上述第1及第2凸起电极的连接温度且上述阻挡用突起或上述阻挡兼粘接用突起开始固化而呈现粘接性的温度压接,从而暂时固定上述第1凸起电极和上述第2凸起电极,
将上述第1凸起电极和上述第2凸起电极被暂时固定且上述第3凸起电极与上述第4凸起电极接触的上述第1半导体芯片和上述第2半导体芯片和上述第3半导体芯片的层叠体,以小于上述第1至第4凸起电极的连接温度且上述阻挡用突起或上述阻挡兼粘接用突起开始固化而呈现粘接性的温度压接,从而暂时固定上述第3凸起电极和上述第4凸起电极,
将上述凸起电极之间被暂时固定的上述第1半导体芯片和上述第2半导体芯片和上述第3半导体芯片的层叠体,加热到上述阻挡用突起或上述阻挡兼粘接用突起的热固化温度以上的温度,从而使上述粘接用突起或上述阻挡兼粘接用突起固化,
将由上述粘接用突起或上述阻挡兼粘接用突起粘接的上述第1半导体芯片和上述第2半导体芯片和上述第3半导体芯片的层叠体,用上述第1至第4凸起电极的连接温度以上的温度压接或回流焊接。
19.如权利要求16所述的层叠型半导体装置的制造方法,其特征在于,
上述阻挡用突起或上述阻挡兼粘接用突起具有热固化性,
将上述第1凸起电极与上述第2凸起电极接触的上述第1半导体芯片和上述第2半导体芯片的层叠体,以小于上述第1及第2凸起电极的连接温度且上述阻挡用突起或上述阻挡兼粘接用突起开始固化而呈现粘接性的温度压接,从而暂时固定上述第1凸起电极和上述第2凸起电极,
将上述第1凸起电极和上述第2凸起电极被暂时固定且上述第3凸起电极与上述第4凸起电极接触的上述第1半导体芯片和上述第2半导体芯片和上述第3半导体芯片的层叠体,加热到上述第1至第4凸起电极的连接温度以上且上述阻挡用突起或上述阻挡兼粘接用突起的热固化温度以上的温度并压接,从而将上述第1凸起电极和上述第2凸起电极连接,并将上述第3凸起电极和上述第4凸起电极连接。
20.如权利要求11所述的层叠型半导体装置的制造方法,其特征在于,
上述第1半导体芯片具有第5表面,该第5表面具备第5连接区域、除上述第5连接区域以外的第5非连接区域以及在上述第5连接区域设置的第5凸起电极,并位于上述第1表面的相反侧,
一边将上述第5凸起电极与连接端子连接,一边将上述第1半导体芯片安装到具有具备上述连接端子的表面的基板上,
将在上述第5表面的上述第5非连接区域及上述基板的上述表面的至少一方的区域局部地设置的粘接用突起或阻挡兼粘接用突起与上述第5非连接区域及上述基板的上述表面的另一方的区域粘接,
在上述基板的上述表面和上述第1半导体芯片的上述第5表面之间的间隙,填充底部填充树脂。
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