JP3946200B2 - 電子部品の実装方法 - Google Patents
電子部品の実装方法 Download PDFInfo
- Publication number
- JP3946200B2 JP3946200B2 JP2004080202A JP2004080202A JP3946200B2 JP 3946200 B2 JP3946200 B2 JP 3946200B2 JP 2004080202 A JP2004080202 A JP 2004080202A JP 2004080202 A JP2004080202 A JP 2004080202A JP 3946200 B2 JP3946200 B2 JP 3946200B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- circuit board
- metal
- chip
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
次に、同図(3)に示す様に、半田バンプ9を有するICチップ10を用意し、フリップチップボンダーを用いて、前記回路基板上にフェイスダウン実装する。その後、リフローを行い、前記ICチップ10の半田バンプ9を溶融させ、ICチップ10と回路基板15の接続を得る。
次に、同図(4)に示す様に、アンダーフィルとして熱硬化樹脂11をICチップ10と回路基板15の間に注入することで回路基板15にICチップ10がフェースダウン実装される。
2 ニッケル箔
3 銅箔
4 金属基材
5 回路配線パターン
6 絶縁層
7 金属突起
8 本発明による回路基板
9 半田バンプ
10 ICチップ
11 熱硬化樹脂
12 絶縁ベース材
13 銅箔層
14 片面型銅張積層板
15 従来工法による回路基板
Claims (1)
- 第一の導電層と半田が溶融する温度においても溶融しない金属よりなる第二の導電層の間にエッチングストッパー層となる異種金属層を有する金属箔を用意し、前記第一の導電層にエッチングにより電子部品接続パッドを含む回路配線パターンを形成し、接着性絶縁樹脂を前記回路配線パターン側に接着し、前記第二の導電層をエッチングすることにより金属突起を前記電子部品接続パッド近傍に形成し、その後前記エッチングストッパー層となる前記異種金属層を除去することにより前記金属突起が形成された回路基板を準備し、前記回路基板の前記電子部品接続パッド上に半田バンプを有する電子部品を前記電子部品接続パッドに前記半田バンプと前記電子部品接続パッドとを位置合わせして搭載し、その後、前記電子部品が搭載された前記回路基板を前記半田バンプが溶融する温度でリフローした際に前記金属突起で前記回路基板と前記電子部品の間に前記金属突起の高さに等しい隙間を形成することを特徴とする電子部品の実装方法
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004080202A JP3946200B2 (ja) | 2004-03-19 | 2004-03-19 | 電子部品の実装方法 |
TW93134892A TW200532879A (en) | 2004-03-19 | 2004-11-15 | Circuit substrate and method for mounting electronic element |
CN 200510056005 CN100490610C (zh) | 2004-03-19 | 2005-03-21 | 电路基板的制造方法及电子零件的安装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004080202A JP3946200B2 (ja) | 2004-03-19 | 2004-03-19 | 電子部品の実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005268594A JP2005268594A (ja) | 2005-09-29 |
JP3946200B2 true JP3946200B2 (ja) | 2007-07-18 |
Family
ID=35050399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004080202A Expired - Fee Related JP3946200B2 (ja) | 2004-03-19 | 2004-03-19 | 電子部品の実装方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP3946200B2 (ja) |
CN (1) | CN100490610C (ja) |
TW (1) | TW200532879A (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080116587A1 (en) * | 2006-11-16 | 2008-05-22 | Chun Ho Fan | Conductor polymer composite carrier with isoproperty conductive columns |
US20090115060A1 (en) | 2007-11-01 | 2009-05-07 | Infineon Technologies Ag | Integrated circuit device and method |
TWI577260B (zh) * | 2010-03-16 | 2017-04-01 | Unitech Printed Circuit Board Corp | A multi - layer circuit board manufacturing method for embedded electronic components |
US8710654B2 (en) | 2011-05-26 | 2014-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
KR101709468B1 (ko) * | 2015-06-19 | 2017-03-09 | 주식회사 심텍 | Pop 구조용 인쇄회로기판, 그 제조 방법 및 이를 이용하는 소자 패키지 |
-
2004
- 2004-03-19 JP JP2004080202A patent/JP3946200B2/ja not_active Expired - Fee Related
- 2004-11-15 TW TW93134892A patent/TW200532879A/zh not_active IP Right Cessation
-
2005
- 2005-03-21 CN CN 200510056005 patent/CN100490610C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005268594A (ja) | 2005-09-29 |
CN100490610C (zh) | 2009-05-20 |
TWI292948B (ja) | 2008-01-21 |
TW200532879A (en) | 2005-10-01 |
CN1678173A (zh) | 2005-10-05 |
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