JP4744293B2 - 半導体素子が直交配置された回路基板の製造方法 - Google Patents
半導体素子が直交配置された回路基板の製造方法 Download PDFInfo
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- JP4744293B2 JP4744293B2 JP2005376556A JP2005376556A JP4744293B2 JP 4744293 B2 JP4744293 B2 JP 4744293B2 JP 2005376556 A JP2005376556 A JP 2005376556A JP 2005376556 A JP2005376556 A JP 2005376556A JP 4744293 B2 JP4744293 B2 JP 4744293B2
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- Japan
- Prior art keywords
- semiconductor element
- circuit board
- solder
- semiconductor
- semiconductor elements
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
Description
前記回路基板の第2の面に長方形の底面を有する第2の半導体素子が実装される、半導体素子が直交配置された回路基板の製造方法であって、
前記第1の半導体素子は、ボールグリッド型で、前記第2の半導体素子は、前記第1の半導体素子の電極ピッチよりも広いもので、前記第1の半導体素子の長手方向と前記第2の半導体素子の長手方向が直交配置され、
粘着性樹脂に固着された回路基板の第1の面に、前記第1の半導体素子を半田を介して接続し、
前記第1の半導体素子を下側にして粘着性樹脂に固定し、前記回路基板の前記第2の面に、前記第2の半導体素子を半田を介して接続する事で解決するものである。
4a、4b、4c、4d、4e 開口部
5a、5b、5c、5d フレーム
6b、6c、6d ランド
7a 第1の領域
7b 第2の領域
10 回路基板
11a 第1の半導体素子
11b 第2の半導体素子
12 粘着性樹脂
13aX、13aY、13bX、13bY 半田ペースト
101 回路基板
102 コア材
103 第1の配線層
104 第1の貫通孔
105 樹脂
106 第2の配線層
107 第2の貫通孔
108 第2の樹脂
109 電極
110 金メッキ
111 半導体素子
111a 第1の半導体素子
111b 第2の半導体素子
112 半田メッキ
201 マザー基板
202 くり抜き部
203 半田ランド
204 ボンディングパッド
205 金属細線
206 302 半田
301 サイド電極
303 電極
401 第1の配線
402 第2の配線
501 粘着性樹脂
Claims (4)
- 回路基板の第1の面に長方形の底面を有する第1の半導体素子が実装され、
前記回路基板の第2の面に長方形の底面を有する第2の半導体素子が実装される、半導体素子が直交配置された回路基板の製造方法であって、
前記第1の半導体素子は、ボールグリッド型で、前記第2の半導体素子は、前記第1の半導体素子の電極ピッチよりも広いもので、前記第1の半導体素子の長手方向と前記第2の半導体素子の長手方向が直交配置され、
粘着性樹脂に固着された回路基板の第1の面に、前記第1の半導体素子を半田を介して接続し、
前記第1の半導体素子を下側にして粘着性樹脂に固定し、前記回路基板の前記第2の面に、前記第2の半導体素子を半田を介して接続する事を特徴とした半導体素子が直交配置された回路基板の製造方法。 - 前記第2の半導体素子は、リードにより実装されるものである請求項1に記載の半導体素子が直交配置された回路基板の製造方法。
- 前記第2の半導体素子は、QFPまたはSIPである請求項2に記載の半導体素子が直交配置された回路基板の製造方法。
- 前記第1の半導体素子と前記第2の半導体素子は、十字状、T字状またはL字状に配置される請求項3に記載の半導体素子が直交配置された回路基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005376556A JP4744293B2 (ja) | 2005-12-27 | 2005-12-27 | 半導体素子が直交配置された回路基板の製造方法 |
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JP2005376556A JP4744293B2 (ja) | 2005-12-27 | 2005-12-27 | 半導体素子が直交配置された回路基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007180245A JP2007180245A (ja) | 2007-07-12 |
JP4744293B2 true JP4744293B2 (ja) | 2011-08-10 |
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JP2005376556A Expired - Fee Related JP4744293B2 (ja) | 2005-12-27 | 2005-12-27 | 半導体素子が直交配置された回路基板の製造方法 |
Country Status (1)
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JP (1) | JP4744293B2 (ja) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3490303B2 (ja) * | 1997-09-16 | 2004-01-26 | 松下電器産業株式会社 | 半導体装置の実装体 |
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