JP2007180245A - 回路基板および回路装置 - Google Patents
回路基板および回路装置 Download PDFInfo
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- JP2007180245A JP2007180245A JP2005376556A JP2005376556A JP2007180245A JP 2007180245 A JP2007180245 A JP 2007180245A JP 2005376556 A JP2005376556 A JP 2005376556A JP 2005376556 A JP2005376556 A JP 2005376556A JP 2007180245 A JP2007180245 A JP 2007180245A
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- Prior art keywords
- circuit board
- semiconductor element
- solder
- semiconductor
- board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
【解決手段】本発明では、両面回路基板に、長方形の底面を有する半導体素子を用い、互いに十字状に直交するように実装している。この構成により、変形を低減することが可能にした。さらにはT字状やL字状に配置しても、上記効果を奏することができる。また、一つの面に複数の半導体素子が第1の実装面に実装される場合には、第2の実装面に、それら半導体素子の少なくとも2つの一部領域および境界部に重畳するように、半導体素子を実装することで、回路基板の変形を低減する。
【選択図】図1
Description
4a、4b、4c、4d、4e 開口部
5a、5b、5c、5d フレーム
6b、6c、6d ランド
7a 第1の領域
7b 第2の領域
10 回路基板
11a 第1の半導体素子
11b 第2の半導体素子
12 粘着性樹脂
13aX、13aY、13bX、13bY 半田ペースト
101 回路基板
102 コア材
103 第1の配線層
104 第1の貫通孔
105 樹脂
106 第2の配線層
107 第2の貫通孔
108 第2の樹脂
109 電極
110 金メッキ
111 半導体素子
111a 第1の半導体素子
111b 第2の半導体素子
112 半田メッキ
201 マザー基板
202 くり抜き部
203 半田ランド
204 ボンディングパッド
205 金属細線
206 302 半田
301 サイド電極
303 電極
401 第1の配線
402 第2の配線
501 粘着性樹脂
Claims (4)
- 回路基板の第1の面に第1の半導体素子が実装され、
前記第1の面の裏面に長方形の底面を有する第2の半導体素子が実装される回路基板であって、
前記第1の半導体素子は、前記第2の半導体素子に重畳し、
前記第1の半導体素子は、前記第2の半導体素子の短辺に平行な方向に延在するよう、実装されることを特徴とする回路基板。 - 回路基板の第1の面に複数の第1の半導体素子が実装され、
前記第1の面の裏面に第2の半導体素子が実装される回路基板であって、
前記複数の第1の半導体素子のうち、少なくとも2つの半導体素子の一部領域と、前記2つの半導体素子の境界領域が前記第2の半導体素子重畳するように、実装されることを特徴とする回路基板。 - 回路基板の第1の面に第1の半導体素子が第1の半田を介して実装され、
前記第1の面の裏面に第2の半導体素子が第2の半田を介して実装される回路基板であって、
前記第1の半田は前記第2の半田より融点温度が低いことを特徴とする回路基板。 - 回路基板の第1の面に第1の半導体素子が第1の半田を介して実装され、前記第1の面の裏面に第2の半導体素子が第1の半田を介して実装される回路基板と、
マザー基板を有し、
前記回路基板とマザー基板が第1の半田より融点温度が低い第2の半田を介して実装されてなる回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005376556A JP4744293B2 (ja) | 2005-12-27 | 2005-12-27 | 半導体素子が直交配置された回路基板の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005376556A JP4744293B2 (ja) | 2005-12-27 | 2005-12-27 | 半導体素子が直交配置された回路基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007180245A true JP2007180245A (ja) | 2007-07-12 |
JP4744293B2 JP4744293B2 (ja) | 2011-08-10 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005376556A Expired - Fee Related JP4744293B2 (ja) | 2005-12-27 | 2005-12-27 | 半導体素子が直交配置された回路基板の製造方法 |
Country Status (1)
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JP (1) | JP4744293B2 (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11154728A (ja) * | 1997-09-16 | 1999-06-08 | Matsushita Electric Ind Co Ltd | 半導体装置およびその実装体 |
-
2005
- 2005-12-27 JP JP2005376556A patent/JP4744293B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11154728A (ja) * | 1997-09-16 | 1999-06-08 | Matsushita Electric Ind Co Ltd | 半導体装置およびその実装体 |
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JP4744293B2 (ja) | 2011-08-10 |
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