JP4802679B2 - 電子回路基板の実装方法 - Google Patents
電子回路基板の実装方法 Download PDFInfo
- Publication number
- JP4802679B2 JP4802679B2 JP2005333887A JP2005333887A JP4802679B2 JP 4802679 B2 JP4802679 B2 JP 4802679B2 JP 2005333887 A JP2005333887 A JP 2005333887A JP 2005333887 A JP2005333887 A JP 2005333887A JP 4802679 B2 JP4802679 B2 JP 4802679B2
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- board
- wiring layer
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Description
2、3、9 配線層
4 貫通スルーホール配線部
5 半導体素子
6 熱硬化性樹脂
7 液状フラックス
8 メインプリント配線板
11 受動部品
12 半導体パッケージ
13 はんだペースト
14 はんだボール
Claims (1)
- 上面および下面に配線層を設けると共に、前記上面の配線層に半導体素子および受動部品がはんだ付けにより実装される第1のプリント配線板と、前記第1のプリント配線板の下面の配線層がはんだ付けされる配線層を上面に有する第2のプリント配線板と、前記第1のプリント配線板の上面の配線層に接続端子がはんだ付けされる前記半導体素子とは別の半導体パッケージとを備えた電子回路基板の実装方法であって、
前記第1のプリント配線板に前記受動部品の端子がはんだ付けされる貫通スルーホール配線部を設け、
かつ前記第2のプリント配線板の配線層にはんだペーストを配置した後、前記半導体素子を実装した第1のプリント配線板を前記第2のプリント配線板上に、第1のプリント配線板の下面の配線層および貫通スルーホール配線部が前記第2のプリント配線板の配線層に前記はんだペーストを介して対向するように配置し、さらに前記受動部品を第1のプリント配線板の貫通スルーホール配線部上に配置すると共に、接続端子にはんだボールを形成した前記半導体パッケージを第1のプリント配線板上に配置し、
その後前記第1のプリント配線板および第2のプリント配線板をリフロー炉で加熱することにより、前記はんだペーストを溶融させ、溶融したはんだペーストを前記貫通スルーホール配線部を通して吸い上げて前記受動部品の端子を貫通スルーホール配線部にはんだ付けすると共に、第1のプリント配線板の下面の配線層と第2のプリント配線板の配線層とをはんだ付けし、かつ前記半導体パッケージのはんだボールを溶融させて前記第1のプリント配線板にはんだ付けすることを特徴とする電子回路基板の実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005333887A JP4802679B2 (ja) | 2005-11-18 | 2005-11-18 | 電子回路基板の実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005333887A JP4802679B2 (ja) | 2005-11-18 | 2005-11-18 | 電子回路基板の実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007142146A JP2007142146A (ja) | 2007-06-07 |
JP4802679B2 true JP4802679B2 (ja) | 2011-10-26 |
Family
ID=38204660
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005333887A Expired - Fee Related JP4802679B2 (ja) | 2005-11-18 | 2005-11-18 | 電子回路基板の実装方法 |
Country Status (1)
Country | Link |
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JP (1) | JP4802679B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100764682B1 (ko) * | 2006-02-14 | 2007-10-08 | 인티그런트 테크놀로지즈(주) | 집적회로 칩 및 패키지. |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6167292A (ja) * | 1984-09-10 | 1986-04-07 | 株式会社日立製作所 | 面付け部品の実装方法および装置 |
JPH0184463U (ja) * | 1987-11-27 | 1989-06-05 | ||
JP3116273B2 (ja) * | 1996-04-26 | 2000-12-11 | 日本特殊陶業株式会社 | 中継基板、その製造方法、基板と中継基板と取付基板とからなる構造体、基板と中継基板の接続体 |
JP3879347B2 (ja) * | 1999-12-20 | 2007-02-14 | 富士電機システムズ株式会社 | モジュール基板接合方法 |
JP4408598B2 (ja) * | 2001-09-28 | 2010-02-03 | パナソニック株式会社 | カード型記録媒体 |
JP2003243562A (ja) * | 2002-02-21 | 2003-08-29 | Omron Corp | 樹脂封止基板とその製造方法および該基板中間製品とその製造方法 |
JP2004335624A (ja) * | 2003-05-06 | 2004-11-25 | Hitachi Ltd | 半導体モジュール |
-
2005
- 2005-11-18 JP JP2005333887A patent/JP4802679B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2007142146A (ja) | 2007-06-07 |
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