CN111630645B - 半导体装置、及半导体装置的制造方法 - Google Patents

半导体装置、及半导体装置的制造方法 Download PDF

Info

Publication number
CN111630645B
CN111630645B CN201880087178.0A CN201880087178A CN111630645B CN 111630645 B CN111630645 B CN 111630645B CN 201880087178 A CN201880087178 A CN 201880087178A CN 111630645 B CN111630645 B CN 111630645B
Authority
CN
China
Prior art keywords
semiconductor chip
wall portion
underfill resin
outer edge
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880087178.0A
Other languages
English (en)
Other versions
CN111630645A (zh
Inventor
高木慎一郎
米田康人
村松雅治
井上直
山本宙和
中田慎一
小山卓雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hamamatsu Photonics KK
Original Assignee
Hamamatsu Photonics KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics KK filed Critical Hamamatsu Photonics KK
Publication of CN111630645A publication Critical patent/CN111630645A/zh
Application granted granted Critical
Publication of CN111630645B publication Critical patent/CN111630645B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

本发明提供一种半导体装置，其具备：支承体，其具有安装区域；半导体芯片，其经由规定距离配置于安装区域上；凸块，其配置于支承体与半导体芯片之间；壁部，其以沿半导体芯片的外缘的一部分的方式配置于支承体与半导体芯片之间；及底部填充树脂层，其配置于支承体与半导体芯片之间；底部填充树脂层覆盖壁部的外侧的侧面。

Description

半导体装置、及半导体装置的制造方法
技术领域
本发明关于一种半导体装置、及半导体装置的制造方法。
背景技术
作为在第一半导体芯片的安装区域安装有第二半导体芯片的半导体装置，已知在通过凸块接合的第一半导体芯片与第二半导体芯片之间配置有底部填充树脂层的装置。制造此种半导体装置时，有时为了在第一半导体芯片与第二半导体芯片之间确实地配置底部填充树脂层，使用真空填充法(例如，参考专利文献1)。
真空填充法中，在真空环境中，以沿第二半导体芯片的外缘的方式在第一半导体芯片的安装区域以环状配置底部填充树脂剂，在第一半导体芯片与第二半导体芯片之间形成密闭空间。其后，通过向大气压环境释放，向对应于该密闭空间的区域填充底部填充树脂剂，通过使底部填充树脂剂固化，在第一半导体芯片与第二半导体芯片之间形成底部填充树脂层。
[现有技术文献]
[专利文献]
[专利文献1]日本专利特开平8-264587号公报
发明内容
[发明所要解决的问题]
然而，制造如上述的半导体装置时，在为了确实地配置底部填充树脂层而使用真空填充法的情形时，有阻碍装置尺寸的小型化的担忧。其理由为由于为了以沿第二半导体芯片的外缘的方式在第一半导体芯片的安装区域以环状配置底部填充树脂剂，需沿第二半导体芯片的外缘的所有部分扩宽第一半导体芯片的安装区域。
本发明的目的在于提供一种谋求可靠性的提高及小型化的半导体装置、以及此种半导体装置的制造方法。
[解决问题的技术手段]
本发明的一侧面的半导体装置具备：支承体，其具有安装区域；半导体芯片，其经由规定距离配置于安装区域上；凸块，其配置于支承体与半导体芯片之间；壁部，其以沿半导体芯片的外缘的一部分的方式配置于支承体与半导体芯片之间；及底部填充树脂层，其配置于支承体与半导体芯片之间。底部填充树脂层覆盖壁部的外侧的侧面。
该半导体装置中，例如于制造时使用真空填充法的情形时，能够通过以沿半导体芯片的外缘的一部分的方式配置的壁部、及以沿半导体芯片的外缘中除该一部分以外的其他部分的方式配置的底部填充树脂剂，在支承体与半导体芯片之间形成密闭空间。由此，无需沿半导体芯片的外缘的一部分扩宽支承体的安装区域。因此，该半导体装置中，可实现底部填充树脂层的确实的配置、及装置尺寸的小型化。进而，该半导体装置中，由于底部填充树脂层覆盖壁部的外侧的侧面，故而可实现壁部的劣化的抑制、及支承体与半导体芯片的接合强度的提高。通过以上，根据该半导体装置，可谋求可靠性的提高及小型化。
本发明的一侧面的半导体装置中，底部填充树脂层可覆盖壁部的外侧的侧面的整体。根据该构成，可更加确实地实现壁部的劣化的抑制、及支承体与半导体芯片的接合强度的提高。
本发明的一侧面的半导体装置中，壁部的材料可与凸块的材料相同。根据该构成，可抑制由凸块与壁部之间的热膨胀系数的差所导致的破损等。另外，凸块及壁部的形成较容易。
本发明的一侧面的半导体装置中，在自支承体与半导体芯片相对的方向观察的情形时，壁部的外侧的侧面可较半导体芯片的外缘的一部分更位于内侧。根据该构成，由于以壁部的外侧的侧面为底面的槽以沿半导体芯片的外缘的一部分的方式形成，故而底部填充树脂层中覆盖壁部的外侧的侧面的部分稳定，同时有助于小型化的该部分的突出量更小。
本发明的一侧面的半导体装置中，底部填充树脂层包括：第一填角部，其以沿半导体芯片的外缘的一部分的方式在该一部分的外侧配置于安装区域；及第二填角部，其以沿半导体芯片的外缘中除一部分以外的其他部分的方式在该其他部分的外侧配置于安装区域。第一填角部的宽度可小于第二填角部的宽度。根据该构成，可维持装置尺寸的小型化，并实现支承体与半导体芯片的接合平衡及接合强度的提高。
本发明的一侧面的半导体装置中，第一填角部及第二填角部可到达半导体芯片的侧面。根据该构成，可更加确实地实现支承体与半导体芯片的接合平衡及接合强度的提高。
本发明的一侧面的半导体装置中，支承体进而具有与安装区域相邻的受光区域，半导体芯片的外缘的一部分可为半导体芯片的外缘中以沿受光区域的方式延伸的部分。根据该构成，半导体芯片与受光区域可接近配置。
本发明的一侧面的半导体装置进而在安装区域具备与半导体芯片相邻的另外的半导体芯片，半导体芯片的外缘的一部分可为半导体芯片的外缘中以沿另外的半导体芯片的方式延伸的部分。根据该构成，半导体芯片与另外的半导体芯片可接近配置。
本发明的一侧面的半导体装置中，支承体进而具有与安装区域相邻的端子区域，半导体芯片的外缘的一部分可为半导体芯片的外缘中以沿端子区域的方式延伸的部分。根据该构成，半导体芯片与端子区域可接近配置。
本发明的一侧面的半导体装置的制造方法具备：第一工序，其在支承体所具有的安装区域上，经由规定距离配置半导体芯片，通过配置于支承体与半导体芯片之间的凸块、及以沿半导体芯片的外缘的一部分的方式配置于支承体与半导体芯片之间的壁部，接合支承体与半导体芯片；第二工序，其在第一气压的环境中，以沿半导体芯片的外缘中除一部分以外的其他部分的方式在其他部分的外侧将底部填充树脂剂配置于安装区域，通过壁部及底部填充树脂剂，在支承体与半导体芯片之间形成密闭空间；及第三工序，其通过配置于高于上述第一气压的第二气压的环境，向与密闭空间对应的区域填充底部填充树脂剂，通过使底部填充树脂剂固化，在支承体与半导体芯片之间配置底部填充树脂层。
该半导体装置的制造方法中，通过以沿半导体芯片的外缘的一部分的方式配置的壁部、及以沿半导体芯片的外缘中除该一部分以外的其他部分的方式配置的底部填充树脂剂，在支承体与半导体芯片之间形成密闭空间。由此，无需沿半导体芯片的外缘的一部分扩宽支承体的安装区域。因此，根据该半导体装置的制造方法，可获得实现可靠性的提高、及装置尺寸的小型化的半导体装置。
[发明的效果]
根据本发明，能够提供谋求了可靠性的提高及小型化的半导体装置、以及此种半导体装置的制造方法。
附图说明
图1为一实施方式的半导体装置的俯视图。
图2为沿图1所示的II-II线的半导体装置的剖视图。
图3的(a)为表示图1所示的半导体装置的制造方法的一工序的俯视图。图3的(b)为表示图1所示的半导体装置的制造方法的一工序的剖视图。
图4的(a)为表示图1所示的半导体装置的制造方法的一工序的俯视图。图4的(b)为表示图1所示的半导体装置的制造方法的一工序的剖视图。
图5的(a)为表示图1所示的半导体装置的制造方法的一工序的俯视图。图5的(b)为表示图1所示的半导体装置的制造方法的一工序的剖视图。
图6的(a)为表示图1所示的半导体装置的制造方法的一工序的俯视图。图6的(b)为表示图1所示的半导体装置的制造方法的一工序的剖视图。
图7的(a)及(b)为其他实施方式的半导体装置的一部分的剖视图。
图8为其他实施方式的半导体装置的俯视图。
图9为沿图8所示的IX-IX线的半导体装置的剖视图。
图10的(a)、(b)及(c)为其他实施方式的半导体装置的俯视图。
具体实施方式
以下，对本发明的实施方式，参考图式进行详细说明。再者，在各图中，对相同或相当部分标记相同符号，省略重复说明。
[半导体装置的构成]
如图1及图2所示，半导体装置1具备第一半导体芯片(支承体)10及第二半导体芯片(半导体芯片)20。第一半导体芯片10例如为影像传感器。第二半导体芯片20例如为读出电路(ROIC，read-out integrated circuit)。第一半导体芯片10与第二半导体芯片20通过倒装芯片接合相互接合。
第一半导体芯片10为在半导体基板11的表面11a侧的部分构建有受光部12及电路部13的半导体芯片。受光部12包括多个像素。电路部13包括设置于表面11a的多个电极垫。所对应的像素与电极垫通过构建于半导体基板11的配线电性连接。再者，各电极垫存在包括凸块下金属的情形。
半导体基板11的表面11a设置有受光区域14及安装区域15。受光区域14为对应于受光部12的区域。安装区域15为对应于电路部13的区域。受光区域14与安装区域15相邻。作为一例，半导体基板11形成为矩形板状(例如20mm×15mm×1mm(厚度)左右的矩形板状)，矩形状的受光区域14在矩形状的表面11a与矩形状的安装区域15相邻。
第二半导体芯片20为在半导体基板21的表面21a侧的部分构建有电路部23的半导体芯片。电路部23包括设置于表面21a的多个电极垫。作为一例，半导体基板21形成为矩形板状(例如10mm×10mm×1mm(厚度)左右的矩形板状)。再者，各电极垫存在包括凸块下金属的情形。
第二半导体芯片20在半导体基板11的表面11a与半导体基板21的表面21a相对的状态下，经由规定距离(例如5μm左右)配置于第一半导体芯片10的安装区域15上。在第一半导体芯片10与第二半导体芯片20相对的方向A(以下，简称为「方向A」)上，设置于半导体基板11的表面11a的多个电极垫与设置于半导体基板21的表面21a的多个电极垫一对一相对。相对的电极垫彼此通过凸块2电性且物理性地连接。各凸块2的高度及宽度例如为5μm左右，相邻的凸块2的中心间距离例如为20μm左右。
第一半导体芯片10与第二半导体芯片20之间，除多个凸块2以外，还配置有1个壁部3。壁部3的高度及宽度例如为5μm左右。第一半导体芯片10与第二半导体芯片20通过多个凸块2及1个壁部3接合。即，壁部3与第一半导体芯片10及第二半导体芯片20抵接。壁部3的材料与凸块2的材料(例如SnAg、SnAgCu、SnBi、In等)相同。但是，壁部3物理性地连接于第一半导体芯片10及第二半导体芯片20的各者，但未电性连接于第一半导体芯片10及第二半导体芯片20的各者。
壁部3以沿第二半导体芯片20的外缘22的一部分22a的方式配置。外缘22为自方向A所见的第二半导体芯片20的外缘。外缘22在自方向A观察的情形时包含于第一半导体芯片10的安装区域15的外缘。外缘22的一部分22a为在自方向A观察的情形时以沿受光区域14的方式延伸的部分。作为一例，外缘22的一部分22a在自方向A观察的情形时，为矩形状的外缘22的受光区域14侧的一边，以沿矩形状的受光区域14的安装区域15侧的一边的方式延伸。
壁部3的外侧的侧面3a(以下，简称为「侧面3a」)在自方向A观察的情形时，较第二半导体芯片20的外缘22的一部分22a更位于内侧。自方向A所见的外缘22的一部分22a与壁部3的侧面3a的距离为10～100μm左右。再者，外侧为在自方向A观察的情形时相对于第二半导体芯片20的中心(重心)而言第二半导体芯片20的外缘22所位于的侧，内侧为在自方向A观察的情形时相对于第二半导体芯片20的外缘22而言第二半导体芯片20的中心(重心)所位于的侧。
第一半导体芯片10与第二半导体芯片20之间配置有底部填充树脂层4。底部填充树脂层4覆盖壁部3的侧面3a的整体。在底部填充树脂层4中覆盖壁部3的侧面3a的部分中，自方向A所见的该部分的宽度(垂直于侧面3a的方向的宽度)自壁部3的一端部3b及另一端部3c的各者越接近壁部3的侧面3a的中央部3d则越小。但，自方向A所见的该部分的宽度也可大致固定。
底部填充树脂层4的外缘设置有第一填角部4a及第二填角部4b。第一填角部4a为以沿第二半导体芯片20的外缘22的一部分22a的方式在该一部分22a的外侧配置于第一半导体芯片10的安装区域15的部分。第二填角部4b为以沿第二半导体芯片20的外缘22中除一部分22a以外的其他部分22b的方式在该其他部分22b的外侧配置于第一半导体芯片10的安装区域15的部分。
第一填角部4a及第二填角部4b到达第二半导体芯片20的侧面20a(即，半导体基板21的侧面)。第一填角部4a及第二填角部4b的各者的高度(距安装区域15的高度)越靠外侧越小。第一填角部4a的高度H1小于第二填角部4b的高度H2。第一填角部4a的宽度W1小于第二填角部4b的宽度W2。再者，高度H1、H2为距安装区域15的高度的最大值。宽度W1、W2为在自方向A观察的情形时自第二半导体芯片20的侧面20a向外侧突出的宽度的最大值。
[半导体装置的制造方法]
如图3所示，准备设置有各凸块2的一部分及壁部3的一部分的第一半导体芯片10、以及设置有各凸块2的一部分及壁部3的一部分的第二半导体芯片20。然后，在第一半导体芯片10的安装区域15上经由规定距离配置第二半导体芯片20，使所对应的凸块2的一部分彼此接触，同时使壁部3的一部分彼此接触。然后，如图4所示，通过加热，使所对应的凸块2的一部分彼此一体化，同时使壁部3的一部分彼此一体化，通过多个凸块2及1个壁部3，接合第一半导体芯片10与第二半导体芯片20(第一工序)。
然后，通过真空填充法，在第一半导体芯片10与第二半导体芯片20之间配置底部填充树脂层4。即，如图5所示，在真空环境(较维持于规定真空度的大气压为低压的环境)(第一气压的环境)中，以壁部3的一端部3b的附近为起点、壁部3的另一端部3c的附近为终点的方式，沿第二半导体芯片20的外缘22的其他部分22b，向第一半导体芯片10的安装区域15供给底部填充树脂剂40。该底部填充树脂剂40的供给通过使分注器50移行而实施。由此，在真空环境中，以沿外缘22的其他部分22b的方式在该其他部分22b的外侧将底部填充树脂剂40配置于安装区域15，通过壁部3及底部填充树脂剂40，在第一半导体芯片10与第二半导体芯片20之间形成密闭空间S(第二工序)。
底部填充树脂剂40的供给的起点需以底部填充树脂剂40通过毛细管现象到达壁部3的一端部3b的程度为该端部3b的附近。同样地，底部填充树脂剂40的供给的终点需以底部填充树脂剂40通过毛细管现象到达壁部3的另一端部3c的程度为该端部3c的附近。底部填充树脂剂40的供给的起点与壁部3的一端部3b的距离、及底部填充树脂剂40的供给的终点与壁部3的另一端部3c的距离通过第一半导体芯片10与第二半导体芯片20的距离、底部填充树脂剂40的粘度等设定。再者，若壁部3的一端部3b与第二半导体芯片20的外缘22的最短距离、及壁部3的另一端部3c与第二半导体芯片20的外缘22的最短距离分别为10～100μm左右(未达第一半导体芯片10与第二半导体芯片20的距离的20倍左右)，则通过毛细管现象可使底部填充树脂剂40到达壁部3的一端部3b及另一端部3c，可形成密闭空间S。另外，在自方向A观察的情形时，在壁部3的一端部3b侧，以安装区域15中沿第二半导体芯片20的外缘22的环状区域与壁部3的侧面3a的延长线交叉的部分为底部填充树脂剂40的供给的起点，在自方向A观察的情形时，在壁部3的另一端部3b侧，以安装区域15中沿第二半导体芯片20的外缘22的环状区域与壁部3的侧面3a的延长线交叉的部分为底部填充树脂剂40的供给的终点，则在后述的第三工序中，底部填充树脂剂40的一部分易于沿壁部3的侧面3a自壁部3的一端部3b及另一端部3c的各者向壁部3的侧面3a的中央部3d行进。
然后，通过解除真空环境释放至大气压，将通过壁部3及底部填充树脂剂40形成密闭空间S的第一半导体芯片10及第二半导体芯片20配置于大气压环境。通过配置于该大气压环境(配置于高于第一气压的第二气压的环境)，如图6所示，向对应于密闭空间S的区域填充底部填充树脂剂40。此时，底部填充树脂剂40的一部分沿壁部3的侧面3a自壁部3的一端部3b及另一端部3c的各者向壁部3的侧面3a的中央部3d行进，覆盖该侧面3a的整体。底部填充树脂剂40向对应于密闭空间S的区域的行进取决于密闭空间S的内外的压力差，沿壁部3的侧面3a的底部填充树脂剂40的行进取决于毛细管现象。然后，通过使底部填充树脂剂40固化形成底部填充树脂层4，在第一半导体芯片10与第二半导体芯片20之间配置底部填充树脂层4(第三工序)。再者，在使底部填充树脂剂40热固化时，也存在底部填充树脂剂40的一部分通过毛细管现象沿壁部3的侧面3a行进的情形。通过以上，制造半导体装置1。
[作用及效果]
半导体装置1中，例如于制造时使用真空填充法的情形时，能够通过以沿第二半导体芯片20的外缘22的一部分22a的方式配置的壁部3、及以沿第二半导体芯片20的外缘22的其他部分22b的方式配置的底部填充树脂剂40，在第一半导体芯片10与第二半导体芯片20之间形成密闭空间S。由此，无需沿第二半导体芯片20的外缘22的一部分22a扩宽第一半导体芯片10的安装区域15。因此，半导体装置1中，可实现底部填充树脂层4的确实的配置、及装置尺寸的小型化。进而，半导体装置1中，由于底部填充树脂层4覆盖壁部3的侧面3a的整体，故而可实现壁部3的劣化的抑制、及第一半导体芯片10与第二半导体芯片20的接合强度(例如，对冲击等的耐性)的提高。通过以上，根据半导体装置1，可谋求可靠性的提高及小型化。
另外，半导体装置1中，第二半导体芯片20的外缘22的一部分22a为第二半导体芯片20的外缘22中以沿受光区域14的方式延伸的部分。通过该构成，可防止底部填充树脂层4向受光区域14上突出，且第二半导体芯片20与受光区域14可接近配置。第二半导体芯片20与受光区域14的接近配置，不用说装置尺寸的小型化，也有助于由受光部12与电路部13之间的配线长度的缩短所导致的噪声产生的抑制。
另外，半导体装置1中，壁部3的材料与凸块2的材料相同。通过该构成，可抑制由凸块2与壁部3之间的热膨胀系数的差所导致的破损等。另外，凸块2及壁部3的形成较容易。例如，在上述半导体装置1的制造方法的第一工序中，可同时(以同一工序)实施第一半导体芯片10及第二半导体芯片20的各者的各凸块2的一部分的形成及壁部3的一部分的形成，可同时(以同一工序)实施所对应的凸块2的一部分彼此的一体化及壁部3的一部分彼此的一体化。
另外，半导体装置1中，在自方向A观察的情形时，壁部3的侧面3a较第二半导体芯片20的外缘22的一部分22a更位于内侧。通过该构成，以壁部3的侧面3a为底面的槽以沿外缘22的一部分22a的方式形成，故而底部填充树脂层4中覆盖壁部3的侧面3a的部分稳定，同时有助于小型化的该部分的突出量更小。另外，由于以壁部3的侧面3a为底面的槽以沿外缘22的一部分22a的方式形成，故而例如，在上述半导体装置1的制造方法的第三工序中，易于通过毛细管现象使底部填充树脂剂40沿壁部3的侧面3a行进。进而，例如，在上述半导体装置1的制造方法的第一工序中，在多个第二半导体芯片20以晶圆而存在的状态下在第二半导体芯片20形成各凸块2的一部分及壁部3的一部分，其后，在如将晶圆切割为多个第二半导体芯片20的情形时，可确实地防止因切割而使壁部3的一部分损伤。
另外，半导体装置1中，底部填充树脂层4包括以沿第二半导体芯片20的外缘22的一部分22a的方式配置的第一填角部4a、及以沿第二半导体芯片20的外缘22的其他部分22b的方式配置的第二填角部4b，第一填角部4a的宽度小于第二填角部4b的宽度。通过该构成，可维持装置尺寸的小型化，并实现第一半导体芯片10与第二半导体芯片20的接合平衡及接合强度的提高。
另外，半导体装置1中，第一填角部4a及第二填角部4b到达第二半导体芯片20的侧面20a。通过该构成，更加确实地实现第一半导体芯片10与第二半导体芯片20的接合平衡及接合强度的提高。
另外，半导体装置1的制造方法中，通过以沿第二半导体芯片20的外缘22的一部分22a的方式配置的壁部3、及以沿第二半导体芯片20的外缘22的其他部分22b的方式配置的底部填充树脂剂40，在第一半导体芯片10与第二半导体芯片20之间形成密闭空间S。由此，无需沿第二半导体芯片20的外缘22的一部分22a扩宽第一半导体芯片10的安装区域15。具体而言，由于分注器50沿第二半导体芯片20的外缘22的其他部分22b移行，故而需使安装区域15扩宽分注器50的直径(例如400μm左右)以上。与此相对，由于分注器50不沿第二半导体芯片20的外缘22的一部分22a移行，故而无需扩宽第一半导体芯片10的安装区域15。因此，根据半导体装置1的制造方法，可获得能实现可靠性的提高、及装置尺寸的小型化的半导体装置1。
再者，作为用于形成底部填充树脂层4的一方法的真空填充法，伴随着芯片结构的高精细化，其重要性增加。通过芯片结构的高精细化，相邻的凸块2的中心间距离例如缩小至20μm左右，为了实现该中心间距离，若各凸块2的高度及宽度例如缩小至5μm左右，则第一半导体芯片10与第二半导体芯片20的距离也例如缩小至5μm左右。在该情形时，由于仅以毛细管现象，底部填充树脂剂40难以行进至第一半导体芯片10与第二半导体芯片20之间(特别是，填充至中心部分较困难)，故而通过密闭空间S的内外的压力差使底部填充树脂剂40行进至第一半导体芯片10与第二半导体芯片20之间的真空填充法是优选的。但是，欲通过环状的底部填充树脂剂40形成密闭空间，则为了使分注器50沿第二半导体芯片20的外缘22的所有部分环状移行，需扩宽第一半导体芯片10的安装区域15。因此，通过以沿第二半导体芯片20的外缘22的一部分22a的方式配置壁部3，无需沿该一部分22a扩宽第一半导体芯片10的安装区域15的半导体装置1的构成及半导体装置1的制造方法在实现底部填充树脂层4的确实的配置、及装置尺寸的小型化的方面极有效。
[变化例]
本发明并不限定于上述实施方式。例如，上述实施方式中的各构成并不限定于上述材料及形状而可使用各种材料及形状。另外，上述一实施方式或变化例的各构成可任意用于其他实施方式或变化例的各构成。
另外，如图7的(a)所示，底部填充树脂层4中沿壁部3的侧面3a的部分可收纳于以壁部3的侧面3a为底面的槽内。另外，如图7的(b)所示，第一填角部4a可不到达第二半导体芯片20的侧面20a。另外，底部填充树脂层4可不覆盖壁部3的侧面3a的整体。例如，底部填充树脂层4可仅覆盖壁部3的侧面3a中除中央部3d(参考图6的(a))以外的部分。若底部填充树脂层4覆盖壁部3的侧面3a的一部分，则可实现壁部3的劣化的抑制、及第一半导体芯片10与第二半导体芯片20的接合强度的提高。
另外，壁部3的侧面3a在自方向A观察的情形时，可位于第二半导体芯片20的外缘22的一部分22a上。即，壁部3可以侧面3a与第二半导体芯片20的侧面20a为同一平面的方式配置于第一半导体芯片10与第二半导体芯片20之间。另外，壁部3的材料可不与凸块2的材料相同。作为一例，凸块2的材料为SnAgCu，与此相对，壁部3的材料可为聚酰亚胺。如此，作为壁部3的材料，不仅可使用金属材料，也可使用树脂材料。
另外，如图8及图9所示，半导体装置1可为相邻的第二半导体芯片20及第三半导体芯片(另外的半导体芯片)30通过倒装芯片接合安装于第一半导体芯片10的安装区域15的半导体装置。该半导体装置1中，以沿第二半导体芯片20的外缘22的一部分22a的方式，在第一半导体芯片10与第二半导体芯片20之间配置有壁部3，以沿第三半导体芯片30的外缘32的一部分32a的方式，在第一半导体芯片10与第三半导体芯片30之间配置有壁部3。外缘22的一部分22a为在自方向A观察的情形时以沿第三半导体芯片30的方式延伸的部分。外缘32的一部分32a为在自方向A观察的情形时以沿第二半导体芯片20的方式延伸的部分。该半导体装置1中，在第一半导体芯片10与第二半导体芯片20之间、第一半导体芯片10与第三半导体芯片30之间、及相对的壁部3的侧面3a彼此之间连续配置有底部填充树脂层4。根据该半导体装置1，第二半导体芯片20与第三半导体芯片30可接近配置。
图8及图9所示的半导体装置1中，在真空填充法中，以沿第二半导体芯片20的外缘22的其他部分23b、及第三半导体芯片30的外缘32的其他部分32b的方式，将底部填充树脂剂40以环状配置于第一半导体芯片10的安装区域15，由此可形成底部填充树脂层4。由于在第一半导体芯片10与第二半导体芯片20之间、及第一半导体芯片10与第三半导体芯片30之间的各者通过壁部3及底部填充树脂剂40形成密闭空间S。此种底部填充树脂剂40的配置例如通过如图8的箭头所示使分注器50移行而实施。再者，底部填充树脂剂40通过毛细管现象行进至相对的壁部3的侧面3a彼此之间。
另外，如图10的(a)、(b)及(c)所示，半导体装置1可为第一半导体芯片10具有相邻的安装区域15及端子区域16的半导体装置。端子区域16为半导体基板11的表面11a中设置有多个端子16a的区域。该半导体装置1中，以沿第二半导体芯片20的外缘22的一部分22a的方式，在第一半导体芯片10与第二半导体芯片20之间设置有壁部3。外缘22的一部分22a为在自方向A观察的情形时以沿端子区域16的方式延伸的部分。该半导体装置1中，与图1及图2所示的半导体装置1的不同主要在于代替受光区域14而将端子区域16设置于第一半导体芯片10。根据该半导体装置1，可防止底部填充树脂层4向端子区域16上突出，且第二半导体芯片20与端子区域16可接近配置。再者，图10的(a)、(b)及(c)中，省略凸块2的图示。
如图10的(a)所示，壁部3可以沿相互分离的多个外缘22的一部分22a的各者的方式，配置于第一半导体芯片10与第二半导体芯片20之间。即，可于第一半导体芯片10与第二半导体芯片20之间配置多个壁部3。其在图1及图2所示的半导体装置1、图8及图9所示的半导体装置1中也相同。另外，如图10的(b)及(c)所示，外缘22的一部分22a的长度可小于外缘22的其他部分22b的长度。另外，壁部3未限定于直线状延伸，例如可为弯曲。这些在图1及图2所示的半导体装置1、图8及图9所示的半导体装置1中也相同。
上述半导体装置1中，本发明的支承体为第一半导体芯片10，但本发明的支承体未限定于此。若本发明的支承体只要为具有安装区域的支承体，则例如可为配线基板、电子零件等。
上述半导体装置1的制造方法中，第二工序在真空环境中实施，第三工序在大气压环境中实施，但若第二工序于第一气压的环境中实施，且第三工序于高于第一气压的第二气压的环境中实施，则可通过由壁部3及底部填充树脂剂40形成的密闭空间S的内外的压力差，使底部填充树脂剂40行进至密闭空间S。
【符号说明】
1半导体装置
2凸块
3壁部
3a外侧的侧面
4 底部填充树脂层
4a 第一填角部
4b 第二填角部
10 第一半导体芯片(支承体)
14 受光区域
15 安装区域
16 端子区域
20 第二半导体芯片(半导体芯片)
20a 侧面
22 外缘
22a 一部分
22b 其他部分
30 第三半导体芯片(另外的半导体芯片)
40 底部填充树脂剂
S 密闭空间。

Claims (15)

1.一种半导体装置，其中，
具备：支承体，其具有安装区域；
半导体芯片，其经由规定距离配置于所述安装区域上；
凸块，其配置于所述支承体与所述半导体芯片之间；
壁部，其以沿所述半导体芯片的外缘的一部分的方式配置于所述支承体与所述半导体芯片之间；及
底部填充树脂层，其配置于所述支承体与所述半导体芯片之间，
所述底部填充树脂层覆盖所述壁部的外侧的侧面，
所述底部填充树脂层包括：
第一部分，其以沿所述半导体芯片的所述外缘的所述一部分的方式在所述壁部的所述外侧的侧面配置于所述安装区域；及
第二部分，其以沿所述半导体芯片的所述外缘中除所述一部分以外的其他部分的方式在该其他部分的外侧配置于所述安装区域，
所述第一部分的宽度小于所述第二部分的宽度。
2.一种半导体装置，其中，
具备：支承体，其具有安装区域；
半导体芯片，其经由规定距离配置于所述安装区域上；
凸块，其配置于所述支承体与所述半导体芯片之间；
壁部，其以沿所述半导体芯片的外缘的一部分的方式配置于所述支承体与所述半导体芯片之间；及
底部填充树脂层，其配置于所述支承体与所述半导体芯片之间，
所述底部填充树脂层覆盖所述壁部的外侧的侧面，
所述支承体进一步具有与所述安装区域相邻的受光区域，
所述半导体芯片的所述外缘的所述一部分为所述半导体芯片的所述外缘中以沿所述受光区域的方式延伸的部分。
3.一种半导体装置，其中，
具备：支承体，其具有安装区域；
半导体芯片，其经由规定距离配置于所述安装区域上；
凸块，其配置于所述支承体与所述半导体芯片之间；
壁部，其以沿所述半导体芯片的外缘的一部分的方式配置于所述支承体与所述半导体芯片之间；
底部填充树脂层，其配置于所述支承体与所述半导体芯片之间；及
在所述安装区域与所述半导体芯片相邻的另外的半导体芯片，
所述底部填充树脂层覆盖所述壁部的外侧的侧面，
所述半导体芯片的所述外缘的所述一部分为所述半导体芯片的所述外缘中以沿所述另外的半导体芯片的方式延伸的部分。
4.一种半导体装置，其中，
具备：支承体，其具有安装区域；
半导体芯片，其经由规定距离配置于所述安装区域上；
凸块，其配置于所述支承体与所述半导体芯片之间；
壁部，其以沿所述半导体芯片的外缘的一部分的方式配置于所述支承体与所述半导体芯片之间；及
底部填充树脂层，其配置于所述支承体与所述半导体芯片之间，
所述底部填充树脂层覆盖所述壁部的外侧的侧面，
所述支承体进一步具有与所述安装区域相邻的端子区域，
所述半导体芯片的所述外缘的所述一部分为所述半导体芯片的所述外缘中以沿所述端子区域的方式延伸的部分。
5.如权利要求1至4中任一项所述的半导体装置，其中，
所述底部填充树脂层覆盖所述壁部的所述外侧的侧面的整体。
6.如权利要求1至4中任一项所述的半导体装置，其中，
所述壁部的材料与所述凸块的材料相同。
7.如权利要求5所述的半导体装置，其中，
所述壁部的材料与所述凸块的材料相同。
8.如权利要求1至4中任一项所述的半导体装置，其中，
在自所述支承体与所述半导体芯片相对的方向观察的情况下，所述壁部的所述外侧的侧面较所述半导体芯片的所述外缘的所述一部分更位于内侧。
9.如权利要求5所述的半导体装置，其中，
在自所述支承体与所述半导体芯片相对的方向观察的情况下，所述壁部的所述外侧的侧面较所述半导体芯片的所述外缘的所述一部分更位于内侧。
10.如权利要求6所述的半导体装置，其中，
在自所述支承体与所述半导体芯片相对的方向观察的情况下，所述壁部的所述外侧的侧面较所述半导体芯片的所述外缘的所述一部分更位于内侧。
11.如权利要求7所述的半导体装置，其中，
在自所述支承体与所述半导体芯片相对的方向观察的情况下，所述壁部的所述外侧的侧面较所述半导体芯片的所述外缘的所述一部分更位于内侧。
12.如权利要求1所述的半导体装置，其中，
所述第一部分及所述第二部分到达所述半导体芯片的侧面。
13.如权利要求1或12所述的半导体装置，其中，
所述第一部分为第一填角部，所述第二部分为第二填角部。
14.一种半导体装置的制造方法，其中，
具备：第一工序，其在支承体所具有的安装区域上，经由规定距离配置半导体芯片，通过配置于所述支承体与所述半导体芯片之间的凸块、及以沿所述半导体芯片的外缘的一部分的方式配置于所述支承体与所述半导体芯片之间的壁部，接合所述支承体与所述半导体芯片；
第二工序，其在第一气压的环境中，以沿所述半导体芯片的所述外缘中除所述一部分以外的其他部分的方式在所述其他部分的外侧将底部填充树脂剂配置于所述安装区域，通过所述壁部及所述底部填充树脂剂，在所述支承体与所述半导体芯片之间形成密闭空间；及
第三工序，其通过配置于高于所述第一气压的第二气压的环境，向与所述密闭空间对应的区域填充所述底部填充树脂剂，通过使所述底部填充树脂剂固化，在所述支承体与所述半导体芯片之间配置底部填充树脂层，
所述底部填充树脂剂，以所述底部填充树脂剂固化前所述底部填充树脂剂的一部分沿所述壁部的外侧的侧面行进并覆盖所述壁部的所述外侧的侧面的方式，在所述第二工序中配置于所述安装区域。
15.如权利要求14所述的半导体装置的制造方法，其中，
所述底部填充树脂剂，以所述底部填充树脂剂固化前所述底部填充树脂剂的一部分沿所述壁部的外侧的侧面行进并覆盖所述壁部的所述外侧的侧面的整体的方式，在所述第二工序中配置于所述安装区域。
CN201880087178.0A 2018-01-25 2018-11-27 半导体装置、及半导体装置的制造方法 Active CN111630645B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2018-010709 2018-01-25
JP2018010709A JP7236807B2 (ja) 2018-01-25 2018-01-25 半導体装置、及び半導体装置の製造方法
PCT/JP2018/043617 WO2019146244A1 (ja) 2018-01-25 2018-11-27 半導体装置、及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN111630645A CN111630645A (zh) 2020-09-04
CN111630645B true CN111630645B (zh) 2023-10-17

Family

ID=67395311

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880087178.0A Active CN111630645B (zh) 2018-01-25 2018-11-27 半导体装置、及半导体装置的制造方法

Country Status (7)

Country Link
US (1) US11482555B2 (zh)
EP (1) EP3745449A4 (zh)
JP (1) JP7236807B2 (zh)
KR (1) KR102641911B1 (zh)
CN (1) CN111630645B (zh)
TW (1) TWI799478B (zh)
WO (1) WO2019146244A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7364343B2 (ja) * 2019-02-26 2023-10-18 浜松ホトニクス株式会社 光検出装置の製造方法、及び光検出装置
CN113571430A (zh) * 2020-04-28 2021-10-29 西部数据技术公司 具有减小的底部填充面积的倒装芯片封装体
WO2023239076A1 (ko) * 2022-06-07 2023-12-14 삼성전자주식회사 수지를 포함하는 반도체 패키지 및 이를 포함하는 전자 장치

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09266210A (ja) * 1996-03-28 1997-10-07 Sharp Corp 半導体装置
JPH11163048A (ja) * 1997-11-28 1999-06-18 Matsushita Electric Works Ltd 半導体チップの実装方法
JP2002170848A (ja) * 2000-11-30 2002-06-14 Kyocera Corp 回路基板
JP2002198384A (ja) * 2000-12-27 2002-07-12 Matsushita Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
JP2004039886A (ja) * 2002-07-04 2004-02-05 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2005276879A (ja) * 2004-03-23 2005-10-06 Sony Corp 半導体装置及びその製造方法
CN1812077A (zh) * 2005-01-25 2006-08-02 台湾积体电路制造股份有限公司 集成电路封装结构及底部填充胶工艺
JP2007103772A (ja) * 2005-10-06 2007-04-19 Texas Instr Japan Ltd 半導体装置の製造方法
CN101794738A (zh) * 2009-01-15 2010-08-04 索尼公司 半导体装置及其制造方法
CN102244068A (zh) * 2010-05-14 2011-11-16 索尼公司 半导体器件、半导体器件制造方法以及电子装置
CN102800662A (zh) * 2011-05-26 2012-11-28 株式会社东芝 层叠型半导体装置及其制造方法
JP2015185567A (ja) * 2014-03-20 2015-10-22 富士通株式会社 電子装置、電子装置の製造方法、電子部品及び電子部品の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3220739B2 (ja) 1995-03-23 2001-10-22 サンユレック株式会社 電子部品の製造方法
US7547579B1 (en) 2000-04-06 2009-06-16 Micron Technology, Inc. Underfill process
JP2002124654A (ja) 2000-10-13 2002-04-26 Mitsubishi Electric Corp 固体撮像装置
US6910812B2 (en) * 2001-05-15 2005-06-28 Peregrine Semiconductor Corporation Small-scale optoelectronic package
US8106521B2 (en) 2006-10-19 2012-01-31 Panasonic Corporation Semiconductor device mounted structure with an underfill sealing-bonding resin with voids
TWI339426B (en) 2006-12-07 2011-03-21 Ind Tech Res Inst Gel-joint encapsulated integrated circuit and a substrate structure are provided
US7883937B1 (en) * 2007-04-30 2011-02-08 Altera Corporation Electronic package and method of forming the same
US20090230409A1 (en) * 2008-03-17 2009-09-17 Philips Lumileds Lighting Company, Llc Underfill process for flip-chip leds
JP2010245341A (ja) * 2009-04-07 2010-10-28 Texas Instr Japan Ltd 半導体装置の製造方法
JP5598253B2 (ja) * 2010-10-25 2014-10-01 富士通セミコンダクター株式会社 半導体装置用基板及び半導体装置
JPWO2012093426A1 (ja) * 2011-01-07 2014-06-09 パナソニック株式会社 半導体モジュール
US10192810B2 (en) * 2013-06-28 2019-01-29 Intel Corporation Underfill material flow control for reduced die-to-die spacing in semiconductor packages
US10910507B2 (en) * 2017-06-09 2021-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09266210A (ja) * 1996-03-28 1997-10-07 Sharp Corp 半導体装置
JPH11163048A (ja) * 1997-11-28 1999-06-18 Matsushita Electric Works Ltd 半導体チップの実装方法
JP2002170848A (ja) * 2000-11-30 2002-06-14 Kyocera Corp 回路基板
JP2002198384A (ja) * 2000-12-27 2002-07-12 Matsushita Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
JP2004039886A (ja) * 2002-07-04 2004-02-05 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2005276879A (ja) * 2004-03-23 2005-10-06 Sony Corp 半導体装置及びその製造方法
CN1812077A (zh) * 2005-01-25 2006-08-02 台湾积体电路制造股份有限公司 集成电路封装结构及底部填充胶工艺
JP2007103772A (ja) * 2005-10-06 2007-04-19 Texas Instr Japan Ltd 半導体装置の製造方法
CN101794738A (zh) * 2009-01-15 2010-08-04 索尼公司 半导体装置及其制造方法
CN102244068A (zh) * 2010-05-14 2011-11-16 索尼公司 半导体器件、半导体器件制造方法以及电子装置
CN102800662A (zh) * 2011-05-26 2012-11-28 株式会社东芝 层叠型半导体装置及其制造方法
JP2015185567A (ja) * 2014-03-20 2015-10-22 富士通株式会社 電子装置、電子装置の製造方法、電子部品及び電子部品の製造方法

Also Published As

Publication number Publication date
KR102641911B1 (ko) 2024-02-29
KR20200108889A (ko) 2020-09-21
CN111630645A (zh) 2020-09-04
US20210057477A1 (en) 2021-02-25
US11482555B2 (en) 2022-10-25
EP3745449A1 (en) 2020-12-02
WO2019146244A1 (ja) 2019-08-01
TW201933500A (zh) 2019-08-16
JP2019129258A (ja) 2019-08-01
EP3745449A4 (en) 2021-11-17
JP7236807B2 (ja) 2023-03-10
TWI799478B (zh) 2023-04-21

Similar Documents

Publication Publication Date Title
JP5039058B2 (ja) 半導体素子の実装構造体
US10490510B2 (en) Cavity package with composite substrate
US8786102B2 (en) Semiconductor device and method of manufacturing the same
CN111630645B (zh) 半导体装置、及半导体装置的制造方法
JP5579402B2 (ja) 半導体装置及びその製造方法並びに電子装置
JP5066529B2 (ja) 半導体素子の実装構造体及び半導体素子の実装方法
US9570414B2 (en) Semiconductor device and method of manufacturing the semiconductor device
US20070273019A1 (en) Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier
US20110074037A1 (en) Semiconductor device
US10607964B2 (en) Semiconductor device
US7663254B2 (en) Semiconductor apparatus and method of manufacturing the same
KR102549580B1 (ko) 플립 칩
US8179686B2 (en) Mounted structural body and method of manufacturing the same
CN112563215A (zh) 电子封装件及其制法
JP7316066B2 (ja) 半導体装置及び半導体装置の製造方法
KR101778395B1 (ko) 3d 프린팅 기술을 이용한 반도체 패키지
US8330266B2 (en) Semiconductor device
JP2010263108A (ja) 半導体装置及びその製造方法
US9343427B2 (en) Manufacturing method of semiconductor device and semiconductor device manufactured thereby
JP2008192815A (ja) 積層型半導体装置
JP4190527B2 (ja) 半導体装置
JP2008153699A (ja) 半導体装置及びその製造方法
JP4828997B2 (ja) 半導体パッケージおよびその実装方法、ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法
US20230131730A1 (en) Package substrate and semiconductor package including the same
JP2014179496A (ja) 半導体装置の製造方法および半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant