CN1812077A - 集成电路封装结构及底部填充胶工艺 - Google Patents

集成电路封装结构及底部填充胶工艺 Download PDF

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CN1812077A
CN1812077A CNA2005100830056A CN200510083005A CN1812077A CN 1812077 A CN1812077 A CN 1812077A CN A2005100830056 A CNA2005100830056 A CN A2005100830056A CN 200510083005 A CN200510083005 A CN 200510083005A CN 1812077 A CN1812077 A CN 1812077A
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CN100373597C (zh
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李新辉
李建勋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路芯片封装结构及其底部填充胶工艺，利用粘结材料以降低集成电路封装结构上倒装芯片边角的应力。此工艺包含提供位于承载基板上的屏蔽结构，于承载基板上黏附倒置的倒装芯片之锡铅凸块，再由倒装芯片与基板之间的多个注入点沿着倒装芯片的边缘注入粘结材料，再顺着粘结材料四周注入密封材料。当进行粘结材料及密封材料填充于集成电路封装之底部填充胶工艺时，屏蔽结构可降低倒装芯片边角的应力。此工艺亦可防止倒装芯片上介电层剥离的情形发生。

Description

集成电路封装结构及底部填充胶工艺
技术领域
本发明涉及一种半导体集成电路之倒装芯片(Flip Chip)封装组合，特别涉及集成电路封装结构及集成电路封装结构底部填充胶工艺(Underfill Process)，其利用结合屏蔽(Dam)并在芯片与承载基板之间指向性的注入底部填充胶材料，来防止或降低在集成电路封装时，倒装芯片球栅阵列封装体(Ball Grid Array，BGA)上的内金属介电层的剥离。
背景技术
多重封装(Multi-leveled Packaging)为制造半导体集成电路工艺中的最后流程之一，包括扩展IC芯片的电极间距以进行后续的封装；保护芯片以避免机械及环境应力；提供芯片适当的散热路径及形成电子导线。IC芯片封装的方式亦决定封装所需的成本、效能及可靠度。
IC芯片的封装类型可概括分为两大类：密封陶瓷封装及塑料封装。密封陶瓷封装是利用真空密封装置将芯片与环绕的包围物隔离的方式封装，典型的密封陶瓷封装应用于高效能的封装等级。而塑料封装芯片则是利用环氧基树脂将芯片封装，其无法完全与环境隔离，因此周边的空气可穿过此封装，并在工艺中会对芯片的质量产生不良的影响。近年来塑料封装技术在其应用及效能上亦有所进展，且塑料封装的生产工艺较符合经济效益，因为塑料封装容易进行自动化生产。
近年来发展的IC芯片球栅阵列封装，可利用陶瓷封装或塑料封装技术，并包含不同内部封装结构型式的封装方法。球栅阵列封装以锡球或锡铅凸块来电性与机械连接IC芯片与其它微电子元件。锡铅凸块将IC芯片固定到电路板上，同时也电性连接芯片电路至电路板上的导线。球栅阵列封装技术包含了较广范的连接技术，例如倒装芯片技术(Flip-chip Technology)或倒装芯片连接技术-C4(ControlledCollapse Chip Connection-C4)。
倒装芯片技术可以用来连接不同种类的电路板，包括陶瓷基板、印刷线路板、有弹性的电路板及氧化硅基板。锡铅凸块一般位于倒装芯片的电传导焊垫边缘，连接倒装芯片的电子导线与电路系统。由于倒装芯片利用微型电路技术来达到其功能，因此锡铅凸块的数目也就相对的增加。典型的倒装芯片尺寸约为每边13毫米，结果造成倒装芯片的周围挤满了锡铅凸块。因此倒装芯片导体图案通常由大量的个别导体所组成，其导体间的间隔距离只有约0.1毫米或更小。
图1是公知例中常见的球栅阵列IC封装结构截面图，IC封装结构体8具有一个以面朝下反转接合于承载基板20的倒装芯片10，承载基板20可为一个印刷电路板。通过芯片基板12表面的多个焊垫16，与含有IC的电接触器在芯片基板12上组装倒装芯片10。每个典型的球面锡铅凸块18都凸出于芯片基板12表面的保护层14。此外，一个锡氧化层19可能覆盖于锡铅凸块18表面。
在IC封装结构体8的元件中，倒装芯片10的主要回焊(Re-flow)温度为320℃，用以在芯片基板12上回焊锡铅凸块18。接着将倒装芯片10反转并分别与锡铅凸块18的焊垫接合。回焊的热度会部分地熔化锡氧化层19使之与锡铅凸块18接合于承载基板20上。
公知例中，在底部填充胶工艺提供一粘结于承载基板20与芯片基板12间的粘结材料22，例如环氧化物。如图2A所示，通过一个注胶机24来分配液态的粘结材料22到承载基板20上的倒装芯片10的每一边角，接着如图2B所示，通过承载基板20与芯片基板12间的毛细作用可拉长此粘结材料22。随着粘结材料22变硬而有较高的杨氏模量(Young’s Modulus)，倒装芯片10黏附于承载基板20上并保护IC封装结构体8组装时锡铅凸块不致裂化。密封材料23具有较低的杨氏模量，可防止芯片基板12上低介电常数介电层的剥离。
粘结材料22附着在IC封装结构体8时，于芯片基板12上所产生的应力使内金属介电层变的脆弱，在使用粘结材料22时，特别是在倒装芯片10的边角处的内金属介电层会剥离。因此需要一种新颖的底部填充胶工艺来预防或降低应力以符合倒装芯片条件，特别是能预防在运用粘结材料于倒装芯片结构体时，芯片上低介电常数介电层发生剥离。
发明内容
本发明的目的是提供一种底部填充胶工艺，用以降低IC结构体上倒装芯片与承载基板间的粘结材料所产生的应力。
本发明的另一目的是提供一种底部填充胶工艺，用以降低倒装芯片所产生的应力。此工艺包括提供承载基板上的屏蔽结构，并利用附加锡铅凸块于承载基板上，再沿着倒装芯片与承载基板间，由位于倒装芯片边缘的多个注入点注入粘结材料，并在粘结材料四周注入密封材料，此屏蔽结构可降低底部填充胶工艺中倒装芯片边角的应力。
为达到本发明所主张的技术优点，本发明提供一种底部填充胶工艺，可降低IC封装结构中倒装芯片与承载基板间的粘结材料所产生的边角应力。此工艺包括提供承载基板上的屏蔽结构，并附加锡铅凸块于承载基板上，再沿着倒装芯片边缘由倒装芯片与承载基板间的多个注入点注入粘结材料，并在粘结材料四周注入密封材料，当应用此粘结材料与密封材料于底部填充胶工艺时，形成的屏蔽结构可降低底部填充胶工艺中倒装芯片边角的应力，或至少可降低倒装芯片之介电层的剥离。
本发明还包含IC芯片结构，具有承载基板及位于承载基板上的多重屏蔽元件；附着于承载基板上的倒装芯片；倒装芯片的各个边角分别连接于不同的屏蔽元件。组装此IC芯片时，在倒装芯片与承载基板间的多个注入点沿着倒装芯片边缘注入粘结材料以降低倒装芯片边角的应力，并在粘结材料四周注入密封材料。
附图说明
为让本发明之上述和其他目的、特征、优点与实施例能更明显易懂，所附附图之详细说明如下：
图1是公知例之一种接合于承载基板的倒装芯片之球栅阵列IC封装结构截面图。
图2A到图2B是公知例之一种将倒装芯片粘结于承载基板的底部填充胶工艺截面图。
图3A到图3D是依照本发明一较佳实施例的一种底部填充胶工艺的连续步骤图。
图4是依照本发明一较佳实施例的一种IC芯片底部填充胶工艺的俯视图。
图5是依照本发明一较佳实施例的一种底部填充胶工艺的连续步骤流程图。
主要元件标记说明
8：IC封装结构体
10：倒装芯片
12：芯片基板
14：保护层
16：焊垫
18：锡铅凸块
19：锡氧化层
20：承载基板
22：粘结材料
23：密封材料
24：注胶机
28：IC封装结构
30：倒装芯片
30a：边缘
30b：边缘
30c：边角
32：芯片基板
34：保护层
36：焊垫
38：锡铅凸块
40：承载基板
40a：边角
40b：边缘
41：接合表面
42：粘结材料
43：密封材料
44：屏蔽结构
46：屏蔽元件区段
46a：对元件区段
48：空气
50：注入点
具体实施方式
本发明提出一种底部填充胶工艺，特别是应用一种倒装芯片与承载基板间的粘结材料，以降低组装IC封装结构时倒装芯片边角所产生的应力。根据此工艺，提供位于承载基板上的屏蔽结构，此屏蔽结构包含多重屏蔽元件，分别与倒装芯片的各个边角邻接。接着，具有多个锡铅凸块的倒装芯片被向下反转接合于此承载基板上。高应力模量的环氧基树脂粘结材料沿着倒装芯片边缘的多个注入点注入倒装芯片与承载基板之间。最后，将含有松香的低应力模量环氧基树脂密封材料注入粘结材料四周。应用此IC封装结构底部填充胶工艺的粘结材料与密封材料，形成的屏蔽结构可降低底部填充胶工艺中倒装芯片边角的应力。本工艺至少可降低倒装芯片介电层的剥离，特别是具有低介电常数的较脆弱的金属内介电层。
本发明还包含IC芯片结构，其具有承载基板及位于承载基板上的多重屏蔽元件。黏附于承载基板上具有多个锡铅凸块之倒装芯片的各个边角分别邻接于不同的屏蔽元件。高应力模量的粘结材料位于倒装芯片与承载基板之间，于组装此IC芯片结构时，分别沿着倒装芯片边缘的多个注入点注入粘结材料以降低倒装芯片边角的应力。本发明亦利用低应力模量环氧基树脂密封材料环绕于高应力模量的粘结材料四周。
如图3D及图4所示，依照本发明披露的工艺组装IC封装结构28，首先需有承载基板40。举例来说，承载基板40可以是一个印刷电路板，其典型的用途是作为一个电子产品中较高等级电子结构的倒装芯片30之电性连接。如图3A所示，屏蔽结构44位于承载基板40上的接合表面41，接着倒装芯片30黏附于IC封装结构28的过程详述于后。
屏蔽结构44为典型的环氧基树脂所构成，如图4所示，接合表面41上可能包含多重屏蔽元件46，分别邻接于承载基板40上的各个边角40a。各屏蔽元件46以一般常见的L-形并包含一对元件区段46a，其成相互垂直排列关系且与承载基板40的边缘40b平行。当组装此IC封装结构28时，多重屏蔽元件46可防止或降低倒装芯片30的芯片基板32上介电层的剥离。
如图3B到图3D所示，倒装芯片30包含位于芯片基板32上分别以铅与各个焊垫36结合的多个锡铅凸块38，一层可能覆盖于各个锡铅凸块38上的锡氧化层，一层绝缘保护层34环绕于焊垫36以保护芯片基板32表面。依照制造IC芯片的公知技术，将IC元件逐项组装于芯片基板32上，再集合其它的芯片基板32，即初步产生了一个氧化硅半导体晶片。在芯片组装的最后，个别的晶粒或倒装芯片30被切割成小方块状。焊垫36附属于芯片基板32上的IC上，而锡铅凸块38则分别形成于各个焊垫36上。因此通过芯片基板32上的焊垫36使锡铅凸块38与IC之间可电互相联系。
如图3B所示，倒装芯片30接着以面向下反转方式接合于承载基板40上的接合表面41。在接合步骤之前此倒装芯片30先以320℃的温度将锡铅凸块38回焊。接着反转倒装芯片30使锡铅凸块38分别结合于承载基板40上的各焊垫36，回焊的热度会部分地熔化锡铅凸块上覆盖的锡氧化层使锡铅凸块38接合于承载基板40上的焊垫36。如图4所示，倒装芯片30的边缘30a及边缘30b的位置正好位于屏蔽结构44的各个屏蔽元件46之对元件区段46a上方并与之成平行关系。
如第3C图所示，高应力模量的粘结材料42接着被注入倒装芯片30与承载基板40之间，粘结材料42通常是环氧基树脂，可将倒装芯片30黏附于承载基板40上，以防止或降低在IC封装结构体组装时锡铅凸块38裂化。如第4图所示，可利用分别邻接芯片基板32的边缘30a的三个注入点50注入粘结材料42，但并不由边缘30b注入此粘结材料42。
当粘结材料42由各个注入点50注入倒装芯片30与承载基板40间时，液态的粘结材料42会因锡铅凸块38间的毛细作用而被拉长，同时此粘结材料42可顺着边缘30b驱赶出倒装芯片30与承载基板40间的空气48。注入点50位于倒装芯片30上的三个边缘30a上，倒装芯片30的边缘30a包括了被保护的屏蔽结构44的所有屏蔽元件46及各个边角30c，可预防粘结材料42于芯片基板32上剥离的介电层中流动，特别是剥离的低介电常数的内金属介电层。
如图3B所示，当粘结材料42变硬时，便沿着粘结材料42边缘注入低应力模量的密封材料43，此密封材料43通常是含有松香的环氧基树脂。接着依照公知技术，在组装IC封装结构28的承载基板40时提供高等级电子结构的电接触器以组装成一个电子产品。在IC封装结构28进行其功能时，密封材料43可隔绝电子产品的外在元件与锡铅凸块的热及电。
图5是依照本发明披露的工艺的连续步骤流程图。如步骤1所示，最初于作为承载基板的印刷电路板上提供一屏蔽结构；接着如步骤2所示，一个具有锡铅凸块的倒装芯片被反转接合于承载基板的个别焊垫上；再如步骤3所示，于倒装芯片与承载基板间注入具有高应力模量的粘结材料，使芯片基板黏附于承载基板上并保护锡铅凸块不致裂化，承载基板上的屏蔽结构可预防在使用粘结材料时应力过度集中于倒装芯片的边角；最后如第4步骤所示，以围绕着粘结材料的方式注入低应力模量的密封材料，以利于锡铅凸块与外在元件间的隔热及绝缘。
虽然本发明已以一较佳实施例披露如上，然其并非用以限定本发明，任何所属技术领域的技术人员，在不脱离本发明之精神和范围内，当可作各种之更动与改进，因此本发明之保护范围当视权利要求所界定者为准。

Claims (13)

1.一种集成电路芯片结构，其特征是至少包含：
承载基板；
倒装芯片，附着于该承载基板之上；
屏蔽结构，位于该承载基板之上；以及
粘结材料，用于该承载基板与该倒装芯片间。
2.根据权利要求1所述的集成电路芯片结构，其特征是该粘结材料至少包含环氧基树脂。
3.根据权利要求1所述的集成电路芯片结构，其特征是该屏蔽结构至少包含环氧基树脂。
4.根据权利要求1所述的集成电路芯片结构，其特征是该屏蔽结构邻接于该倒装芯片的边角。
5.根据权利要求1所述的集成电路芯片结构，其特征是该屏蔽结构至少包含多个屏蔽元件。
6.一种集成电路芯片结构，其特征是至少包含：
承载基板；
矩形倒装芯片，附着于该承载基板之上；
屏蔽结构，位于该承载基板之上；
粘结材料，用于该承载基板与该倒装芯片之间；以及
密封材料，环绕于该粘结材料周围。
7.根据权利要求6所述的集成电路芯片结构，其特征是该粘结材料至少包含环氧基树脂。
8.根据权利要求6所述的集成电路芯片结构，其特征是该屏蔽结构至少包含多个屏蔽元件位于该倒装芯片的各个边角，且其中每一个上述屏蔽元件至少包含环氧基树脂。
9.根据权利要求6所述的集成电路芯片结构，其特征是该密封材料至少包含含松香的环氧基树脂。
10.根据权利要求6所述的集成电路芯片结构，其特征是该屏蔽结构至少包含环氧基树脂。
11.根据权利要求6所述的集成电路芯片结构，其特征是该屏蔽结构至少包含具有L-形结构的多个屏蔽元件。
12.一种集成电路芯片结构，其特征是该结构至少包含：
承载基板；
多个屏蔽元件，位于该承载基板上；
倒装芯片，附着于该承载基板之上，其中该倒装芯片的边角分别与该屏蔽元件相邻接；
粘结材料，用于该承载基板与该倒装芯片之间；以及
密封材料，环绕于该粘结材料周围。
13.根据权利要求12所述的集成电路芯片结构，其特征是每一个上述屏蔽元件至少包含一对元件区段且其相互垂直。
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