CN107492527B - 具有顺应性角的堆叠半导体封装体 - Google Patents

具有顺应性角的堆叠半导体封装体 Download PDF

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CN107492527B
CN107492527B CN201710289319.4A CN201710289319A CN107492527B CN 107492527 B CN107492527 B CN 107492527B CN 201710289319 A CN201710289319 A CN 201710289319A CN 107492527 B CN107492527 B CN 107492527B
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semiconductor package
flexible substrate
adhesive material
stacked
package
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CN107492527A (zh
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J·塔利多
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STMicroelectronics International NV
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STMicroelectronics lnc USA
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Abstract

本申请涉及具有顺应性角的堆叠半导体封装体。一个或多个实施例涉及堆叠在柔性折叠衬底上的堆叠封装体，比如封装体上封装体(PoP)封装体。这些堆叠封装体具有顺应性角。具体地，这些堆叠封装体包括在该折叠衬底的层之间的这些角处的粘合材料。该粘合材料具有低弹性模量，如例如，硅树脂粘合剂的弹性模量。该粘合材料的该低弹性模量产生了该堆叠封装体的顺应性角。该粘合材料对该折叠衬底之间的在该堆叠封装体的底部半导体封装体周围形成的开口进行填充。就此而言，该底部半导体封装体可以具有拉回角或者凹角，并且该粘合材料对由这些凹角所形成的这些开口进行填充。这些凹角可以具有任何大小或者形状。

Description

具有顺应性角的堆叠半导体封装体
技术领域
本公开的实施例涉及堆叠半导体封装体和形成堆叠半导体封装体的方法。
背景技术
对更小的电子设备的不断需求迫使这类设备的制造商在设备内部的任何可能的地方增大部件密度并减小部件大小。半导体制造者已经通过以下方式做出回应：增加使用芯片尺度封装和晶片级封装技术来最小化半导体封装体的占用面积，有时将封装体减小到与半导体裸片自身的尺寸相接近的尺寸。具体地，已经实施了对可直接表面安装的球栅阵列和倒装芯片构型的使用，从而减小了半导体封装体的大小。
已经通过垂直地堆叠封装体来形成堆叠封装体(也被称为封装体上封装体(Package-on-Package，PoP)封装体，从而节省了印刷电路板(PCB)上的空间。堆叠封装体是垂直堆叠的封装体并且包括垂直堆叠在底部封装体之上的一个或多个顶部封装体。堆叠封装体通常比单独的封装体更加刚性并且在一些情况下可能由于堆叠封装体内不同材料的刚性和不同热膨胀系数而引起翘曲。在将封装体耦合到PCB时，堆叠封装体的刚性可能导致焊接可靠性减小。
发明内容
一个或多个实施例涉及堆叠在柔性折叠衬底上的堆叠封装体，比如封装体上封装体(PoP)封装体。堆叠封装体具有顺应性角，这些顺应性角在一些实施例中减小堆叠封装体的刚性。具体地，这些堆叠封装体包括在堆叠的角处(比如在折叠衬底的层之间)的粘合材料。该粘合材料具有低弹性模量，如例如，硅树脂粘合剂的弹性模量。粘合材料的低弹性模量产生了堆叠封装体的顺应性角并且容纳通常可能在堆叠封装体中引起的翘曲中的至少一些。此外，在将堆叠封装体耦合到另一设备(比如PCB)时，粘合剂改善了堆叠封装体的角处的导电凸块的寿命。
在至少一个实施例中，该粘合材料对该折叠衬底之间的在该堆叠封装体的底部半导体封装体周围形成的开口进行填充。就此而言，该底部半导体封装体可以具有拉回角或者凹角，并且该粘合材料对由这些凹角所形成的这些开口进行填充。这些开口中的这些凹角和该粘合材料可以具有任何大小或者形状。
附图说明
在附图中，完全相同的参考号标识类似的元件。附图中的元件的大小和相对位置不一定按比例绘制。
图1A至图1C展示了根据一个实施例的堆叠封装体的各种视图；
图2展示了图1A至图1C的被耦合到PCB的堆叠封装体的侧视图。
图3展示了根据另一个实施例的堆叠封装体的侧视图。
图4A至图4G展示了根据本公开的实施例的用于形成堆叠封装体(比如图1A至图1C的堆叠封装体)的装配工艺的各个阶段的横截面视图。
图5是将具有顺应性角的半导体封装体(比如图1A至图1C的封装体)的焊料寿命与不具有顺应性角的封装体的焊料寿命进行比较的表。
具体实施方式
将理解的是，尽管出于说明的目的在此描述了本公开的多个具体实施例，但在不背离本公开的精神和范围的情况下可以做出各种修改。
在以下说明中，阐述了某些具体细节以便提供对所公开的主题的各种方面的全面理解。然而，所公开的主题可以在没有这些具体细节的情况下实施。在一些实例中，尚未具体描述包括在此所公开的主题的实施例的公知结构和半导体(比如半导体功率设备)加工方法以免模糊本公开的其它方面的描述。
图1A是根据一个实施例的封装体上封装体(PoP)封装体或者堆叠封装体10的等距视图。如下文将详细解释的，图1B是堆叠封装体10的侧视图，而图1C是堆叠封装体10的顶视图，用虚线展示了底部封装体的凹角。
堆叠封装体10包括被耦合到折叠柔性衬底16的顶部半导体封装体12和底部半导体封装体14。顶部半导体封装体12和底部半导体封装体14包括集成了如本领域中熟知的集成电路等一个或多个电气部件的一个或多个半导体芯片30(图4A)。集成电路可以是被实施为形成在芯片内并根据芯片的电气设计和功能电互连的有源设备、无源设备、导电层以及电介质层的模拟电路或者数字电路。
半导体芯片30周围为包封材料20，该包封材料为保护其中的电气部件(比如半导体芯片和导电接线或凸块)不受损坏(比如腐蚀、物理损坏、潮湿损坏或对电气部件的损坏的其他原因)的外部环境来源的影响的电介质材料。包封材料20可以是模制化合物，比如聚合物树脂。尽管在堆叠封装体中只示出了两个半导体封装体，但应当理解的是，堆叠封装体可以包括堆叠中的更大数量的半导体封装体并且可以进一步包括柔性衬底或者另一个衬底中的更多折叠。
柔性衬底16将顶部半导体封装12和底部半导体封装体14电气地且机械地耦合到一起。在折叠部分16a处将柔性衬底16折叠以形成上部部分16b和下部部分16c。将顶部半导体封装体12直接耦合到柔性衬底16的上部部分16b并且将底部半导体封装体14直接耦合到柔性衬底16的下部部分16c。
如本领域中熟知的，柔性衬底16包括导电触点、导电迹线和绝缘材料。具体地，柔性衬底包括上部部分16b和下部部分16c上的导电触点。各个导电触点在柔性衬底16上通过导电迹线耦合到一起，这些导电迹线如本领域中公知的那样延伸穿过柔性衬底16的折叠部分16a。在那个方面，上部部分16b的一个或多个导电触点通过延伸穿过柔性衬底16的折叠部分16a的导电迹线耦合到下部部分16c的导电触点。柔性衬底16的绝缘材料将其中的各种导电部件隔离开。
柔性衬底16具有内表面16d和外表面16e。内表面16d和外表面16e位于柔性衬底16的上部部分16b和下部部分16c两者上。顶部半导体封装体12通过第一组导电凸块(比如焊料凸块)22a耦合到柔性衬底16的上部部分16b的外表面16e的导电触点。如本领域中熟知的，第一组导电凸块22a被耦合到顶部半导体封装体12内的半导体芯片的一个或多个电气部件。
柔性衬底16的内表面16d面向底部半导体封装体14的第一表面和第二表面。具体地，柔性衬底16的内表面16d(在其上部部分16b处)面向底部半导体封装体14的第二表面，并且柔性衬底16的下部部分16c的内表面16d面向底部半导体封装体14的第一表面。将底部半导体封装体14电耦合到柔性衬底16的下部部分16c的内表面16d上的导电触点。具体地，将底部半导体封装体14之内的半导体芯片的电气部件电耦合到柔性衬底16的下部部分16c的内表面16d的导电触点。例如，如本领域中熟知的，半导体芯片可以通过采用倒装芯片构型的导电凸块或者通过导电接线耦合。
在柔性衬底16的下部部分16c的外表面16e的导电触点上形成第二组导电凸块(比如焊球)22b。如在图2中示出的，第二组导电凸块22b被配置成用于将堆叠封装体耦合到另一个设备，比如PCB28。如将对本领域普通技术人员而言明显的，顶部半导体封装体12和底部半导体封装体14中的半导体芯片通过柔性衬底16的下部部分16c上的第二组导电凸块22b电耦合到PCB 28的电气部件。PCB28是电子设备的一部分，该电子设备可以是任何电子设备(比如智能电话、笔记本计算机或者任何其他电子设备)，包括作为更大设备的一部分的设备。
在堆叠封装体10的角处，在柔性衬底16的上部部分16b和下部部分16c的内表面16d之间为粘合材料24。粘合材料24为具有低杨氏模量(比如硅树脂粘合剂的杨氏模量)的任何粘合材料。例如，在一个实施例中，粘合材料的杨氏模量在约0.001至0.05GPa之间。具体地，粘合材料的杨氏模量小于半导体封装体的包封材料20的杨氏模量。在那个方面，粘合材料24为允许堆叠封装体10(特别是在堆叠封装体的角处)更加顺应性的弹性材料，从而为封装体提供顺应性角。由于粘合材料24为可弹性变形的材料，由此减少了堆叠封装体10的翘曲。另外地，如将参照图5更加详细地解释的，堆叠封装体10的顺应性角延长了堆叠封装体的导电凸块(特别是第二组导电凸块22b)的寿命。此外，粘合材料24有助于将柔性衬底16的上部部分16b和下部部分16c机械耦合到一起。在一个实施例中，粘合材料24为硅树脂或者基于硅树脂的粘合剂。
粘合材料24对由柔性衬底16的上部部分16b与下部部分16c之间的底部半导体封装体14中的凹陷形成的开口34(图4C)进行填充。具体地，底部半导体封装体14具有凹角33(图4C)，这些凹角在堆叠封装体10的在柔性衬底16的上部部分16b与下部部分16c之间的角处创造开口34。更具体地，底部半导体封装体14的包封材料20包括如在图4C中最佳示出的凹角33。粘合材料24填充(或者至少基本上填充)底部半导体封装体14的在柔性衬底16的上部部分16b与下部部分16c之间的区域中的凹角。
图1C用虚线展示了粘合材料24的形状，其在所展示的实施例中为正方形。粘合材料24对底部半导体封装体14的凹角进行填充，这些凹角可以具有任何种类的形状，比如三角形形状、矩形形状或者任何其他适当形状。
在对堆叠封装体10的操作时，顶部半导体封装体12和底部半导体封装体14通过柔性衬底16以及第一组和第二组导电凸块22b与PCB 28电通信。顶部半导体封装体12和底部半导体封装体14中的一者或两者还可以被配置成用于通过柔性衬底16彼此通信。
如上所述，具有粘合材料24填充角的堆叠封装体10在板安装之后提供了改进的板级可靠性(BLR)。粘合材料24的灵活性可以减轻堆叠封装体10的应力，已确定该应力在堆叠封装体的角处最高。在已将堆叠封装体10耦合到另一个设备或者PCB 28之后，柔性衬底16的上部部分16b与下部部分16c之间的粘合材料24延长了第一组和/或第二组导电凸块22的寿命。具体地，粘合材料24吸收施加于堆叠封装体10的角处的导电凸块22的应力。因此，粘合材料24在封装体中弹性变形并减轻应力，而不是导电凸块22破裂，从而减少了封装体的翘曲。
图3展示了根据另一个实施例的堆叠封装体10a的侧视图。除了图3的堆叠封装体10a中的粘合材料24不仅对柔性衬底16的上部部分16b与下部部分16c之间的角中的开口进行填充而且位于底部半导体封装体14与柔性衬底16的上部部分16b之间之外，图3的堆叠封装体10a与图1的堆叠封装体10基本上相同。也就是说，粘合材料24对由如参照图1A至图1C而描述的底部封装体14的凹角形成的开口进行填充，并且粘合剂24的一部分在底部封装体14的背部表面与柔性衬底16的上部部分16b之间。在底部封装体14的背部表面与柔性衬底16的上部部分16b的内表面16d之间的粘合材料的该部分帮助将柔性衬底16的上部部分16b粘合到底部半导体封装体14和/或柔性衬底16的下部部分16c。粘合材料24的该部分还可以提供解决翘曲问题并减轻导电凸块破裂的堆叠封装体10a的增强弹性。
图4A至图4G展示了根据本公开的实施例的用于形成堆叠封装体(比如图1A至图1C的堆叠封装体)的装配工艺的各个阶段的横截面视图。
如在图4A中示出的，半导体芯片30被放置在柔性衬底16的下部部分16c的内表面16d上并与其电气和机械耦合。具体地，可以将半导体芯片30的第一表面耦合到柔性衬底16的下部部分16c的内表面16d。在图4A中，半导体芯片30的第二表面朝上。半导体芯片30的第二表面为该芯片的包括以上所讨论的电气部件的有源表面。将导电接线32的第一端耦合到半导体芯片10的有源表面的键合焊盘，并且将导电接线32的第二端耦合到柔性衬底16的导电触点。
尽管未示出，但是半导体芯片30也可以通过倒装芯片安排被其耦合到柔性衬底16的下部部分16c的内表面16d。也就是说，如本领域中熟知的，可以将导电凸块耦合到半导体芯片30的有源表面的键合焊盘与柔性衬底16的导电触点之间。
如在图4B中示出的，使用包封材料20来包封半导体芯片30以形成底部半导体封装体14。具体地，可以执行模制步骤，在该模制步骤中，将模制化合物(比如树脂)引入到容纳柔性衬底16和半导体芯片30的模具中。模制化合物在半导体芯片30和导电接线周围流动并随着时间硬化。硬化过程可以包括一个或多个固化步骤。底部半导体封装体14被形成为具有用于形成如在图4C中示出的开口34的凹角33。例如，模具被成型成用于形成具有凹角33的包封材料20，从而使得开口34保持在封装体的角处。图4C示出了平面视图中的底部半导体封装体14并且展示了封装体的四个角中的每个角处的开口34和凹角33。
如在图4D中示出的，粘合材料24被分配到由底部半导体封装体14的凹角33形成的开口34中。例如，硅树脂沉积在开口34中。粘合材料24随着时间硬化。在一个实施例中，粘合材料24可以涉及用于硬化的固化步骤。
在一些实施例中，对多个半导体芯片执行在图4A至图4D中示出的步骤，从而使得在单个柔性衬底带或阵列上形成多个底部半导体封装体14。在这种实施例中，柔性衬底可以经受划线操作，包括锯切、激光或者穿孔以分离成单独的柔性衬底。
如在图4E中示出的，柔性衬底16的上部部分被折叠到底部半导体封装体14的第二表面以及粘合材料24之上以形成折叠部分16a。开口34中的粘合材料24将柔性衬底16的上部部分16b粘合到柔性衬底16的下部部分16c。
如在图4F中示出的，使用标准的半导体凸块形成技术来在柔性衬底16的下部部分16c的外表面的导电触点上形成第二组导电凸块22b。
如在图4G中示出的，使用第一组导电凸块22a来将顶部半导体封装体12耦合到柔性衬底16的上部部分16b的外表面16e。顶部半导体封装体12为任何先前形成的半导体封装体。形成顶部半导体封装体12的细节在本领域中是熟知的并且为了简洁起见不在此提供。首先可以或者在柔性衬底16的上部部分16b的外表面16e的导电触点上或者在顶部半导体封装体12本身的导线或触点上形成第一组导电凸块22a。如本领域中熟知的，在使用柔性衬底16与顶部半导体封装体12之间的第一组导电凸块22a来将其放置在一起之后，第一组导电凸块22a可以经受使第一组导电凸块22a回流并且粘合到柔性衬底16和顶部半导体封装体12的导电凸块的回流步骤。
装配工艺可以按照与以上所描述的顺序不同的顺序执行。例如，顶部半导体封装体12可以在折叠柔性衬底之前被耦合到柔性衬底16的上部部分16b。
图5示出了图表，展示了对根据图1A至图1C的实施例的具有顺应性角的堆叠封装体的导电凸块的寿命与根据相关技术的不具有顺应性角的堆叠封装体的导电凸块的寿命进行的比较。如在该图表中示出的，具有顺应性角的堆叠封装体的导电凸块具有更长的寿命，从而提高了堆叠封装体的板级可靠性。
可以组合以上所描述的各种实施例以提供进一步实施例。在本说明书中引用的和/或在申请数据表中列举的所有美国专利、美国专利申请公开、美国专利申请、外国专利、外国专利申请和非专利公开通过引用而完全并入于此。如果必要，则可以修改实施例的方面以运用各种专利、申请和公开文献的概念来提供更多实施例。
可以按照上文详述的描述对实施例进行这些和其他改变。总之，在以下权利要求书中，所使用的术语不应当被解释为将权利要求书限制于本说明书和权利要求书中所公开的特定实施例，而是应当被解释为包括所有可能的实施例、连同这种权利要求有权获得的等效物的整个范围。相应地，权利要求书并不受本公开的限制。

Claims (20)

1.一种堆叠半导体封装体，包括：
柔性衬底，所述柔性衬底具有第一表面和第二表面，所述第一表面和所述第二表面包括导电触点，所述柔性衬底被折叠并形成上部部分和下部部分；
第一半导体封装体，所述第一半导体封装体位于所述柔性衬底的所述上部部分与所述下部部分之间，所述第一半导体封装体包括凹角；
粘合材料，所述粘合材料位于所述凹角处，并且位于所述第一半导体封装体的背部表面与所述柔性衬底的所述上部部分之间，所述粘合材料将所述柔性衬底的所述上部部分与所述下部部分耦合在一起；以及
第二半导体封装体，所述第二半导体封装体被耦合到所述柔性衬底的所述上部部分。
2.如权利要求1所述的堆叠半导体封装体，其中，所述粘合材料包括硅树脂。
3.如权利要求1所述的堆叠半导体封装体，其中，所述粘合材料具有第一杨氏模量并且所述第一半导体封装体包括具有大于所述第一杨氏模量的第二杨氏模量的包封材料，其中所述第一半导体封装体的所述包封材料具有所述凹角。
4.如权利要求1所述的堆叠半导体封装体，其中，所述第一半导体封装体的所述凹角形成正方形开口、三角形开口以及矩形开口中的至少一种。
5.如权利要求1所述的堆叠半导体封装体，其中，所述粘合材料位于所述堆叠半导体封装体的角处。
6.如权利要求1所述的堆叠半导体封装体，包括所述第一半导体封装体的背部表面与所述柔性衬底的所述上部部分之间的粘合材料。
7.如权利要求1所述的堆叠半导体封装体，其中，所述堆叠半导体封装体被耦合到印刷电路板。
8.一种形成堆叠半导体封装体的方法，包括：
将第一半导体芯片耦合到柔性衬底的第一部分的第一表面；
用包封材料包封所述第一半导体芯片以形成具有凹角的第一半导体封装体，其中，所述柔性衬底的所述第一部分的所述第一表面的多个部分被所述凹角暴露；
将粘合材料放置在被所述柔性衬底的所述第一部分的所述第一表面的所述凹角暴露的所述部分中；以及
将所述柔性衬底的第二部分折叠在所述柔性衬底的所述第一部分之上，
其中所述粘合材料将所述柔性衬底的所述第一部分与所述第二部分耦合在一起，并且所述粘合材料的一部分位于所述第一半导体封装体的背部表面与所述第二部分之间。
9.如权利要求8所述的方法，进一步包括：将第二半导体封装体耦合到所述柔性衬底的所述第二部分以形成堆叠封装体。
10.如权利要求9所述的方法，进一步包括：用导电凸块将所述堆叠封装体耦合到印刷电路板。
11.如权利要求8所述的方法，其中，所述粘合材料为硅树脂粘合材料。
12.如权利要求8所述的方法，其中，所述粘合材料将所述柔性衬底的所述第一部分和所述第二部分粘合在一起。
13.如权利要求8所述的方法，其中，所述第一半导体芯片的所述凹角为正方形、矩形或三角形之一。
14.如权利要求8所述的方法，其中，将粘合材料放置在所述柔性衬底的所述第一部分的所述第一表面的所述部分中包括将粘合剂放置在所述第一半导体封装体的背部表面上。
15.一种电子设备，包括：
印刷电路板；
导电凸块，所述导电凸块被耦合到所述印刷电路板；以及
半导体封装体，所述半导体封装体被耦合到所述导电凸块，所述半导体封装体包括：
折叠柔性衬底，所述折叠柔性衬底形成包括导电触点以及上部部分和下部部分的内表面和外表面；
第一半导体封装体，所述第一半导体封装体位于所述折叠柔性衬底的所述上部部分与所述下部部分之间并且被电耦合到所述折叠柔性衬底的所述下部部分的所述内表面的所述导电触点，所述第一半导体封装体包括在所述第一半导体封装体的外部周界处的凹角；
粘合材料，所述粘合材料位于所述凹角处并且位于所述第一半导体封装体的背部表面与所述柔性衬底的所述上部部分之间，并且所述粘合材料将所述折叠柔性衬底的所述上部部分与所述下部部分耦合在一起；以及
第二半导体封装体，所述第二半导体封装体被电耦合到所述折叠柔性衬底的所述外表面上的所述导电触点中的第一组，所述第一组导电触点在所述折叠柔性衬底的所述上部部分上。
16.如权利要求15所述的电子设备，其中，所述半导体封装体被耦合到所述折叠柔性衬底的所述外表面和所述下部部分上的所述导电凸块。
17.如权利要求15所述的电子设备，其中，所述导电凸块中的第一组在所述折叠柔性衬底的所述下部部分处的所述外表面上，并且所述粘合材料在所述折叠柔性衬底的所述下部部分处的所述内表面上，从而使得所述第一组导电凸块与所述粘合材料相反。
18.如权利要求15所述的电子设备，其中，所述粘合材料为硅树脂。
19.如权利要求15所述的电子设备，其中，所述粘合材料在被硬化时比所述第一半导体封装体的包封材料在被硬化时更有弹性。
20.如权利要求15所述的电子设备，其中，所述第一半导体封装体包括包封材料并且所述凹角被形成在所述包封材料中。
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