CN107492527B - Stacked semiconductor packages with compliant corners - Google Patents

Stacked semiconductor packages with compliant corners Download PDF

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Publication number
CN107492527B
CN107492527B CN201710289319.4A CN201710289319A CN107492527B CN 107492527 B CN107492527 B CN 107492527B CN 201710289319 A CN201710289319 A CN 201710289319A CN 107492527 B CN107492527 B CN 107492527B
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China
Prior art keywords
semiconductor package
flexible substrate
adhesive material
stacked
package
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CN201710289319.4A
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Chinese (zh)
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CN107492527A (en
Inventor
J·塔利多
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STMicroelectronics International NV
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STMicroelectronics lnc USA
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Abstract

The application relates to a stacked semiconductor package having compliant corners. One or more embodiments relate to stacked packages, such as package-on-package (PoP) packages, stacked on a flexible folded substrate. The stacked packages have compliant corners. In particular, the stacked packages include adhesive material at the corners between layers of the folded substrate. The adhesive material has a low modulus of elasticity, such as, for example, that of a silicone adhesive. The low elastic modulus of the adhesive material creates a compliant angle for the stacked package. The adhesive material fills openings formed around the bottom semiconductor packages of the stacked package between the folded substrates. In this regard, the bottom semiconductor package may have pull-back corners or re-entrant corners, and the adhesive material fills the openings formed by the re-entrant corners. These re-entrant corners may be of any size or shape.

Description

Stacked semiconductor packages with compliant corners
Technical Field
Embodiments of the present disclosure relate to stacked semiconductor packages and methods of forming stacked semiconductor packages.
Background
The increasing demand for smaller electronic devices forces manufacturers of such devices to increase component density and decrease component size wherever possible within the device. Semiconductor manufacturers have responded by: increasing the use of chip scale packaging and wafer level packaging techniques to minimize the footprint of semiconductor packages sometimes reduces the package to a size that is close to the size of the semiconductor die itself. In particular, the use of direct surface mountable ball grid array and flip chip configurations has been implemented, thereby reducing the size of the semiconductor package.
Stacked packages (also referred to as Package-on-Package (PoP) packages) have been formed by vertically stacking packages, thereby saving space on a Printed Circuit Board (PCB). the stacked packages are vertically stacked packages and include one or more top packages vertically stacked above a bottom Package.
Disclosure of Invention
One or more embodiments relate to stacked packages, such as package-on-package (PoP) packages, stacked on a flexible folded substrate. The stacked packages have compliant angles that, in some embodiments, reduce the rigidity of the stacked packages. In particular, these stack packages include adhesive material at the corners of the stack (such as between layers of a folded substrate). The adhesive material has a low modulus of elasticity, such as, for example, that of a silicone adhesive. The low modulus of elasticity of the adhesive material creates a compliant angle for the stacked package and accommodates at least some of the warpage that may typically be caused in the stacked package. In addition, the adhesive improves the life of the conductive bumps at the corners of the stacked package when coupling the stacked package to another device (such as a PCB).
In at least one embodiment, the adhesive material fills an opening between the folded substrates formed around a bottom semiconductor package of the stacked package. In this regard, the bottom semiconductor package may have pull-back corners or re-entrant corners, and the adhesive material fills the openings formed by the re-entrant corners. The re-entrant corners in the openings and the bonding material may be of any size or shape.
Drawings
In the drawings, identical reference numbers identify similar elements. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale.
1A-1C illustrate various views of a stacked package according to one embodiment;
fig. 2 shows a side view of the stacked package of fig. 1A-1C coupled to a PCB.
Fig. 3 illustrates a side view of a stacked package according to another embodiment.
Fig. 4A-4G illustrate cross-sectional views of various stages of an assembly process for forming a stacked package, such as the stacked package of fig. 1A-1C, according to an embodiment of the present disclosure.
Fig. 5 is a table comparing solder life of semiconductor packages having compliant corners, such as the packages of fig. 1A-1C, to solder life of packages not having compliant corners.
Detailed Description
It will be understood that, although specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure.
In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and semiconductor (such as semiconductor power device) processing methods that include embodiments of the subject matter disclosed herein have not been described in detail so as not to obscure the description of other aspects of the disclosure.
Fig. 1A is an isometric view of a package on package (PoP) package or stack package 10 according to one embodiment. As will be explained in detail below, fig. 1B is a side view of the stacked package 10, and fig. 1C is a top view of the stacked package 10, illustrating the reentrant corners of the bottom package in dashed lines.
The stacked package 10 includes a top semiconductor package 12 and a bottom semiconductor package 14 coupled to a folded flexible substrate 16. The top semiconductor package 12 and the bottom semiconductor package 14 include one or more semiconductor chips 30 (fig. 4A) that integrate one or more electrical components, such as integrated circuits, as are well known in the art. The integrated circuit may be an analog circuit or a digital circuit implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the chip and electrically interconnected according to the electrical design and function of the chip.
Surrounding the semiconductor chip 30 is an encapsulant material 20, which is a dielectric material that protects the electrical components therein (such as the semiconductor chip and the conductive wires or bumps) from external environmental sources of damage (such as corrosion, physical damage, moisture damage, or other causes of damage to the electrical components). The encapsulant material 20 may be a molding compound, such as a polymer resin. Although only two semiconductor packages are shown in the stacked package, it should be understood that the stacked package may include a greater number of semiconductor packages in the stack and may further include more folds in the flexible substrate or another substrate.
The flexible substrate 16 electrically and mechanically couples the top semiconductor package 12 and the bottom semiconductor package 14 together. The flexible substrate 16 is folded at the folding portion 16a to form an upper portion 16b and a lower portion 16 c. The top semiconductor package 12 is directly coupled to the upper portion 16b of the flexible substrate 16 and the bottom semiconductor package 14 is directly coupled to the lower portion 16c of the flexible substrate 16.
The flexible substrate 16 includes conductive contacts, conductive traces, and insulating material, as is well known in the art. In particular, the flexible substrate includes conductive contacts on the upper portion 16b and the lower portion 16 c. The various conductive contacts are coupled together on the flexible substrate 16 by conductive traces that extend through the folded portion 16a of the flexible substrate 16 as is well known in the art. In that regard, one or more conductive contacts of the upper portion 16b are coupled to conductive contacts of the lower portion 16c by conductive traces extending through the folded portion 16a of the flexible substrate 16. The insulating material of the flexible substrate 16 isolates the various conductive components therein.
The flexible substrate 16 has an inner surface 16d and an outer surface 16 e. The inner surface 16d and the outer surface 16e are located on both the upper portion 16b and the lower portion 16c of the flexible substrate 16. The top semiconductor package 12 is coupled to the conductive contacts of the outer surface 16e of the upper portion 16b of the flexible substrate 16 by a first set of conductive bumps (such as solder bumps) 22 a. The first set of conductive bumps 22a are coupled to one or more electrical components of the semiconductor chip within the top semiconductor package 12, as is well known in the art.
The inner surface 16d of the flexible substrate 16 faces the first and second surfaces of the bottom semiconductor package 14. Specifically, the inner surface 16d of the flexible substrate 16 (at the upper portion 16b thereof) faces the second surface of the bottom semiconductor package 14, and the inner surface 16d of the lower portion 16c of the flexible substrate 16 faces the first surface of the bottom semiconductor package 14. The bottom semiconductor package 14 is electrically coupled to conductive contacts on the inner surface 16d of the lower portion 16c of the flexible substrate 16. Specifically, the electrical components of the semiconductor chip within the bottom semiconductor package 14 are electrically coupled to the conductive contacts of the inner surface 16d of the lower portion 16c of the flexible substrate 16. For example, the semiconductor chips may be coupled by conductive bumps in a flip chip configuration or by conductive wires, as is well known in the art.
A second set of conductive bumps (e.g., solder balls) 22b are formed on the conductive contacts on the outer surface 16e of the lower portion 16c of the flexible substrate 16. As shown in fig. 2, the second set of conductive bumps 22b are configured to couple the stacked package to another device, such as a PCB 28. As will be apparent to those of ordinary skill in the art, the semiconductor chips in the top and bottom semiconductor packages 12, 14 are electrically coupled to the electrical components of the PCB28 through the second set of conductive bumps 22b on the lower portion 16c of the flexible substrate 16. The PCB28 is part of an electronic device, which may be any electronic device (such as a smartphone, notebook computer, or any other electronic device), including devices that are part of a larger device.
At the corners of the stacked package 10, between the inner surfaces 16d of the upper and lower portions 16b, 16c of the flexible substrate 16 is an adhesive material 24. Adhesive material 24 is any adhesive material having a low young's modulus, such as the young's modulus of a silicone adhesive. For example, in one embodiment, the young's modulus of the bonding material is between about 0.001 and 0.05 GPa. Specifically, the young's modulus of the adhesive material is smaller than the young's modulus of the encapsulating material 20 of the semiconductor package. In that regard, the adhesive material 24 is an elastomeric material that allows the stacked package 10 to be more compliant, particularly at the corners of the stacked package, thereby providing compliant corners for the package. Since the adhesive material 24 is an elastically deformable material, the warpage of the stacked package 10 is reduced. Additionally, as will be explained in more detail with reference to fig. 5, the compliant angle of the stacked package 10 extends the life of the conductive bumps of the stacked package (particularly the second set of conductive bumps 22 b). In addition, the adhesive material 24 helps mechanically couple the upper portion 16b and the lower portion 16c of the flexible substrate 16 together. In one embodiment, the adhesive material 24 is a silicone or silicone-based adhesive.
The adhesive material 24 fills an opening 34 (fig. 4C) formed by a recess in the bottom semiconductor package 14 between the upper portion 16b and the lower portion 16C of the flexible substrate 16. Specifically, the bottom semiconductor package 14 has reentrant corners 33 (fig. 4C) that create openings 34 at the corners of the stacked package 10 between the upper portion 16b and the lower portion 16C of the flexible substrate 16. More specifically, the encapsulating material 20 of the bottom semiconductor package 14 includes reentrant corners 33 as best shown in fig. 4C. The adhesive material 24 fills (or at least substantially fills) the re-entrant corners of the bottom semiconductor package 14 in the region between the upper portion 16b and the lower portion 16c of the flexible substrate 16.
Fig. 1C illustrates, in phantom, the shape of the adhesive material 24, which in the illustrated embodiment is square. Adhesive material 24 fills the reentrant corners of bottom semiconductor package 14, which may have any variety of shapes, such as triangular shapes, rectangular shapes, or any other suitable shape.
In operation of the stacked package 10, the top semiconductor package 12 and the bottom semiconductor package 14 are in electrical communication with the PCB28 through the flexible substrate 16 and the first and second sets of conductive bumps 22 b. One or both of the top semiconductor package 12 and the bottom semiconductor package 14 may also be configured for communication with each other through the flexible substrate 16.
As described above, the stacked package 10 having the adhesive material 24 filling the corners provides improved Board Level Reliability (BLR) after board mounting. The flexibility of the adhesive material 24 may relieve stress on the stacked package 10, which has been determined to be highest at the corners of the stacked package. The adhesive material 24 between the upper portion 16b and the lower portion 16c of the flexible substrate 16 extends the life of the first and/or second set of conductive bumps 22 after the stacked package 10 has been coupled to another device or PCB 28. Specifically, the adhesive material 24 absorbs the stress applied to the conductive bumps 22 at the corners of the package on package 10. Therefore, the adhesive material 24 is elastically deformed and relieves stress in the package body, rather than the conductive bump 22 being broken, thereby reducing warpage of the package body.
Fig. 3 illustrates a side view of a stacked package 10a according to another embodiment. The stacked package 10a of fig. 3 is substantially the same as the stacked package 10 of fig. 1, except that the adhesive material 24 in the stacked package 10a of fig. 3 not only fills the opening in the corner between the upper portion 16b and the lower portion 16c of the flexible substrate 16, but also is located between the bottom semiconductor package 14 and the upper portion 16b of the flexible substrate 16. That is, the adhesive material 24 fills the opening formed by the reentrant corner of the bottom package 14 as described with reference to fig. 1A-1C, and a portion of the adhesive 24 is between the back surface of the bottom package 14 and the upper portion 16b of the flexible substrate 16. This portion of adhesive material between the backside surface of the bottom package 14 and the inner surface 16d of the upper portion 16b of the flexible substrate 16 helps to adhere the upper portion 16b of the flexible substrate 16 to the bottom semiconductor package 14 and/or the lower portion 16c of the flexible substrate 16. This portion of the adhesive material 24 may also provide enhanced flexibility of the stacked package 10a to address warpage issues and mitigate conductive bump cracking.
Fig. 4A-4G illustrate cross-sectional views of various stages of an assembly process for forming a stacked package, such as the stacked package of fig. 1A-1C, according to an embodiment of the present disclosure.
As shown in fig. 4A, the semiconductor chip 30 is placed on and electrically and mechanically coupled to the inner surface 16d of the lower portion 16c of the flexible substrate 16. Specifically, the first surface of the semiconductor chip 30 may be coupled to the inner surface 16d of the lower portion 16c of the flexible substrate 16. In fig. 4A, the second surface of the semiconductor chip 30 faces upward. The second surface of the semiconductor chip 30 is the active surface of the chip including the electrical components discussed above. A first end of the conductive wire 32 is coupled to a bond pad of the active surface of the semiconductor chip 10 and a second end of the conductive wire 32 is coupled to a conductive contact of the flexible substrate 16.
Although not shown, the semiconductor chip 30 may also be coupled to the inner surface 16d of the lower portion 16c of the flexible substrate 16 by a flip chip arrangement. That is, conductive bumps may be coupled between bond pads of the active surface of the semiconductor chip 30 and conductive contacts of the flexible substrate 16, as is well known in the art.
As shown in fig. 4B, the semiconductor chip 30 is encapsulated with an encapsulating material 20 to form the bottom semiconductor package 14. Specifically, a molding step may be performed in which a molding compound (such as a resin) is introduced into a mold that accommodates the flexible substrate 16 and the semiconductor chip 30. The molding compound flows around the semiconductor chip 30 and the conductive wiring and hardens over time. The hardening process may include one or more curing steps. The bottom semiconductor package 14 is formed with a reentrant corner 33 for forming an opening 34 as shown in fig. 4C. For example, the mold is shaped to form the encapsulant material 20 with reentrant corners 33 such that the openings 34 remain at the corners of the package. Fig. 4C shows the bottom semiconductor package 14 in plan view and shows the opening 34 and reentrant corners 33 at each of the four corners of the package.
As shown in fig. 4D, adhesive material 24 is dispensed into an opening 34 formed by reentrant corners 33 of bottom semiconductor package 14. For example, silicone is deposited in the openings 34. The adhesive material 24 hardens over time. In one embodiment, the adhesive material 24 may involve a curing step for hardening.
In some embodiments, the steps illustrated in fig. 4A-4D are performed on a plurality of semiconductor chips, such that a plurality of bottom semiconductor packages 14 are formed on a single flexible substrate strip or array. In such embodiments, the flexible substrate may be subjected to scribing operations, including sawing, laser or perforation to separate into individual flexible substrates.
As shown in fig. 4E, an upper portion of the flexible substrate 16 is folded over the second surface of the bottom semiconductor package 14 and the adhesive material 24 to form a folded portion 16 a. The adhesive material 24 in the opening 34 adheres the upper portion 16b of the flexible substrate 16 to the lower portion 16c of the flexible substrate 16.
As shown in fig. 4F, a second set of conductive bumps 22b are formed on the conductive contacts on the outer surface of the lower portion 16c of the flexible substrate 16 using standard semiconductor bumping techniques.
As shown in fig. 4G, the top semiconductor package 12 is coupled to the outer surface 16e of the upper portion 16b of the flexible substrate 16 using a first set of conductive bumps 22 a. The top semiconductor package 12 is any previously formed semiconductor package. Details of forming the top semiconductor package 12 are well known in the art and are not provided herein for the sake of brevity. The first set of conductive bumps 22a may first be formed on either the conductive contacts of the outer surface 16e of the upper portion 16b of the flexible substrate 16 or the wires or contacts of the top semiconductor package 12 itself. As is well known in the art, after the first set of conductive bumps 22a between the flexible substrate 16 and the top semiconductor package 12 are used to place them together, the first set of conductive bumps 22a may be subjected to a reflow step that reflows and adheres the first set of conductive bumps 22a to the flexible substrate 16 and the conductive bumps of the top semiconductor package 12.
The assembly process may be performed in a different order than that described above. For example, the top semiconductor package 12 may be coupled to the upper portion 16b of the flexible substrate 16 prior to folding the flexible substrate.
Fig. 5 shows a graph illustrating a comparison of the life span of conductive bumps of stacked packages having compliant corners according to the embodiments of fig. 1A-1C with the life span of conductive bumps of stacked packages not having compliant corners according to the related art. As shown in the graph, the conductive bumps of the stacked package having compliant corners have a longer lifetime, thereby improving board-level reliability of the stacked package.
The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the application data sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims (20)

1. A stacked semiconductor package, comprising:
a flexible substrate having a first surface and a second surface, the first surface and the second surface including conductive contacts, the flexible substrate being folded and forming an upper portion and a lower portion;
a first semiconductor package positioned between the upper portion and the lower portion of the flexible substrate, the first semiconductor package comprising a reentrant angle;
an adhesive material located at the recessed corners and between a back surface of the first semiconductor package and the upper portion of the flexible substrate, the adhesive material coupling the upper portion and the lower portion of the flexible substrate together; and
a second semiconductor package coupled to the upper portion of the flexible substrate.
2. The stacked semiconductor package of claim 1, wherein the adhesive material comprises silicone.
3. The stacked semiconductor package of claim 1, wherein the adhesive material has a first young's modulus and the first semiconductor package comprises an encapsulation material having a second young's modulus greater than the first young's modulus, wherein the encapsulation material of the first semiconductor package has the reentrant angle.
4. The stacked semiconductor package of claim 1, wherein the reentrant corners of the first semiconductor package form at least one of square openings, triangular openings, and rectangular openings.
5. The stacked semiconductor package of claim 1, wherein the adhesive material is located at a corner of the stacked semiconductor package.
6. The stacked semiconductor package of claim 1, comprising an adhesive material between a back surface of the first semiconductor package and the upper portion of the flexible substrate.
7. The stacked semiconductor package of claim 1 wherein the stacked semiconductor package is coupled to a printed circuit board.
8. A method of forming a stacked semiconductor package, comprising:
coupling a first semiconductor chip to a first surface of a first portion of a flexible substrate;
encapsulating the first semiconductor chip with an encapsulation material to form a first semiconductor package having a reentrant corner, wherein portions of the first surface of the first portion of the flexible substrate are exposed by the reentrant corner;
placing an adhesive material in the portion exposed by the re-entrant angle of the first surface of the first portion of the flexible substrate; and
folding a second portion of the flexible substrate over the first portion of the flexible substrate,
wherein the adhesive material couples the first and second portions of the flexible substrate together and a portion of the adhesive material is between a back surface of the first semiconductor package and the second portion.
9. The method of claim 8, further comprising: coupling a second semiconductor package to the second portion of the flexible substrate to form a stacked package.
10. The method of claim 9, further comprising: the stacked package is coupled to a printed circuit board with conductive bumps.
11. The method of claim 8, wherein the adhesive material is a silicone adhesive material.
12. The method of claim 8, wherein the adhesive material adheres the first and second portions of the flexible substrate together.
13. The method of claim 8, wherein the reentrant corner of the first semiconductor chip is one of square, rectangular, or triangular.
14. The method of claim 8, wherein placing an adhesive material in the portion of the first surface of the first portion of the flexible substrate comprises placing an adhesive on a back surface of the first semiconductor package.
15. An electronic device, comprising:
a printed circuit board;
a conductive bump coupled to the printed circuit board; and
a semiconductor package coupled to the conductive bumps, the semiconductor package comprising:
a folded flexible substrate forming inner and outer surfaces including conductive contacts and upper and lower portions;
a first semiconductor package positioned between the upper portion and the lower portion of the folded flexible substrate and electrically coupled to the conductive contacts of the inner surface of the lower portion of the folded flexible substrate, the first semiconductor package comprising a reentrant corner at an outer perimeter of the first semiconductor package;
an adhesive material located at the recessed corners and between a back surface of the first semiconductor package and the upper portion of the flexible substrate, and coupling the upper portion and the lower portion of the folded flexible substrate together; and
a second semiconductor package electrically coupled to a first set of the conductive contacts on the outer surface of the folded flexible substrate, the first set of conductive contacts being on the upper portion of the folded flexible substrate.
16. The electronic device defined in claim 15 wherein the semiconductor package is coupled to the conductive bumps on the outer surface and the lower portion of the folded flexible substrate.
17. The electronic device of claim 15, wherein a first set of the conductive bumps are on the outer surface at the lower portion of the folded flexible substrate and the adhesive material is on the inner surface at the lower portion of the folded flexible substrate such that the first set of conductive bumps are opposite the adhesive material.
18. The electronic device of claim 15, wherein the adhesive material is silicone.
19. The electronic device of claim 15, wherein the adhesive material is more elastic when hardened than an encapsulation material of the first semiconductor package when hardened.
20. The electronic device defined in claim 15 wherein the first semiconductor package comprises an encapsulant material and the reentrant corners are formed in the encapsulant material.
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US8278141B2 (en) * 2008-06-11 2012-10-02 Stats Chippac Ltd. Integrated circuit package system with internal stacking module
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US8034661B2 (en) 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
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