KR102549580B1 - 플립 칩 - Google Patents

플립 칩 Download PDF

Info

Publication number
KR102549580B1
KR102549580B1 KR1020160074068A KR20160074068A KR102549580B1 KR 102549580 B1 KR102549580 B1 KR 102549580B1 KR 1020160074068 A KR1020160074068 A KR 1020160074068A KR 20160074068 A KR20160074068 A KR 20160074068A KR 102549580 B1 KR102549580 B1 KR 102549580B1
Authority
KR
South Korea
Prior art keywords
layer
bump
flip chip
electrode pad
substrate
Prior art date
Application number
KR1020160074068A
Other languages
English (en)
Other versions
KR20170141067A (ko
Inventor
심영석
김형주
박주훈
김창덕
Original Assignee
(주)와이솔
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)와이솔 filed Critical (주)와이솔
Priority to KR1020160074068A priority Critical patent/KR102549580B1/ko
Priority to US15/617,425 priority patent/US10546827B2/en
Priority to CN201710430817.6A priority patent/CN107507809B/zh
Publication of KR20170141067A publication Critical patent/KR20170141067A/ko
Application granted granted Critical
Publication of KR102549580B1 publication Critical patent/KR102549580B1/ko

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02175—Flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02185—Shape of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219—Material of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022—Protective coating, i.e. protective bond-through coating
    • H01L2224/02205—Structure of the protective coating
    • H01L2224/02206—Multilayer protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022—Protective coating, i.e. protective bond-through coating
    • H01L2224/0221—Shape of the protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022—Protective coating, i.e. protective bond-through coating
    • H01L2224/02215—Material of the protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05564—Only on the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05566—Both on and outside the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16014—Structure relative to the bonding area, e.g. bond pad the bump connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16052—Shape in top view
    • H01L2224/16055—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/07—Polyamine or polyimide
    • H01L2924/07025—Polyimide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명의 일 실시예에 따른 플립 칩은 기판; 상기 기판 상에 적층된 전극패드층; 상기 전극패드층의 양쪽 끝단에 적층된 패시베이션층; 상기 전극패드층 및 패시베이션층 상에 적층된 UBM층; 상기 UBM층 상에 형성된 범프;를 포함하고, 상기 전극패드층 상에 패시베이션층이 적층되지 않는 오프닝은 상기 범프의 너비보다 넓은 것을 특징으로 한다.

Description

플립 칩{Flip Chip}
본 발명은 플립 칩에 관한 것으로, 보다 상세하게는 초음파 본딩 시 크랙 발생을 방지할 수 있는 플립 칩에 관한 것이다.
일반적으로 반도체 기판에 여러 공정들을 수행하여 복수개의 반도체 칩들을 형성한 후, 다양한 패키징 공정을 수행하며 각 반도체 칩들을 인쇄회로기판에 실장하여 반도체 패키지를 형성한다.
이와 같이 반도체 패키지를 형성하기 위해서는 금속 리드 등의 와이어(wire)를 반도체 칩에 부착시켜 반도체 칩을 기판과 접속시키는 와이어 본딩 공정과, 반도체 칩에 구비된 전극에 범프(Bump)를 형성하여 범프와 기판의 패드를 접속하는 플립 칩 패키지 공정 등이 이용되고 있다.
이때, 상기 플립 칩 패키지는 반도체 칩과 기판이 대향하도록 배치되어 반도체 칩에 구비된 도전성 범프들과 기판의 패드들이 일대일 방식으로 전기적으로 연결된 구조를 갖게 되며, 반도체 칩과 기판 사이에는 언더필(underfill)층이 형성되어 도전성 범프를 외부 충격으로부터 보호하도록 구성된다.
특히, 최근 반도체 칩의 동작 속도가 증가하면서 기존의 와이어 본딩 방식으로는 패키지의 특성을 만족시키기 어려워지고 있으며, 그에 따라 고기능 반도체 칩의 패키지에서는 반도체 칩과 기판을 직접 연결하는 플립 칩 패키지 공정의 이용이 증가되고 있다.
도 1은 종래 기술에 따른 플립 칩 패키지의 단면도를 나타낸 것이다.
도 1을 참조하면, 반도체 칩(1)의 하면에는 전극패드(2)가 형성되어 있고 전극패드(2)에는 인쇄회로기판(4)과의 전기적 접속을 위해 금(Au) 재질의 범프(3)가 형성되어 있다.
한편, 반도체 칩(1)이 실장되는 인쇄회로기판(4)에는 상기 범프(3)가 안착되는 본딩패드(5)가 형성되어 있고, 본딩패드(5)에는 전도성을 증가시키며 본딩패드의 산화를 방지하기 위해 금(Au) 재질로 코팅된 접촉층(6)이 형성된다. 그리고 반도체 칩(1)과 인쇄회로기판(4) 사이에는 열경화성 접착제인 에폭시 수지 등의 언더필 수지(7)가 형성되어 범프 사이의 공간을 보강함으로써, 온도 변화에 따른 열팽창, 열수축 등에 의해 반도체 칩과 범프의 경계 부위에 응력이 집중되어 불량이 발생되는 것을 방지한다.
반도체 칩(1)과 인쇄회로기판(4)의 전기적 접속을 위해 반도체 칩(1)의 범프(3)와 접촉층(6)이 접촉되도록 반도체 칩(1)을 인쇄회로기판(4)에 안착한 후 열과 압력을 가하게 되면 범프(3)와 본딩패드(5)가 접합하게 된다.
초음파 본딩 방법의 경우, 반도체 칩에 초음파 에너지를 인가하고 하중을 가하면서 가열하여 범프가 열, 압력 및 초음파에 의한 에너지로 인해 용융되어 패드에 접합됨으로써 반도체 칩과 인쇄회로기판이 전기적으로 연결된다.
하지만, 종래의 이러한 구조에 의하면 본딩시 가해지는 압력으로 인해 반도체 플립 칩의 전극패드에 크랙(Crack)이 발생하는 문제점이 있다.
대한민국 특허공개공보 제 10-2009-0015760호
본 발명이 해결하고자 하는 과제는, 초음파 본딩시에도 크랙이 발생하지 않는 플립 칩을 제공하는 것이다.
상기와 같은 기술적 과제를 해결하기 위해, 본 발명의 일 실시예에 따른 플립 칩은 기판; 상기 기판 상에 적층된 전극패드층; 상기 전극패드층의 양쪽 끝단에 적층된 패시베이션층;상기 전극패드층 및 패시베이션층 상에 적층된 UMB층; 상기 UBM층 상에 형성된 범프;를 포함하고, 상기 전극패드층 상에 패시베이션층이 적층되지 않는 오프닝은 상기 범프의 너비보다 넓은 것을 특징으로 한다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 반도체 플립 칩은 상기 기판과 전극패드층 사이에 적층된 다층 패턴층을 더 포함할 수 있다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 다층 패턴층은 다른 메탈 층과의 연결을 위한 비아(via)가 형성될 수 있다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 알루미늄 패드층 및 패시베이션층의 두께는 0.35um 이상일 수 있다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 범프는 금을 포함할 수 있다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 오프닝은 사각형, 원형, 및 팔각형 형상 중 어느 하나의 형상이고, 상기 범프는 원형 및 사각형 중 어느 하나의 형상일 수 있다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 UBM층의 양쪽 끝단에는 본딩 시 범프에 가해지는 힘을 분산하기 위한 완충층을 더 포함할 수 있다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 완충층은 폴리이미드일 수 있다.
또한, 본 발명의 일 실시예에 따른 플립 칩에서, 상기 기판은 CMOS 공정을 사용한 실리콘 웨이퍼일 수 있다.
본 발명에 의한 플립 칩에 의하면, 초음파 본딩시에 패드에 크랙이 발생하는 것을 방지할 수 있다.
특히, 와이어 본딩 패키지 어셈블리 공정을 사용하는 CMOS(Complementary metal-oxide-semiconductor) 공정 웨이퍼 본딩시에 금(Au) 범프 플립 본딩 공정을 사용할 수 있게 함으로써 다양한 패키지에 응용할 수 있다.
도 1은 종래기술에 따른 플립칩 패키지의 단면도를 나타낸 것이다.
도 2는 본 발명의 일 실시예에 따른 플립 칩의 범프 형성 전 단면도를 나타낸 것이다.
도 3은 본 발명의 일 실시예에 따른 플립 칩의 범 단면도를 나타낸 것이다.
도 4는 본 발명의 다른 실시예에 따른 플립칩의 단면도를 나타낸 것이다.
도 5는 본 발명의 실시예에 따른 오프닝 및 범프의 형상을 나타낸 것이다.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시예를 가질 수 있는바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 그러나, 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다.
도면들에 있어서, 본 발명의 실시 예들은 도시된 특정 형태로 제한되는 것이 아니며 명확성을 기하기 위하여 과장된 것이다. 본 명세서에서 특정한 용어들이 사용되었으나. 이는 본 발명을 설명하기 위한 목적에서 사용된 것이며, 의미 한정이나 특허 청구 범위에 기재된 본 발명의 권리 범위를 제한하기 위하여 사용된 것은 아니다.
본 명세서에서 ‘및/또는’이란 표현은 전후에 나열된 구성요소들 중 적어도 하나를 포함하는 의미로 사용된다. 또한, ‘연결되는/결합되는’이란 표현은 다른 구성요소와 직접적으로 연결되거나 다른 구성요소를 통해 간접적으로 연결되는 것을 포함하는 의미로 사용된다. 본 명세서에서 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함한다. 또한, 명세서에서 사용되는 ‘포함한다’또는 ‘포함하는’으로 언급된 구성요소, 단계, 동작 및 소자는 하나 이상의 다른 구성요소, 단계, 동작 및 소자의 존재 또는 추가를 의미한다.
또한, '제1, 제2' 등과 같은 표현은, 복수의 구성들을 구분하기 위한 용도로만 사용된 표현으로써, 구성들 사이의 순서나 기타 특징들을 한정하지 않는다.
실시예들의 설명에 있어서, 각 층(막), 영역, 패턴 또는 구조물들이 기판, 각 층(막), 영역, 패드 또는 패턴들의 "상/위(on)"에 또는 "하/아래(under)"에 형성된다는 기재는, 직접(directly) 또는 다른 층을 개재하여 형성되는 것을 모두 포함한다. 각 층의 상/위 또는 하/아래에 대한 기준은 도면을 기준으로 설명한다.
이하, 첨부된 도면을 참조하여 본 발명의 실시예에 따른 초음파 본딩용 플립칩의 구조 및 제조방법을 상세히 설명한다.
도 2는 본 발명의 일 실시예에 따른 플립 칩의 단면도로, 범프가 접착되기 전의 플립 칩을 도시한 것이고, 도 3은 범프(bump)가 접착된 플립 칩을 도시한 것이다.
도 2에서 (a)를 참조하면, 플립 칩은 반도체 기판(10), 상기 반도치 기판 상에 형성된 전극패드층(30), 및 상기 전극패드층(30) 상에 형성된 패시베이션층(40)을 포함한다.
상기 반도체 기판(10)은 CMOS(Complementary metal-oxide-semiconductor) 공정에 의해 생성된 실리콘(Si) 웨이퍼일 수 있다. 상기 CMOS 공정에 대해서는 상세한 설명을 생략하기로 한다.
상기 전극패드층(30)은 알루미늄층일 수 있으며, 상기 전극패드층(30)의 두께는 얇아야 하며 변형에 의해 패시베이션층(40)의 형상 변화를 주어서는 안된다. 상기 전극패드층(30)은 0.35um 이상 일 수 있다. 상기 전극패드층(30)에는 범프가 형성되어야 하기 때문에 패시베이션층(40)은 범프의 양쪽 끝단에 적층된다.
상기 패시베이션층(40)은 기판(10)과 전극패드층(30)의 끝단에 동시에 적층되어 기판(10)과 전극패드층(30)을 외부 물질로부터 오염되지 않도록 보호한다. 즉, 패시베이션층(40)은 수분과 같은 외부 오염물질로부터 소자를 보호한다. 상기 패시베이션층(40) 또한 얇은 것이 유리하며 두께는 0.35um 이상일 수 있다.
상기 패시베이션층(40)은 SiO2(SiN)와 같은 산화막이 사용될 수 있다.
상기 전극패드층(30)에서 패시베이션층(40)이 적층되지 않은 부분을 오프닝(opening)이라고 정의한다. 오프닝의 형상에는 제한이 없으며 사각형, 원형, 팔각형 등과 같은 다양한 형상이 사용될 수 있다. 오프닝은 범프가 형성되는 부분으로 절연기판과의 패키징시에 압착되어 접착부위가 넓어지므로 전체 체적을 고려하여 설계되어야 한다. 예를 들어 범프가 원형이고 지름이 44mm, 높이가 27um인 금(Au) 범프를 본딩하는 경우에는 본딩 후 압축되는 높이를 고려하여야 한다. 예를 들어, 본딩 후 범프의 높이가 10um 높이로 줄어든다고 예상되는 경우에는 이를 고려하여 오프닝의 넓이를 결정하여야 한다. 기존 범프의 체적과 10um로 압착된 후 범프의 체적은 동일해야 하므로 압착 후의 범프의 지름은 72mm가 된다. 따라서 오프닝은 72mm보다는 넓어야 하며 범프의 위치 틀어짐을 고려하여 오프닝을 설계할 수 있다. 오프닝의 너비는 본딩전 범프의 너비보다 넓어야 한다.
이를 수학식으로 나타내면 아래와 같다.
[수학식 1]
플립 본딩 전 범프 체적 = 플립 본딩 후 범프 체적
(44/2)2 ×π×27 = r2 ×π×10
2r=72.4mm
한편, 상기 전극패드층(30) 밑에는 다층 패턴층이 없는 것이 좋다. 다층 패턴층이 있는 경우에는 압착시 패턴층에 크랙이 발생할 수 있기 때문이다. 하지만 다층 패턴층이 필요한 경우에는 압축시 충격을 완화해 줄 수 있을 정도로 두꺼워야 한다. 상기 다층 패턴층의 두께는 1~5um일 수 있다. 그리고 다층 패턴층에는 층간을 연결하는 비아(via)를 형성하여 플립 본딩시 가해지는 충격을 완화할 수도 있다.
도 2에서 (b)는 제1 메탈패턴층(22) 및 제2 메탈패턴층(24)을 포함하는 다층 패턴층(20)이 기판(10)과 전극패드층(30) 사이에 적층된 예를 도시한 것이고, 도 2에서 (c)는 비아(26)가 형성된 다층 패턴층(20)이 기판(10)과 전극패드층(30) 사이에 적층된 예를 도시한 것이다.
도 2에서 (b) 또는 (c)와 같은 형태의 다층 패턴층(20)을 기판(10)과 전극패드층(30) 사이에 형성하는 경우, 플립 본딩 시에도 메탈층이 손상되는 것을 방지할 수 있다.
도 3은 상기 도 2에 범프를 형성한 예를 도시한 것으로, 도 3에서 (a)는 플립 본딩 전의 플립 칩 단면도를 도시한 것이고, (b)는 플립 본딩 후 범프가 압착된 상태의 단면도를 도시한 것이다.
도 3을 참조하면, 본 발명의 일 실시예에 따른 플립 칩은 기판(10), 상기 기판 상에 형성된 다층 패턴층(20), 상기 다층 패턴층 상에 형성된 전극패드층(30), 상기 전극패드층(30)의 양쪽 끝단에 형성되어 오프닝을 형성하고 소자를 보호하는 패시베이션층(40), 상기 전극패드층(30) 상에 형성된 UBM(Under Bump Metallurgy)층(50) 및 상기 UBM층(50) 상에 형성된 범프(60)를 포함한다.
상기 기판(10), 다층패턴층(20), 전극패드층(30), 및 패시베이션층(40)은 앞서 도 2에서 살펴본 구성과 동일하다.
상기 UBM층(50)은 텅스턴-티타늄층(W-Ti)으로 범프가 형성되기 전에 범프의 아래에 형성된다. 범프는 알루미늄에 대해 젖음성이 나쁘기 때문에 알루미늄 패드층에 범프가 붙게 하기 위한 접착 개선막(adhesion promotion layer)이 필요하고 또한 범프는 녹는점이 낮아 확산이 빠르게 일어나므로 범프의 확산이 칩에 일어나지 않도록 막아주는 확산 방지막(diffusion barrier)이 필요하다. 즉, UBM층(50)은 접착 개선 및 확산 방지의 역할을 한다.
상기 범프(60)는 UBM층(50) 위에 형성되며, 범프의 형상에는 제한이 없으나 플립 본딩 후 범프와 전극패드층(30)간의 간섭이 없어야 한다. 즉, 모양은 원형이나 사각형 등과 같이 다양한 형태가 가능하나 간섭을 없애기 위해서는 패드의 오프닝 사이즈를 고려한 범프 설계가 필요하다. 그리고 범프 사이즈는 범핑 후 범프의 접착력을 고려해야 한다. 범프(60) 성분은 금(Au)을 포함할 수 있다. 범프(60)의 경도(hardness)는 90HV 이하여야 한다. 플립 본딩 후 범프의 높이가 고려되어야 하기 때문이다.
플립 본딩 후에는 도 3(b)과 같이 범프가 압착되어야 하는데 경도가 너무 세면 압착에 의한 접착력이 저하되어 범프와 기판의 접촉층이 떨어질 수 있다.
도 4는 본 발명의 다른 실시예로써, 완충층(70)을 추가한 경우의 예를 도시한 것이다.
플립 본딩에 의한 UBM층(50)의 충격을 완화하기 위해 UBM층(50)의 양쪽 끝단에 완충층(70)을 형성할 수 있다. 완충층(70)으로는 폴리이미드(polyimide)층이 사용될 수 있다.
도 4에서 (a)는 플립 본딩 전을 도시한 것이고, 도 4에서 (b)는 플립 본딩 후를 도시한 것이다.
도 4에서 (b)를 참조하면, 플립 본딩시 범프(60)에 가해지는 압력이 완충층으로 분산되어 UBM층(50)을 보호할 수 있다.
도 5는 본 발명의 일 실시예에 따른 범프의 형상 및 그에 따른 오프닝의 예를 나타낸 평면도이다.
도 5에서 (a)는 범프가 원형이고 오프닝이 사각형, 원형, 및 팔각형인 경우를 왼쪽부터 차례로 나타낸 것이고, 도 5에서 (b)는 범프가 사각형이고 오프닝이 사각형, 원형, 및 팔각형인 경우를 왼쪽부터 차례로 나타낸 것이다.
앞서 설명한 바와 같이 범프 및 오프닝의 형상에 제한은 없으나 범프와 오프닝과의 간섭을 방지하기 위해서는 사각형 형상의 오프닝에 원형의 범프를 사용하는 것이 바람직하다.
이상에서 본 발명에 따른 실시예들이 설명되었으나, 이는 예시적인 것에 불과하며, 당해 분야에서 통상적 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 범위의 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호 범위는 다음의 특허청구범위에 의해서 정해져야 할 것이다.
10 : 기판
20 : 다층 패턴층
30 : 전극패드층
40 : 패시베이션층
50 : UBM층
60 : 범프
70 : 완충층

Claims (9)

  1. 기판;
    상기 기판 상에 적층된 전극패드층;
    상기 전극패드층의 양쪽 끝단에 적층된 패시베이션층;
    상기 전극패드층 및 패시베이션층 상에 적층된 UBM(Under Bump Matallurgy)층;
    상기 UBM층 상에 형성된 범프; 및
    상기 UBM층의 양쪽 끝단에 형성되어, 본딩 시 범프에 가해지는 압력을 분산시켜서 아래의 UBM층을 보호하는 완충층;
    을 포함하고,
    상기 전극패드층 상에 패시베이션층이 적층되지 않는 오프닝은 상기 범프의 너비보다 넓고,
    상기 UBM층 양쪽 끝단에 형성된 상기 완충층 사이의 오프닝도 상기 범프의 너비보다 넓으며,
    상기 완충층은 상기 범프의 대향면을 향해 계단 형상으로 형성된 것을 특징으로 하는 플립 칩.
  2. 제1항에 있어서,
    상기 기판과 상기 전극패드층 사이에 적층된 다층 패턴층을 더 포함하는 플립 칩.
  3. 제2항에 있어서,
    상기 다층 패턴층은 다른 메탈 층과의 연결을 위한 비아(via)가 형성된 플립 칩.
  4. 제1항에 있어서,
    상기 전극패드층과 상기 패시베이션층의 두께는 0.35um 이상인 플립 칩.
  5. 제1항에 있어서,
    상기 범프는 금을 포함하는 플립 칩.
  6. 제 1항에 있어서,
    상기 오프닝은 사각형, 원형, 및 팔각형 형상 중 어느 하나의 형상이고,
    상기 범프는 원형 및 사각형 중 어느 하나의 형상인 플립 칩.
  7. 삭제
  8. 삭제
  9. 삭제
KR1020160074068A 2016-06-14 2016-06-14 플립 칩 KR102549580B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020160074068A KR102549580B1 (ko) 2016-06-14 2016-06-14 플립 칩
US15/617,425 US10546827B2 (en) 2016-06-14 2017-06-08 Flip chip
CN201710430817.6A CN107507809B (zh) 2016-06-14 2017-06-09 倒装芯片

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160074068A KR102549580B1 (ko) 2016-06-14 2016-06-14 플립 칩

Publications (2)

Publication Number Publication Date
KR20170141067A KR20170141067A (ko) 2017-12-22
KR102549580B1 true KR102549580B1 (ko) 2023-06-29

Family

ID=60573049

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160074068A KR102549580B1 (ko) 2016-06-14 2016-06-14 플립 칩

Country Status (3)

Country Link
US (1) US10546827B2 (ko)
KR (1) KR102549580B1 (ko)
CN (1) CN107507809B (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148389B (zh) * 2018-07-11 2020-02-07 上海华虹宏力半导体制造有限公司 温度循环测试时阻止产生裂纹的器件和工艺方法
CN112071819B (zh) * 2019-06-11 2023-05-16 群创光电股份有限公司 电子装置
CN112038320A (zh) * 2020-08-05 2020-12-04 厦门通富微电子有限公司 一种基板及倒装芯片封装结构
TWI774218B (zh) * 2021-01-28 2022-08-11 欣興電子股份有限公司 金屬凸塊結構及其製作方法與驅動基板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110212615A1 (en) * 2007-02-05 2011-09-01 Chipmos Technologies Inc. Manufacturing method of a bump structure having a reinforcement member

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310699A (en) 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
JPH10209210A (ja) * 1997-01-20 1998-08-07 Sharp Corp 半導体装置及びその製造方法並びにその検査方法
US6448171B1 (en) * 2000-05-05 2002-09-10 Aptos Corporation Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
JP4324572B2 (ja) * 2005-03-03 2009-09-02 カシオマイクロニクス株式会社 バンプの形成方法
US7053490B1 (en) * 2005-07-27 2006-05-30 Semiconductor Manufacturing International (Shanghai) Corporation Planar bond pad design and method of making the same
JP2007273624A (ja) * 2006-03-30 2007-10-18 Fujitsu Ltd 半導体装置及びその製造方法
JP2008016514A (ja) 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US9466579B2 (en) * 2007-07-26 2016-10-11 Nxp B.V. Reinforced structure for a stack of layers in a semiconductor component
KR20090015760A (ko) 2007-08-09 2009-02-12 삼성전기주식회사 패키지 제조방법
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
TWI497669B (zh) * 2012-03-22 2015-08-21 矽品精密工業股份有限公司 形成於半導體基板上之導電凸塊及其製法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110212615A1 (en) * 2007-02-05 2011-09-01 Chipmos Technologies Inc. Manufacturing method of a bump structure having a reinforcement member

Also Published As

Publication number Publication date
KR20170141067A (ko) 2017-12-22
US20170358546A1 (en) 2017-12-14
CN107507809B (zh) 2020-11-03
US10546827B2 (en) 2020-01-28
CN107507809A (zh) 2017-12-22

Similar Documents

Publication Publication Date Title
JP4998268B2 (ja) 半導体装置及びその製造方法
US9129818B2 (en) Semiconductor device having conductive pads and a method of manufacturing the same
US8217520B2 (en) System-in-package packaging for minimizing bond wire contamination and yield loss
JP5529371B2 (ja) 半導体装置及びその製造方法
US20170125369A1 (en) Semiconductor package and method for manufacturing the same
US7262510B2 (en) Chip package structure
US8860215B2 (en) Semiconductor device and method of manufacturing the same
KR102549580B1 (ko) 플립 칩
US9887144B2 (en) Ring structure for chip packaging
US10607964B2 (en) Semiconductor device
JP6495692B2 (ja) 半導体装置及びその製造方法
JP2012009655A (ja) 半導体パッケージおよび半導体パッケージの製造方法
US20180315712A1 (en) Embedded substrate package structure
KR20080095677A (ko) 플립 칩 패키지 및 그 패키지 제조방법
JP2007242684A (ja) 積層型半導体装置及びデバイスの積層方法
JP6495130B2 (ja) 半導体装置及びその製造方法
JP2012009713A (ja) 半導体パッケージおよび半導体パッケージの製造方法
TWI467723B (zh) 半導體封裝件及其製法
JP4937856B2 (ja) 半導体装置及びその製造方法
US9978723B2 (en) Semiconductor device
KR20110076605A (ko) 반도체 패키지 및 그 제조 방법
JP2007134489A (ja) 半導体装置の製造方法及び半導体装置
KR20220005354A (ko) 반도체 소자용 범프 구조물
CN116613111A (zh) 电子封装件及其制法
KR20080020378A (ko) 플립 칩 패키지

Legal Events

Date Code Title Description
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant