CN107507809B - 倒装芯片 - Google Patents

倒装芯片 Download PDF

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Publication number
CN107507809B
CN107507809B CN201710430817.6A CN201710430817A CN107507809B CN 107507809 B CN107507809 B CN 107507809B CN 201710430817 A CN201710430817 A CN 201710430817A CN 107507809 B CN107507809 B CN 107507809B
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layer
chip
substrate
bump
electrode pad
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CN107507809A (zh
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沈映锡
金亨柱
朴柱勋
金昌德
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TIANJIN WEISHENG ELECTRONICS CO Ltd
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TIANJIN WEISHENG ELECTRONICS CO Ltd
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    • H01L2224/16058—Shape in side view being non uniform along the bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract

本发明一实施例的倒装芯片，其特征在于，包括：基板；层压在所述基板上的电极焊盘层；层压在所述电极焊盘层的两侧末端的钝化层；层压在所述电极焊盘层及所述钝化层上的UMB层；形成在所述UBM层上的凸点，所述电极焊盘层上未层压所述钝化层的开口的宽度大于所述凸点的宽度。本发明的倒装芯片能够防止超声波焊接时焊盘上产生裂纹。

Description

倒装芯片
技术领域
本发明涉及倒装芯片，更详细地说，涉及超声波焊接时能够防止裂纹产生的倒装芯片。
背景技术
一般而言，在半导体基板上实施多种工艺以形成多个半导体芯片之后，实施多种封装工艺并将各个半导体芯片贴装到印刷回路基板而形成半导体封装件。
如上所述，为了形成半导体封装件，利用将金属导线等的引线(wire) 粘贴到半导体芯片以将半导体芯片连接到基板的引线接合工艺、在半导体芯片所具备的电极上形成凸点(Bump)来连接凸点与基板的焊盘(pad)的倒装芯片封装工艺等。
此时，将所述倒装芯片封装件配置成半导体芯片与基板相对，从而具有半导体芯片所具备的多个导电性凸点与基板的多个焊盘以一对一方式电气性连接的结构，半导体芯片与基板之间形成底部填充(underfill)层以保护导电性凸点免受外部冲击。
尤其，最近随着半导体芯片的工作速度的增加，以往的引线接合方式已无法满足封装的特性，据此，在高功能半导体芯片的封装件中应用直接连接半导体芯片与基板的倒装芯片封装工艺的现象在逐渐增加。
图1示出传统技术的倒装芯片封装件的剖面图。
参照图1，半导体芯片1的下面形成电极焊盘2，电极焊盘2上形成金(Au) 材质的凸点3以与印刷回路基板4电气性地连接。
另外，贴装半导体芯片1的印刷回路基板4上形成用于放置所述凸点3 的焊盘5，焊盘5上形成为了增加传导性并防止焊盘氧化而用金(Au)材质镀膜的接触层6。而且，半导体芯片1与印刷回路基板4之间形成热硬化性粘合剂如环氧树脂等底部填充树脂7以加固凸点之间的空间，从而防止因温度变化产生的热膨胀、热收缩等而应力集中在半导体芯片与凸点的界限部位而产生不良的现象。
为了半导体芯片1与印刷回路基板4的电气性连接，将半导体芯片1放置到印刷回路基板4以使半导体芯片1的凸点3与接触层6接触，然后施加热与压力，实现凸点3与焊盘5的接合。
超声波焊接方法是向半导体芯片施加超声波能量并增加荷重地加热，凸点因热、压力及超声波的能量而熔融并接合到焊盘，从而电气性地连接半导体芯片与印刷回路基板。
但是，这种传统的结构存在因焊接时施加的压力导致半导体倒装芯片的电极焊盘上产生裂纹(Crack)的问题。
(在先技术文献)
(专利文献)
(专利文献1)韩国专利公开公报第10-2009-0015760号
发明内容
(要解决的技术问题)
本发明要解决的技术问题是提供一种超声波焊接时也不产生裂纹的倒装芯片。
(解决问题的手段)
为解决如所述的技术问题，本发明一实施例的倒装芯片的特征在于，包括：基板；层压在所述基板上的电极焊盘层；层压在所述电极焊盘层的两侧末端的钝化层；层压在所述电极焊盘层及所述钝化层上的UMB层；形成在所述UBM层上的凸点，所述电极焊盘层上未层压所述钝化层的开口的宽度大于所述凸点的宽度。
并且，本发明一实施例的倒装芯片中，还可包括层压在所述基板与所述电极焊盘层之间的多层图案层。
并且，本发明一实施例的倒装芯片中，所述多层图案层上可形成用于与其他金属层连接的导孔(via)。
并且，本发明一实施例的倒装芯片中，所述铝焊盘层及所述钝化层的厚度为0.35um以上。
并且，本发明一实施例的倒装芯片中，所述凸点可包括金。
并且，本发明一实施例的倒装芯片中，所述开口为四角形、圆形及八角形形状中的任意一个形状，所述凸点为圆形及四角形中的任意一个形状。
并且，本发明一实施例的倒装芯片中，所述UBM层的两侧末端还可包括缓冲层，用于分散接合时施加到凸点的力。
并且，本发明一实施例的倒装芯片中，所述缓冲层可以是聚酰亚胺。
并且，本发明一实施例的倒装芯片中，所述基板可以是使用CMOS工艺的硅片。
(发明的效果)
根据本发明的倒装芯片，能够防止超声波焊接时焊盘上产生裂纹的现象。
尤其，使用引线接合封装组件工艺的CMOS(Complementary metal-ox ide-semiconductor：互补型金属氧化物半导体)工艺晶片接合时可使用金(A u)凸点倒装焊工艺，从而能够应用到多种封装。
附图说明
图1示出传统技术中的倒装芯片封装的剖面图。
图2示出本发明一实施例的倒装芯片的形成凸点之前的剖面图。
图3示出本发明一实施例的倒装芯片的凸点剖面图。
图4示出本发明另一实施例的倒装芯片的剖面图。
图5示出本发明实施例的开口及凸点的形状。
符号说明
10：基板
20：多层图案层
30：电极焊盘层
40：钝化层
50：UBM层
60：凸点
70：缓冲层
具体实施方式
可对本发明实施多种变更，而且可具有多种实施例，但在附图中示出特定实施例并进行具体说明。但是，这并不是将本发明限定于特定实施形态，应理解为包括本发明的思想及技术范围内的所有变更、等同物乃至替代物。
附图中，本发明的实施例并不限定于示出的特定形态，而是以求明确而夸大的。本说明书中使用了特定的用语，但仅用于说明本发明，并不是为了限定意思或限定专利权利要求范围中记载的本发明的权利范围。
本说明书中“及/或”的表述是指包括前后罗列的构件中的至少一个的意思。并且，“连接的/结合的”的表述是指包括与其他构件直接连接或通过其他构件间接连接的情况。本说明书中，除了有特别说明之外，句子中的单数形式包括复数形式。并且，说明书中使用“包括”或“包括的”来说明的构件、步骤、动作及元件意味着一个以上的其他构件、步骤、动作及元件的存在或追加。
并且，“第一、第二”等表述的用途仅在于区分复数形式的构件，并不限定构件之间的顺序或其他特征。
实施例的说明中，各层(膜)、区域、图案或构造物形成在基板、各层(膜) 区域、垫或图案的“上/上方(on)”或“下/下方(under)”的记载包括直接 (directly)形成或夹杂其他层而形成。对各层的上/上方或下/下方的基准以附图为基准进行说明。
以下，参照附图详细说明本发明实施例的超声波焊接用倒装芯片的结构及制造方法。
图2示出本发明一实施例的倒装芯片的形成凸点之前的剖面图，示出粘接凸点之前的倒装芯片，图3示出已粘接凸点的倒装芯片。
参照图2的(a),倒装芯片包括半导体基板10、形成在所述半导体基板上的电极焊盘层30及形成在所述电极焊盘层30上的钝化层40。
所述半导体基板10可以是根据CMOS(Complementary metal-oxide-semiconductor)工艺生成的硅(Si)晶片。省略对所述CMOS工艺的具体说明。
所述电极焊盘层30可以是铝层，所述电极焊盘层30的厚度应较薄，不可因变形而导致钝化层40的形状变化。所述电极焊盘层30可以是0.35um以上。因所述电极焊盘层30上形成凸点，钝化层40层压在凸点的两侧末端。
所述钝化层40同时层压在基板10与电极焊盘层30的末端以保护基板 10与电极焊盘层30免受外部物质的污染。即，钝化层40可保护元件免受水分等外部污染物质的影响。优选地，所述钝化层40应较薄，厚度可以是 0.35um以上。
所述钝化层40可使用如SiO2(SiN)等氧化膜。
所述电极焊盘层30中未层压所述钝化层40的部分被称为开口 (opening)。对开口的形状无限制，可使用四角形、圆形、八角形等多种形状。开口是形成凸点的部分，其与绝缘基板封装时被压缩而粘接部位会变宽，因此应考虑整体体积进行设计。例如，凸点为圆形且接合直径为44mm, 高度为27um的金(Au)凸点时，应考虑接合后被压缩的高度。例如，预想接合后凸点的高度会减少到10um时，应考虑此而决定开口的宽度。现有凸点的体积和被压缩到10um后的凸点的体积应相同，因此压缩后的凸点的直径为72mm。因此，开口应宽于72mm，可考虑凸点的位置偏差来设计开口。开口的宽度应大于接合前的凸点的宽度。
用数学公式表示如下。
[公式1]
倒装焊之前的凸点体积＝倒装焊之后的凸点体积
(44/2)2×π×27＝r2×π×10
2r＝72.4mm
另外，优选地，所述电极焊盘层30的底部无多层图案层。若存在多层图案层，则压缩时图案层会产生裂纹。但是，需要多层图案层时，其厚度应足以缓和压缩时的冲击。所述多层图案层的厚度可以是1～5um。并且，多层图案层可形成连接层与层之间的导孔(via)以缓和倒装焊时施加的冲击。
图2的(b)示出包括第一金属图案层22及第二金属图案层24的多层图案层20层压在基板10与电极焊盘层30之间的例子，图2的(c)示出形成导孔26 的多层图案层20层压在基板10与电极焊盘层30之间的例子。
如图2的(b)或(c)等形态的多层图案层20形成于基板10与电极焊盘层30 之间时，倒装焊时也能防止金属层受损。
图3示出在所述图2上形成凸点的例子，图3的(a)示出倒装焊之前的倒装芯片剖面图，(b)示出倒装焊之后凸点被压缩状态的剖面图。
参照图3，本发明一实施例的倒装芯片包括：基板10；形成在所述基板上的多层图案层20；形成在所述多层图案层上的电极焊盘层30；形状所述电极焊盘层30的两侧末端而形成开口并保护元件的钝化层40；形成在所述电极焊盘层30上的UBM(Under BumpMetallurgy：凸点下金属层)层50；及形成在所述UBM层50上的凸点60。
所述基板10、多层图案层20、电极焊盘层30及钝化层40与前述图2的结构相同。
所述UBM层50为钨钛层(W-Ti)，在形成凸点之前形成在凸点的下面。凸点对铝的润湿性差，因此需要用粘合力增强膜(adhesion promotion layer) 来将凸点粘合到铝焊盘层，并且凸点的熔点低且快速扩散，因此需要防止芯片上发生凸点扩散的扩散防止膜(diffusion barrier)。即，UBM层50起到增强粘合力及防止扩散的作用。
所述凸点60形成在UBM层50上，对凸点的形状无限制，但倒装焊后凸点与电极焊盘层30之间应无干涉。即，形状可以是圆形或四角形等多种形态，但为了消除干涉等，应考虑焊盘的开口尺寸进行凸点设计。并且，凸点尺寸应考虑形成凸点后的凸点粘合力。凸点60的成分可包括金(Au)。凸点60的硬度(hardness)应为90HV以下。应考虑倒装焊后凸点的高度。
倒装焊后，应如图3的(b)地压缩凸点，若硬度太强，会因压缩而降低粘合力，导致凸点与基板的接触层分离。
图4示出作为本发明的另一实施例的增加缓冲层70的例子。
为了缓和倒装焊对UBM层50的冲击，可在UBM层50的两侧末端形成缓冲层70。作为缓冲层70，可使用聚酰亚胺(polyimide)层。
图4的(a)示出倒装焊之前，图4的(b)示出倒装焊之后。
参照图4的(b)，倒装焊时施加到凸点60的压力会分散到缓冲层而保护 UBM层50。
图5是示出本发明一实施例的凸点的形状及开口的例子的平面图。
图5的(a)中从左到右依次示出凸点为圆形且开口为四角形、圆形及八角形的情况，图5的(b)中从左到右依次示出凸点为四角形且开口为四角形、圆形及八角形的情况。
如前所述，对凸点及开口的形状无限制，但为了防止凸点与开口间的干涉，优选采用四角形形状的开口和圆形的凸点。
如上述地说明了本发明，但本发明所属技术领域的普通技术人员能够理解在维持本发明的技术思想和必要特征的情况下，能够以其他形态实施本发明。
因此，以上记载的实施例只是示例性的，并不是以前述的实施例来限定本发明的范围。并且，附图中示出的顺序图只是实施本发明时为了获得最优选的结果而示例性地示出的顺序，因此可增加其他步骤或删除部分步骤。
本发明的范围由专利权利要求范围而确定，但除了由专利权利要求范围的记载事项直接得出的构成之外，由与其等同的构成得出的所有变更或变形形态也包括在本发明的权利范围之内。

Claims (8)

1.一种倒装芯片，包括：
基板；
层压在所述基板上的电极焊盘层；
层压在所述电极焊盘层的两侧末端的钝化层；
层压在所述电极焊盘层及所述钝化层上的UBM(Under Bump Metallurgy)层；
形成在所述UBM层上的凸点，
所述电极焊盘层上未层压所述钝化层的开口的宽度大于所述凸点的宽度；
所述UBM层的两侧末端还包括缓冲层，用于分散接合时施加到凸点的力；
形成于所述UBM层的两侧末端的所述缓冲层之间的开口的宽度也大于所述凸点的宽度，
所述缓冲层朝向所述凸点的对向面形成为阶梯形状。
2.根据权利要求1所述的倒装芯片，
还包括：层压在所述基板与所述电极焊盘层之间的多层图案层。
3.根据权利要求2所述的倒装芯片，
所述多层图案层上形成用于与其他金属层连接的导孔(via)。
4.根据权利要求1所述的倒装芯片，
所述电极焊盘层及所述钝化层的厚度为0.35um以上。
5.根据权利要求1所述的倒装芯片，
所述凸点包括金。
6.根据权利要求1所述的倒装芯片，
所述电极焊盘层上未层压所述钝化层的开口为四角形、圆形及八角形形状中的任意一个形状，
所述凸点为圆形及四角形中的任意一个形状。
7.根据权利要求1所述的倒装芯片，
所述缓冲层是聚酰亚胺。
8.根据权利要求1所述的倒装芯片，
所述基板是使用CMOS工艺的硅片。
CN201710430817.6A 2016-06-14 2017-06-09 倒装芯片 Active CN107507809B (zh)

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CN109148389B (zh) * 2018-07-11 2020-02-07 上海华虹宏力半导体制造有限公司 温度循环测试时阻止产生裂纹的器件和工艺方法
CN116387270A (zh) * 2019-06-11 2023-07-04 群创光电股份有限公司 电子装置
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TWI774218B (zh) * 2021-01-28 2022-08-11 欣興電子股份有限公司 金屬凸塊結構及其製作方法與驅動基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310699A (en) * 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
JP2006245288A (ja) * 2005-03-03 2006-09-14 Casio Micronics Co Ltd バンプの形成方法及び半導体装置
CN103325760A (zh) * 2012-03-22 2013-09-25 矽品精密工业股份有限公司 形成于半导体基板上的导电凸块及其制法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209210A (ja) * 1997-01-20 1998-08-07 Sharp Corp 半導体装置及びその製造方法並びにその検査方法
US6448171B1 (en) * 2000-05-05 2002-09-10 Aptos Corporation Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
US7053490B1 (en) * 2005-07-27 2006-05-30 Semiconductor Manufacturing International (Shanghai) Corporation Planar bond pad design and method of making the same
JP2007273624A (ja) * 2006-03-30 2007-10-18 Fujitsu Ltd 半導体装置及びその製造方法
JP2008016514A (ja) 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
TWI419242B (zh) * 2007-02-05 2013-12-11 Chipmos Technologies Inc 具有加強物的凸塊結構及其製造方法
US9466579B2 (en) * 2007-07-26 2016-10-11 Nxp B.V. Reinforced structure for a stack of layers in a semiconductor component
KR20090015760A (ko) 2007-08-09 2009-02-12 삼성전기주식회사 패키지 제조방법
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310699A (en) * 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
JP2006245288A (ja) * 2005-03-03 2006-09-14 Casio Micronics Co Ltd バンプの形成方法及び半導体装置
CN103325760A (zh) * 2012-03-22 2013-09-25 矽品精密工业股份有限公司 形成于半导体基板上的导电凸块及其制法

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